CN110445493A - A kind of data collection synchronous device and method based on FPGA TDC - Google Patents
A kind of data collection synchronous device and method based on FPGA TDC Download PDFInfo
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- CN110445493A CN110445493A CN201910588356.4A CN201910588356A CN110445493A CN 110445493 A CN110445493 A CN 110445493A CN 201910588356 A CN201910588356 A CN 201910588356A CN 110445493 A CN110445493 A CN 110445493A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
- H03M1/0624—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by synchronisation
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/10—Calibration or testing
- H03M1/1071—Measuring or testing
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
- H03M1/1245—Details of sampling arrangements or methods
- H03M1/1255—Synchronisation of the sampling frequency or phase to the input frequency or phase
Abstract
A kind of data collection synchronous device and method based on FPGA TDC, device include: sampling module (1), generate sample point data for carrying out analog-to-digital conversion according to analog waveform of the sampling clock to input；Receiving module (2), for receiving sample point data according to work clock, wherein work clock is divided by sampling clock and generated after trigger signal arrival；Time delay chain (3), for being delayed to trigger signal；Latch module (4), trigger signal when arriving for clock rising edge at work, after latching delay；Coding module (5), the trigger signal after delay for calculating latch and the time interval between work clock rising edge；Synchronization module (6) moves point synchronization for carrying out according to time interval to sample point data.By the time interval of the first job rising edge clock after measurement trigger signal and triggering, the synchronism deviation of more analog input cards due to caused by the phase difference between work clock can be eliminated.
Description
Technical field
This disclosure relates to data processing field, and in particular, to a kind of data collection synchronous device based on FPGA TDC
And method.
Background technique
Acquire mainly is realized with triggering unanimously by sample clock frequency, phase between holding different acquisition board more at present
Board is synchronous.In order to achieve this, clock and triggering can be fanned out to other acquisitions by mainboard using an analog input card as mainboard
Board；Special clock can also be used with triggering board to ensure that all analog input cards keep synchronous completely.It is fanned out to using clock
Chip can produce the sampling clock of multiple synchronizations, be supplied to each analog input card by almost the same cabling or driving, in addition,
Trigger signal is also fanned out to all analog input cards to guarantee to acquire simultaneously.
The analog-digital converter (Analog-to-Digital Converter, ADC) of analog input card is in each sampling period pair
Waveform is digitized and is generated a sample point data, then is spread out of sample point data by adc data interface.In order to reduce
Adc data clock frequency, ADC are passed using Double Data Rate (Double Data Rate, DDR) and more data-interfaces (Demux)
Transmission of data is to reduce adc data clock.In the analog input card of high-speed, high precision, general use site programmable gate array
(Field-Programmable Gate Array, FPGA) receives processing data, and FPGA work clock is by ADC sampling clock
Repeatedly frequency dividing generates, and therefore, FPGA work clock there is a possibility that a variety of phases.For multiple analog input cards, FPGA work
Making the phase difference of clock, to result in sampled point in each data clock cycle unjustified, even if each analog input card receives simultaneously
Trigger signal, the sample point data that each analog input card uploads can be also deviated, this is that institute is unacceptable in reconfiguration waveform.
Therefore, more analog input card high speed acquisitions are synchronous other than sampling clock is synchronous with triggering, it is also necessary to consider FPGA work clock phase
Synchronism deviation caused by potential difference is different.
Summary of the invention
(1) technical problems to be solved
Present disclose provides a kind of data collection synchronous device and methods based on FPGA TDC, utilize data collection synchronous
In device FPGA realize time-to-digit converter (Time-to-Digital Converter, TDC), with measure trigger signal with
The time interval of first FPGA work clock rising edge after triggering, and eliminate due to the phase difference between FPGA work clock
The synchronism deviation of caused more analog input cards.
(2) technical solution
Present disclose provides a kind of data collection synchronous device based on FPGATDC, comprising: sampling module is used for basis
Sampling clock carries out analog-to-digital conversion to the analog waveform of input and generates sample point data；Receiving module, for being arrived in trigger signal
After coming, sample point data is received according to work clock, wherein the work clock is divided by the sampling clock and generated；Delay
Chain, for being delayed to the trigger signal；Latch module, for latching institute when the work clock rising edge arrives
Trigger signal after stating delay；Coding module, trigger signal after delay and the work clock for calculating the latch
Time interval between rising edge；Synchronization module, for move point together to the sample point data according to the time interval
Step.
Optionally, the data collection synchronous device further include: broadening module, for broadening the trigger signal, so that
Trigger signal after the broadening within a preset range, and is transmitted to described prolong by the width of the trigger signal after obtaining the broadening
When chain.
Optionally, the data collection synchronous device further include: control module, for judging whether the time interval is full
Sufficient preset condition, and when the time interval meets the preset condition, the synchronization module is controlled according between the time
It is synchronized every carrying out shifting point to the sample point data.
Optionally, the time delay chain is made of one or more delay unit, the trigger signal successively pass through described in prolong
Shi Danyuan is delayed.
Optionally, the latch module is made of one or more trigger, each corresponding institute of the delay unit
State trigger, for the work clock rising edge arrive when, to the trigger signal by delay unit delay after
Trigger signal is latched, and the time interval is equal to prolonging for the corresponding delay unit of trigger signal after the delay of the latch
The sum of when.
Optionally, the maximum delay of the time delay chain is not less than the period of the work clock.
Optionally, the synchronization module calculates the ratio of the time interval and sampling clock cycle, and according to the ratio
The sample point data is carried out to move point synchronization.
Optionally, the shifting point is synchronous for when moving back, the synchronous points of point of moving are equal to the time interval and sampling
The ratio of clock cycle；It is that the shifting point is synchronous to count equal to the period of the work clock when moving forward that the shifting point is synchronous
The ratio of difference and sampling clock cycle between the time interval.
The disclosure additionally provides a kind of data collection synchronous method, comprising: S1, according to sampling clock to the analog wave of input
Shape carries out analog-to-digital conversion and generates sample point data, and divides to obtain work clock to sampling clock；S2 arrives in trigger signal
Afterwards, sample point data is received according to work clock；S3 is delayed to the trigger signal；S4 rises in the work clock
When along arrival, the trigger signal after latching the delay；S5, trigger signal and the work after calculating the delay of the latch
Time interval between rising edge clock；S6 carries out the sample point data according to the time interval to move point synchronization.
Optionally, the step S6 includes: the first ratio for calculating the time interval and sampling clock cycle, moves back institute
Sample point data is stated, points is moved back and is equal to first ratio；Or between the period and the time of the calculating work clock
Difference between, and the second ratio of the difference and sampling clock cycle is calculated, move forward the sample point data, and move forward point
Number is equal to second ratio.
(3) beneficial effect
The data collection synchronous device and method that the disclosure provides has the advantages that
(1) it solves ADC sampling clock frequency dividing and generates more collection plates caused by the FPGA work clock of a variety of possibilities
Stationary problem between card thus reduces setting for FPGA to make FPGA that tick-over clock be selected also to be able to satisfy internal timing
Meter requirement, logical design difficulty and power consumption；
(2) synchronization between more analog input cards can be realized in the internal logic design for being based only upon FPGA, does not need additional hard
Part design, to use the device and method and original system without hardware modifications, it is succinct accurate.
Detailed description of the invention
Fig. 1 diagrammatically illustrates the structural block diagram of the data collection synchronous device of embodiment of the present disclosure offer.
Fig. 2 diagrammatically illustrates the application scenarios block diagram of the data collection synchronous device of embodiment of the present disclosure offer.
Fig. 3 diagrammatically illustrates the working sequence signal between the different data acquisition synchronizing device of embodiment of the present disclosure offer
Figure.
Before the sample point data shifting point that Fig. 4 A diagrammatically illustrates multiple analog input cards of embodiment of the present disclosure offer synchronizes
Schematic diagram.
After the sample point data shifting point that Fig. 4 B diagrammatically illustrates multiple analog input cards of embodiment of the present disclosure offer synchronizes
Schematic diagram.
Fig. 5 diagrammatically illustrates the flow chart of the data collection synchronous method of embodiment of the present disclosure offer.
Description of symbols:
1- sampling module；2- receiving module；3- time delay chain；4- latch module；5- coding module；6- synchronization module；7- exhibition
Wide module；8- control module.
Specific embodiment
For the purposes, technical schemes and advantages of the disclosure are more clearly understood, below in conjunction with specific embodiment, and reference
The disclosure is further described in attached drawing.
First embodiment of the present disclosure provides a kind of data collection synchronous device, refering to fig. 1, right in conjunction with Fig. 2 to Fig. 4
Fig. 1 shown device is described in detail.
Refering to fig. 1, data collection synchronous device includes sampling module 1, receiving module 2, time delay chain 3, latch module 4, compiles
Code module 5, synchronization module 6, broadening module 7 and control module 8.
Sampling module 1 is used to carry out analog-to-digital conversion according to analog waveform of the sampling clock to input to generate sample point data.
Receiving module 2 is used for after trigger signal Trigger arrival, is connect according to the work clock of data collection synchronous device
Receive sample point data, wherein work clock obtains after being divided by sampling clock.
Broadening module 7 is for broadening trigger signal, so that the width of the trigger signal after broadening is within a preset range, uses
Delay transport can be carried out in the width of guarantee trigger signal, the trigger signal after broadening is also transmitted to delay by broadening module 7
Chain 3.
Time delay chain 3 is for being delayed to the trigger signal after broadening, the delay unit that can be demarcated by one or more
It is sequentially connected composition, trigger signal successively passes through delay unit and is delayed.The maximum delay of time delay chain 3 is not less than work clock
Period, before guaranteeing that the next rising edge of work clock arrives, the delay of trigger signal is not finished in time delay chain 3.Triggering
Transmission range of the signal in time delay chain can characterize time interval.
Trigger signal when latch module 4 arrives for clock rising edge at work, after latching delay.Latch module 4 by
One or more trigger composition, each delay unit corresponding trigger are right when arriving for clock rising edge at work
Trigger signal by delay unit delay after trigger signal latched.To include that N number of delay unit is in time delay chain 3
Example, for a certain trigger signal, when clock rising edge arrives when operating, which may be merely through time delay chain 3
In preceding M delay unit, wherein 1≤M < N, when latch module 4 latches the trigger signal after delay unit delay, M+1 to the
No signal exports in N number of delay unit, at this point, the trigger signal after delay is latched in latch module 4 in preceding M trigger,
M+1 is not latched into signal into n-th trigger.
Coding module 5 was used to calculate between the trigger signal after the delay latched and the time between work clock rising edge
It is equal to the sum of the delay of the corresponding delay unit of trigger signal after the delay latched every, the time interval, for above-mentioned example,
The time interval is equal to the sum of the delay of preceding M delay unit in time delay chain 3.
Control module 8 is for judging that whether effectively (i.e. data valid) above-mentioned time interval, that is, judges the time interval
Whether preset condition is met.Preset condition is, for example, the period that the time interval is less than work clock, when time interval is less than work
When making the period of clock, the time interval is effective, and synchronization module 6 is in normal operating conditions, i.e. synchronization module 6 can be according to this
Time interval carries out sample point data to move point synchronization；Otherwise the time interval is invalid, and synchronization module 6 cannot be to sample point data
It carries out moving point synchronization.In addition, control module 8 can be also used for the resetting of data collection synchronous device.
Synchronization module 6 is used for according to the time interval being calculated in coding module 5 to the sampling number in receiving module 2
According to carrying out shifting point.Specifically, synchronization module 6 calculates the ratio of time interval and sampling clock cycle, and according to the ratio to adopting
Sampling point data carry out shifting point.When moving point to move back, the ratio that points a little are equal to time interval and sampling clock cycle is moved, when
When moving point to move forward, the difference and sampling clock cycle being equal between the period and time interval of work clock of counting a little is moved
Ratio.By taking sampling clock is 1GHz, work clock is 125MHz as an example, the period of sampling clock cycle 1ns, work clock are
8ns, it is assumed that time interval 5ns, if synchronization module 6 using moving back, moves points=5ns/1ns=5 a little, synchronization module 6 will
Sample point data in receiving module 2 moves back at 5 points；If synchronization module 6 moves points=8ns-5ns/1ns=a little using Forward
3, synchronization module 6 moves forward the sample point data in receiving module 2 at 3 points.
Data collection synchronous device in the embodiment of the present disclosure can be by first job clock after trigger signal and triggering
The time interval of rising edge accurately measures, and measurement accuracy meets the resolution requirements in a sampling period in 60ps or so.
Referring to Fig.2, the data in the embodiment of the present disclosure are acquired same by taking the high speed acquisition system based on PXIe platform as an example
Step device is arranged in the analog input card of Fig. 2, and the sampling clock between each analog input card is consistent with trigger signal, and the disclosure is implemented
Data collection synchronous device is mainly used for solving in each analog input card since the phase difference between FPGA work clock causes in example
More analog input card synchronism deviations.ADC model used in analog input card is, for example, ADC12D1000, is quantified with 12bit
Precision and 1GSPS sample rate, the ADC is configurable using two data-interfaces (i.e. DId and DI) and using ddr mode, at this time
The frequency of adc data clock DCLK is 250MHz, and by adc data clock DCLK frequency dividing as in data collection synchronous device
FPGA work clock DIV_DCLK, to reduce power consumption and reduce logical design difficulty, at this point, the frequency of FPGA work clock is
125MHz.In this example, FPGA receives 8 sampled points in each operating clock cycle, however since ADC sampling clock 8 divides
Frequency obtains work clock and there is a possibility that 8 kinds of phases, since the received sampled point of each operating clock cycle of FPGA acquires the moment
Related to FPGA work clock phase, leading to the sample point data moment maximum deviation of different acquisition board is 7 sampling periods.
In order to be aligned the sample point data of more analog input cards in time, it is same to need to obtain data acquisition in each analog input card
Walk the phase difference between the FPGA work clock of device.It, can be with respectively adopting when the received trigger signal of each analog input card is consistent
Collect the FPGA in the data collection synchronous device of board and realizes TDC to measure first FPGA after trigger signal and triggering and work
The time interval of rising edge clock, when time interval difference is the FPGA work of data collection synchronous device in each analog input card
The phase difference of clock.The phase difference of FPGA work clock is equal to sample point data Time of day offsets between each analog input card, in data
When processing according to the phase difference between FPGA work clock can the more analog input cards of Accurate align the sample point data moment.
In the present embodiment, by taking two analog input cards in the high speed acquisition system based on PXIe platform as an example, illustrate this two
The working sequence of a analog input card.Refering to Fig. 3, in the present embodiment, still adopted with the sampling clock SCLK of above-mentioned ADC for 1GHz, ADC
With two data-interface DId and DI and using for DDR technology.The frequency of adc data clock DCLK is 250MHz, the two
The FPGA work clock of data collection synchronous device is respectively DIV_DCLK_1 and DIV_DCLK_2 in analog input card.Trigger signal
After Trigger arrives, first group of data that the analog input card 1 of first data acquisition synchronizing device receives are D1~D8, the
First group of data that the analog input card 2 of two data acquisition synchronizing devices receives are D5~D12, two data collection synchronous dresses
The time interval of first FPGA work clock rising edge after setting trigger signal and triggering is respectively T1And T2.Due to sampling
Clock cycle is 1ns, according to T1And T2Value be calculated and need to the sample point data of analog input card 1 and analog input card 2 difference
Move back 3.5 and 7.5 sampled points.Being rounded herein is 3 and 7 sampled points, and the sample point data of two analog input cards can be realized
It synchronizes in time, is achieved in the precise synchronization of the two data collection synchronous devices.
In the present embodiment, by taking four analog input cards in the high speed acquisition system based on PXIe platform as an example, illustrate this number
The effect of more analog input card precise synchronizations is realized according to acquisition synchronizing device.After dividing four for the sine wave one that signal source exports in input
It states in four analog input cards, since the sampling clock of each analog input card and triggering are consistent, this four analog input cards are adopted
The waveform of collection is consistent, but due to the phase difference of data collection synchronous device work clock in each analog input card, after triggering
The sample point data of upload is unjustified in time, if not carrying out shifting point to the sample point data of upload, four obtained are acquired
The corresponding waveform of the sample point data of board is as shown in Figure 4 A, the corresponding waveform point ratio of the sample point data of this four analog input cards
For figure 1, figure 2, figure 3 and figure 4；To measure first number after obtaining trigger signal and triggering in four analog input cards
For being respectively 2ns, 3ns, 6ns and 7ns according to the time interval of acquisition synchronizing device FPGA work clock rising edge, if utilizing this
Public data acquisition synchronizing device carries out shifting point to the sample point data that analog input card uploads, and needs respectively to adopt each analog input card
Sampling point data move back 2,3,6,7 sampled points, the corresponding waveform of the sample point data of four obtained analog input cards such as Fig. 4 B institute
Show, the corresponding waveform minute of sample point data after this four analog input cards shifting points is than being figure 1 ', figure 2 ', figure 3 ' and figure
4 ', move the image hotpoint that different acquisition board reconstructs after putting precise synchronization.Comparison diagram 4A and 4B, it can be seen that disclosure number
Sample point data is carried out after moving point according to acquisition synchronizing device, the precise synchronization of more analog input cards may be implemented.
In addition it is also necessary to which explanation, for above-mentioned multiple analog input cards, should be used uniformly the mode moved forward or backward
The data uploaded to each analog input card carry out shifting point, and the data that cannot be uploaded to a part of analog input card move forward, to another
The data that a part of analog input card uploads are moved back.
The second embodiment of the present disclosure shows a kind of data collection synchronous method, and refering to Fig. 5, method includes following operation.
S1 carries out analog-to-digital conversion according to analog waveform of the sampling clock to input and generates sample point data, and to sampling
Clock division obtains work clock.
S2 receives sample point data according to work clock after trigger signal arrival.
S3 is delayed to trigger signal.
Firstly, broadening trigger signal, to guarantee that the width of trigger signal can carry out delay transport.
Then, it is delayed to the trigger signal after broadening, and not to the maximum delay ability of the trigger signal after broadening
Less than the period of work clock.
S4, trigger signal when clock rising edge arrives at work, after latching delay.
When work clock rising edge arrives, the delay of certain time is carried out to trigger signal, it is assumed that delay time is
M is operated in S4, is latched to the trigger signal after delay M.
S5, the time interval between the trigger signal after calculating the delay of latch and work clock rising edge.
It operates in S5, the time interval between the trigger signal after the delay of latch and work clock rising edge is equal to touching
It signals the time being delayed, such as equal to the time M in operation S4.
S6 carries out sample point data according to time interval to move point synchronization.
Operation S6 be divided to for two kinds of situations: moving back a little or to the point that moves forward.
When selection moves back, needs to calculate the first ratio of time interval and sampling clock cycle, move back sampling number
According to, move back points be equal to the first ratio.
It selects to when Forward, needs to calculate the difference between the period of work clock and time interval, and calculate the difference
Second ratio of value and sampling clock cycle, move forward sample point data, and Forward points are equal to the second ratio.
In conclusion the data collection synchronous device and method that the disclosure provides mainly is realized on FPGA, utilize
FPGA realizes TDC to measure the time interval of trigger signal with first FPGA work clock rising edge after triggering, and passes through this
A little time intervals (are located at multiple to eliminate multiple data collection synchronous devices caused by phase difference between FPGA work clock
In analog input card) synchronism deviation.
Particular embodiments described above has carried out further in detail the purpose of the disclosure, technical scheme and beneficial effects
Describe in detail it is bright, it is all it should be understood that be not limited to the disclosure the foregoing is merely the specific embodiment of the disclosure
Within the spirit and principle of the disclosure, any modification, equivalent substitution, improvement and etc. done should be included in the guarantor of the disclosure
Within the scope of shield.
Claims (10)
1. a kind of data collection synchronous device based on FPGA TDC, comprising:
Sampling module (1) generates sample point data for carrying out analog-to-digital conversion according to analog waveform of the sampling clock to input；
Receiving module (2), for receiving the sample point data according to work clock, wherein described after trigger signal arrival
Work clock is divided by the sampling clock and is generated；
Time delay chain (3), for being delayed to the trigger signal；
Latch module (4), for the trigger signal when the work clock rising edge arrives, after latching the delay；
Coding module (5), the trigger signal after delay for calculating the latch and between the work clock rising edge
Time interval；
Synchronization module (6) moves point synchronization for carrying out according to the time interval to the sample point data.
2. data collection synchronous device according to claim 1, wherein the data collection synchronous device further include:
It broadens module (7), for broadening the trigger signal, so that the width of the trigger signal after the broadening is in default model
In enclosing, and the trigger signal after the broadening is transmitted to the time delay chain (3).
3. data collection synchronous device according to claim 1, wherein the data collection synchronous device further include:
Control module (8), for judging whether the time interval meets preset condition, and described in meeting in the time interval
When preset condition, controls the synchronization module (6) and the sample point data is carried out according to the time interval to move point synchronization.
4. data collection synchronous device according to claim 1, wherein the time delay chain (3) is prolonged by one or more
Shi Danyuan composition, the trigger signal are successively delayed through the delay unit.
5. data collection synchronous device according to claim 4, wherein the latch module (4) is by one or more
Trigger composition, each corresponding trigger of the delay unit, is used for when the work clock rising edge arrives, right
The trigger signal by delay unit delay after trigger signal latched, the time interval is equal to the latch
The sum of the delay of the corresponding delay unit of trigger signal after delay.
6. data collection synchronous device according to claim 1, wherein the maximum delay of the time delay chain (3) is not less than
The period of the work clock.
7. data collection synchronous device according to claim 1, wherein the synchronization module (6) calculated between the time
Every the ratio with sampling clock cycle, and the sample point data is carried out according to the ratio to move point synchronization.
8. data collection synchronous device according to claim 7, in which: the synchronous shifting point is shifting point when moving back
Synchronous points are equal to the ratio of the time interval and sampling clock cycle；The synchronous shifting point is shifting point when moving forward
Synchronous points are equal to the ratio of difference and sampling clock cycle between the period and the time interval of the work clock.
9. a kind of data collection synchronous method, comprising:
S1 carries out analog-to-digital conversion according to analog waveform of the sampling clock to input and generates sample point data, and to sampling clock
Frequency dividing obtains work clock；
S2 receives the sample point data according to the work clock after trigger signal arrival；
S3 is delayed to the trigger signal；
S4, the trigger signal when the work clock rising edge arrives, after latching the delay；
S5, the time interval between trigger signal and the work clock rising edge after calculating the delay of the latch；
S6 carries out the sample point data according to the time interval to move point synchronization.
10. data collection synchronous method according to claim 9, wherein the step S6 includes:
The first ratio for calculating the time interval and sampling clock cycle, moves back the sample point data, moves back points and is equal to
First ratio；Or
The difference between the period of the work clock and the time interval is calculated, and calculates the difference and sampling clock week
The second ratio of phase, move forward the sample point data, and Forward points are equal to second ratio.
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| CN112362088A (en) * | 2020-12-11 | 2021-02-12 | 中国石油大学(华东) | Synchronous acquisition method and system for multi-grating data |
| CN112597097A (en) * | 2020-12-28 | 2021-04-02 | 济南浪潮高新科技投资发展有限公司 | ADC data acquisition card of PXIE interface, application method and medium thereof |
| CN114564073A (en) * | 2022-02-24 | 2022-05-31 | 山东浪潮科学研究院有限公司 | Method for synchronizing trigger signals between boards of quantum measurement and control system |
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| CN111707852A (en) * | 2020-06-29 | 2020-09-25 | 济南浪潮高新科技投资发展有限公司 | Method, device, equipment and storage medium for synchronizing signals of multi-channel waveform generator |
| CN112362088A (en) * | 2020-12-11 | 2021-02-12 | 中国石油大学(华东) | Synchronous acquisition method and system for multi-grating data |
| CN112597097A (en) * | 2020-12-28 | 2021-04-02 | 济南浪潮高新科技投资发展有限公司 | ADC data acquisition card of PXIE interface, application method and medium thereof |
| CN114564073A (en) * | 2022-02-24 | 2022-05-31 | 山东浪潮科学研究院有限公司 | Method for synchronizing trigger signals between boards of quantum measurement and control system |
| CN114564073B (en) * | 2022-02-24 | 2023-05-16 | 山东浪潮科学研究院有限公司 | Method for synchronizing trigger signals between boards of quantum measurement and control system |
| CN116578166A (en) * | 2023-07-12 | 2023-08-11 | 国仪量子(合肥)技术有限公司 | Synchronous trigger data acquisition method, storage medium and acquisition equipment |
| CN116578166B (en) * | 2023-07-12 | 2023-09-22 | 国仪量子(合肥)技术有限公司 | Synchronous trigger data acquisition method, storage medium and acquisition equipment |
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