CN106253902B - The multi-channel parallel acquisition system of identification calibration function is resetted with more device synchronizations - Google Patents
The multi-channel parallel acquisition system of identification calibration function is resetted with more device synchronizations Download PDFInfo
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- CN106253902B CN106253902B CN201610852029.1A CN201610852029A CN106253902B CN 106253902 B CN106253902 B CN 106253902B CN 201610852029 A CN201610852029 A CN 201610852029A CN 106253902 B CN106253902 B CN 106253902B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/10—Calibration or testing
- H03M1/1009—Calibration
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/1205—Multiplexed conversion systems
- H03M1/123—Simultaneous, i.e. using one converter per channel but with common control or reference circuits for multiple converters
Abstract
The invention discloses a kind of multi-channel parallel acquisition systems that identification calibration function is resetted with more device synchronizations, in the N number of ADC and FPGA module of multi-channel parallel acquisition system, 1st FPGA module issues the reset operation that reset signal completes ADC and DCM according to system reset initial order, generates the datamation clock CCLK inside stable FPGA1；2nd separately includes a synchronous identification module to n-th FPGA module and resets control module, synchronous identification module is adjusted the length of delay of the datamation clock of a upper FPGA module, identification is synchronized to the datamation clock of this FPGA and a upper FPGA using deserializer and sequence detection module, length of delay when will be synchronous is as time interval, then reset signal is adjusted to the length of delay of corresponding A DC and Clock Managing Unit according to time interval, is corrected to complete more device synchronizations and reset identification.Using present invention can ensure that reset accuracy, so that the phase relation of multi-channel data work clock after each synchronous reset be made to be determining.
Description
Technical field
The invention belongs to ultra-high-speed data acquisition technical fields, more specifically, are related to a kind of with more device synchronizations
Reset the multi-channel parallel acquisition system of identification calibration function.
Background technique
With the fast development of science and technology, the complexity of signal increasingly increases, the requirement to the sample rate of acquisition system also by
It is cumulative to add, due to the restriction of monolithic ADC (Analog-to-Digital Converter analog-digital converter) chip sample rate, only
The sample rate of system can be improved by the way of parallel acquisition.And way more popular at present is to utilize time-interleaved modulus
Conversion (TIADC) technology improves the sample rate of system.However the system of more device parallel acquisitions is difficult to do due to reset signal
To it is complete while reset, to frequently can lead to follow-up data split incorrect for then this reset signal asynchronous, finally leads
High sampling rate index is caused to cannot achieve.Moreover, the phenomenon uses the more framework sides FPGA more ADC because of the further promotion of sample rate
Formula becomes to be more and more obvious, and has seriously affected the stability of system realization.
In Practical Project, in order to enable the synchronised clock of external high-speed ADC output can satisfy FPGA (Field-
Programmable Gate Array, field programmable gate array) the speed of service, need to synchronised clock make one frequency dividing
Reduction of speed processing, and the operation generally uses DCM (Digital Clock Manager, Clock management list inside FPGA
Member) clock is performed corresponding processing.Then it influences to reset simultaneously operating just to include the reset of ADC and the reset of DCM.And cause
There are two the reason of resetting asynchronous operation is main: the not easy to control and reset signal and sampling clock of reset signal delay are not
Homology, it is multiple just at will lead in the metastable zone of sampling clock that the two reasons all may cause reset signal
There is indeterminacy phenomenon in phase behind position, may finally cause the incorrect of data split.
In multi-channel parallel acquisition system, including N group ADC module and FPGA module.N piece ADC is simultaneously to from channel
Data carry out corresponding acquisition operation, according to the adjustment to sampling clock phase, the acquisition data SD that will be obtained1..., SDNIt passes
It is defeated to be received accordingly to respective fpga chip.Fig. 1 is the ultrahigh speed parallel acquisition system principle frame of the more FPGA of more ADC
Figure.As shown in Figure 1, each FPGA is to its reset signal source RST, according to reset clock CLKRSTGenerate two-way reset signal RSTADC
And RSTDCM, it is sent respectively to corresponding ADC chip and DCM module.For ADC chip, in reset signal RSTADCIt reaches
Later, ADC chip can be according to one data sampling synchronizing clock signals homologous with sampling clock SCLK of generation at the time of reset
DCLK is sent to DCM module.By taking the time relationship of four frequency dividings as an example, the clock phase of the sampling synchronization clock signal DCLK of generation
Relationship is up to 4 kinds of situations.Fig. 2 is the clock phase relational graph of the lower four kinds of issuable DCLK of four frequency dividings.It is eliminated in Fig. 2
The analysis of device inside inherent delay illustrates 4 kinds of possible clock phase relationships.Further, in ultra-high-speed data acquisition
In order to be the work clock CCLK for meeting FPGA internal operation speed data sampling synchronizing clock signals DCLK reduction of speed in system,
It then needs through DCM (Clock Managing Unit) according to reset signal RSTDCMTo execute corresponding reduction of speed operation.Reduction of speed operation will
The CCLK that out of phase can be generated eventually leads to the synchronizing sequence uncertain problem of multi-channel parallel data.
If expanding to increasingly complex situation, the multi-channel parallel formed for N group ADC module and FPGA module is acquired
System, if respective sampling clock has all carried out the operation that M times divides, then at most can produce M × N kind situation, and
This also considerably increases the uncertainty of data split sequence.And in practical application, situation can be more complicated, because adopting
There is also many uncertain shake sections around the rising edge of sample clock sclk, i.e., described metastable zone in engineering design
Between, if reset signal acts on this section, also result in the final uncertainty for resetting result.So being in these sections
Forbid carrying out reset operation to TIADC system.Furtherly, since the edge of any clock signal all has this metastable state
Section, so any result resetted is all likely located at its any one section of front and back, these various reasons cause, right
It needs to carry out special processing in the reset operation of ADC chip.
More ADC existing at present, which reset synchronization processing method, mainly to be had: hardware synchronization repositioning and reset method of identification.The former
Reset signal is generated using the work clock homologous with sampling clock, then delays to reach each ADC and DCM device through what is known
Part so that meeting corresponding stablize resets required section, and then generates stable synchronized result, the i.e. fixation of parallel data
Ordinal relation.This method is shown in periodical literature, Analysis on multiple-component synchronization of
ultra-fast time-interleaved analog-to-digital conversion systems and its
Novel parameterized hardware solution, REVIEW OF SCIENTIFIC INSTRUMENTS,
2014.05.The latter carries out any operation to the reset of each ADC and DCM, using external High-precision time interval measurement device pair
The data processing clock CCLK of each reduction of speed output carries out phase difference identification two-by-two to determine after resetting as a result, adjusting in turn
The ordinal relation of corresponding sampled data.This method is shown in that document " adopt by Chinese patent, CN201110389013, a kind of more adc datas
The synchronous identification device of the data of collecting system, 2011.11.30 ".Both methods can solve the problems, such as more ADC synchronous resets,
But required hardware is more complex or debugging process is relatively complicated, is difficult effectively to be realized in practical projects.And
They are influenced by temperature larger, and temperature once changes the phase that will lead to correct and deviates again, increase and reset not
Deterministic risk.
Summary of the invention
It is an object of the invention to overcome the deficiencies of the prior art and provide one kind, and there are more device synchronizations to reset identification correction
The multi-channel parallel acquisition system of function, by datamation clock in each FPGA module in multi-channel parallel acquisition system
CCLK is accurately identified, and generates corresponding reset signal delay control, so that the multichannel number after each synchronous reset
Phase relation according to work clock CCLK is determining, to guarantee the synchronous correctness of Back end data.
For achieving the above object, the multi-channel parallel that there are the present invention more device synchronizations to reset identification calibration function is adopted
The value range of collecting system, including N group ADC module and FPGA module, N is N >=2, and wherein ADC module is in signal condition channel
Signal be acquired, acquisition data are sent to FPGA module, to generate data synchronous for reset signal based on the received for ADC module
Clock signal DCLK；It include Clock Managing Unit, serioparallel exchange module, data memory module and data processing mould in FPGA module
Block, Clock Managing Unit generate the datamation clock inside FPGA according to reset signal and data synchronizing clock signals DCLK
CCLK is sent to trigger module and data memory module；Serioparallel exchange module will acquire data and carry out serioparallel exchange, after conversion
Parallel acquisition data be sent to data memory module；Data memory module is under datamation clock control to parallel acquisition number
According to being cached；Data processing module is sent to subsequent module after being handled from reading data in data memory module；
Include resetting to generate A module in 1st FPGA module, resets and generate A module for received reset signal RST1Into
Reset signal RST is obtained after row branchADC1And RSTDCM1, it is transmitted to inside the 1st ADC module and the 1st FPGA module respectively
Clock Managing Unit；
2nd into n-th FPGA module, and a reset control module and synchronous identification mould is respectively configured in each FPGA module
Block, resetting control module includes resetting generate B module, reset synchronization module, delay control A module and delay control B module；The
In i FPGA, i=2,3 ..., N reset generation B module and open after the reset signal for receiving identification control module generates instruction
Begin to generate reset signal RSTi；Synchronization module is resetted to receive in the FPGA that Clock Managing Unit generates in (i-1)-th FPGA module
Portion clock CCLKi-1, according to CCLKi-1To reset signal RSTiIt synchronizes, obtains synchronous reset signal RSTi', it is sent respectively to
Delay control A module and delay control B module；Delay control A module is to synchronous reset signal RSTi' according to length of delay ΔAiInto
Row delay obtains reset signal RSTADCiIt is sent to i-th of ADC module；Delay control B module is to synchronous reset signal RSTi' press
According to length of delay ΔBiPostponed to obtain reset signal RSTDCMiIt is sent to the Clock Managing Unit of i-th of FPGA module；
The length of delay Δ of delay control A module and delay control B module in i-th of FPGAAiAnd ΔBiIn multi-channel parallel
Acquisition system is successively determined by the synchronization identification module of each FPGA according to FPGA serial number when initializing, synchronous identification module packet
Include delay control C module, deserializer, sequence detection module and identification control module, the specific works of each module are as follows:
The length of delay of delay control A module, delay control B module and delay control C module is set to by identification control module
0, the transmission reset signal generation instruction of B module is generated to resetting, then according to predetermined period to the length of delay of delay control C module
ΔCiCarry out periodical setting, the length of delay of moment tδ indicates the increase step-length of delay control, monitors simultaneously
The level signal that sequence detection module is sent then continues to adjust Δ if it is inactive levelCi, otherwise by current delay value ΔCiMake
For clock CCLKiWith clock CCLKi-1The time interval of phase differenceIdentify control module according toNext step operation is carried out, point
For three kinds of situations:
IfWherein σ indicates the uncertainty of datamation clock edge shake, then current delay value ΔAiWith
ΔBiIt determines；
IfTSCLKIndicate the period of sampling clock, identification control module enables length of delayTCCLKIndicate the period of datamation clock, length of delay ΔBiIt is constant, then re-start synchronization
Identification obtains time CCLKiWith clock CCLKi-1The time interval of phase difference
IfIdentification control module enables length of delay ΔBi=ΔBi+TSCLK, length of delay ΔAiIt is constant, then
It re-starts synchronous identification and obtains time CCLKiWith clock CCLKi-1The time interval of phase difference
Delay control C module receives the FPGA internal clocking that Clock Managing Unit generates in (i-1)-th FPGA module
CCLKi-1, according to length of delay ΔCiClock CCLK ' after being postponedi-1It is sent to deserializer；
Deserializer receives the FPGA internal clocking CCLK of Clock Managing Unit output in i-th of FPGAi, after carrying out K frequency multiplication
To clock CCLK ' after delayi-1It unstrings, the Serial No. to unstring is sent to sequence detection module；
Sequence detection module detects received Serial No., if testing result is clock CCLK ' after delayi-1
With clock CCLKiIt is synchronous, significant level is exported to identification control module, otherwise exports inactive level to identification control module.
The multi-channel parallel acquisition system that there are the present invention more device synchronizations to reset identification calibration function, in multi-channel parallel
In the N number of ADC and FPGA module of acquisition system, the 1st FPGA module is complete according to system reset initial order sending reset signal
It is operated at the reset of ADC and DCM, generates the datamation clock CCLK inside stable FPGA1；2nd to n-th FPGA module
In each FPGA module, separately include a synchronous identification module and reset control module, synchronous identification module passes through first
Adjustment is adjusted the length of delay of the datamation clock of a upper FPGA module, using deserializer and sequence detection module pair
The datamation clock of this FPGA and upper FPGA synchronizes identification, and length of delay when will synchronize is as time interval, so
Afterwards according to the length of delay of time interval adjustment reset signal to corresponding A DC and Clock Managing Unit, to complete more device synchronizations
Reset identification correction.Using present invention can ensure that reset accuracy, to make multi-channel data work after each synchronous reset
It is determining for making the phase relation of clock CCLK.
Detailed description of the invention
Fig. 1 is the ultrahigh speed parallel acquisition system principle diagram of the more FPGA of more ADC；
Fig. 2 is the clock phase relational graph of the lower four kinds of possible DCLK of four frequency dividings；
Fig. 3 is that there are the present invention more device synchronizations to reset the specific reality for identifying the multi-channel parallel acquisition system of calibration function
Apply mode structure chart；
Fig. 4 is the timing diagram of more ADC synchronous reset processes between adjacent FPGA.
Fig. 5 is the timing diagram of phase difference identification process between adjacent C CLK.
Specific embodiment
A specific embodiment of the invention is described with reference to the accompanying drawing, preferably so as to those skilled in the art
Understand the present invention.Requiring particular attention is that in the following description, when known function and the detailed description of design perhaps
When can desalinate main contents of the invention, these descriptions will be ignored herein.
Embodiment
Fig. 3 is that there are the present invention more device synchronizations to reset the specific reality for identifying the multi-channel parallel acquisition system of calibration function
Apply mode structure chart.As shown in figure 3, the multi-channel parallel that there are the present invention more device synchronizations to reset identification calibration function acquires system
System includes N group ADC and FPGA module, and the value range of N is N >=2.
ADC module is acquired the analog signal in conditioning channel, and the data of acquisition are sent to corresponding FPGA mould
The serioparallel exchange module 2 of block.
Comprising at Clock Managing Unit (DCM) 1, serioparallel exchange module 2, data memory module 3 and data in FPGA module
Module 4 is managed, each module is described as follows:
The data sync clock signal DCLK (frequency-dividing clock of sampling clock) of the received ADC module of Clock Managing Unit 1
The internal operation clock CCLK of FPGA is obtained after carrying out scaling down processing, is sent to data memory module 3.
Serioparallel exchange module 2 will acquire data and carry out serioparallel exchange, and the parallel acquisition data after conversion are sent to data
Memory module 3.
Data memory module 3 delays parallel acquisition data under the control of datamation clock and storage control signal
It deposits.
Data processing module 4 is sent to subsequent module from being read after data are handled in data memory module 3, such as after
Continuous aggregation of data processing and control module, System Control Center etc..
In the present invention, it is provided with reset in the 1st FPGA module and generates A module 5, resets and generate A module 5 from rear module
Receive reset signal RST1, by reset signal RST1Reset signal RST is obtained after carrying out branchADC1And RSTDCM1, it is transmitted to respectively
1 (DCM of Clock Managing Unit inside 1st ADC module and the 1st FPGA module1), the 1st ADC module is according to reset signal
RSTADC1Generate data sync clock signal DCLK1, by the sampling synchronization clock signal DCLK of generation1It is sent to the 1st FPGA mould
1 (the DCM of Clock Managing Unit of block1), then by the Clock Managing Unit 1 of the 1st FPGA module according to reset signal RSTDCM1Point
Frequency obtains the datamation clock CCLK inside FPGA1, Clock Managing Unit 1 removes work clock CCLK1It is sent to data storage
Outside module 3, it is also necessary to while being sent to the control C module 71 of the delay in the 2nd FPGA module and resetting synchronization module 72.
2nd into n-th FPGA module, increases a reset control module 6, including resets and generate B module 61, resets
Synchronization module 62, delay control A module 63 and delay control B module 64；Wherein, it resets synchronization module 62 and receives reset signal
RSTi, i=2,3 ..., N, the work clock CCLK sent according to (i-1)-th modulei-1To reset signal RSTiSynchronize place
Reason, obtains synchronizing rear reset signal RSTi', branch is sent to delay control A module 63 and delay control B module 64.Delay control
A module 63 processed is according to length of delay ΔAiADC is obtained after being postponediReset signal RSTADCi, it is sent to i-th of ADC module.
Delay control B module 63 is according to length of delay ΔBiCorresponding 1 (DCM of Clock Managing Unit is obtained after being postponedi) reset signal
RSTDCMi, the Clock Managing Unit 1 that is sent in i-th of FPGA module.
It can be seen that in the present invention according to the explanation of the above modules, in order to guarantee the certainty of storing data sequence,
Length of delay ΔAiAnd ΔBiSetting be its key, it is ensured that reset signal RSTiSampling clock is not at after synchronized and delay
Signal SCLKiWith data sync clock DCLKiMetastable zone in.Due to actual reset signal RSTiIn length of delay ΔAiWith
ΔBiOn the basis of be also superimposed the delay of hardware itself, and the length of delay of different hardware designs is different, and the value is not easy to survey
It measures, traditional verification method is to determine whether to reach metastable mesh by the data combined result after test of many times
, but the highly reliable purpose that automatically corrects, and different hardware cloth linear systems cannot be fully achieved in this kind of test judgement method
System (especially FPGA internal wiring) there is different realization processes, be highly detrimental to the reliable realization of system.Therefore this hair
It is bright the 2nd into n-th FPGA module, also increase separately and be configured with a synchronous identification module 7, it is multiple for determining in the FPGA
The length of delay Δ of position control module 6AiAnd ΔBi.The mutual cooperation of the two modules could complete the more ADC of whole system and reset synchronization
Automatically correct purpose.
In the initialization of multi-channel parallel high speed acquisition system, the 1st FPGA module is first according to RST1Complete ADC1And DCM1
Reset, then the 2nd to n-th FPGA module in sequence successively by its synchronize identification module 7 it is resetted in control module 6
Delay control A module 63 and delay control the corresponding length of delay Δ of B module 64AiAnd ΔBiIt is determined.In order to preferably say
Reset control module 6 and synchronous identification module 7 in the bright present invention, first to length of delay ΔAiAnd ΔBiSetting principle said
It is bright.
Fig. 4 is the timing diagram of more ADC synchronous reset processes between adjacent FPGA.As shown in figure 4, SCLKiIndicate ADCiMould
The sampling clock of block, RSTi' indicate the reset signal after resetting synchronization module 62 and synchronizing.CCLKi-1It is (i-1)-th ADCi-1With
DCM in FPGA modulei-1In RSTi-1Work clock of the data generated under signal function inside FPGA.It is assumed that the present embodiment
In clock division multiple in each ADC module be 4, DCM clock division multiple be 2.RSTi' delayed control A module again
63 postpone Δ with delay control B module 64 respectivelyAiAnd ΔBiAfterwards, i-th of reset signal RST after being postponedADCiWith
RSTDCMi.When there are different length of delays, the result that the two reset signals are acted on may be different.Such as RSTi' undergoing
ΔAi(1) RST after postponingADCiIn non-SCLK rising edge r2Metastable zone between when, be labeled as RSTADCi(1), i-th of ADC
Module is resetted according to the reset signal, meets SCLKiRising edge r2The useful signal at moment generates data sync clock letter
Number DCLKi(1)；Conversely, such as RSTi' in experience ΔAi(2) RST after postponingADCiIn SCLKiRising edge r2Metastable zone between
When, it is labeled as RSTADCi(2), i-th of ADC module is resetted according to the reset signal, is in SCLKiRising edge r2It is metastable
State state may generate data sync clock signal DCLKi(1) or DCLKi(2), and the phase difference of the two clocks is corresponding
Time interval (time corresponding to phase difference between two rising edge clocks) isTSCLKIndicate the week of sampling clock
Phase.At this point, the two DCLK are in same RSTDCMiCCLK may be occurred by acting on lower CCLKi(1) or CCLKi(3) two kinds of feelings
The time interval of condition, their phase differences is also
Similarly, it is assumed that in RSTADCi(1) stable DCLK has been produced under acting oni(1), then RSTi' in experience ΔBi(1) prolong
The RST to lagDCMiIn non-DCLKi(1) rising edge t6Metastable zone between when, be labeled as RSTDCMi(1), i-th of DCM according to
The reset signal is resetted, and DCLK is meti(1) rising edge t6The action condition at moment generates datamation clock signal
CCLKi(1)；Conversely, such as RSTi' in experience ΔBi(2) RST after postponingDCMiIn DCLKi(1) rising edge t6Metastable zone
Between when, be labeled as RSTDCMi(2), i-th of DCM is resetted according to the reset signal, is in DCLKi(1) rising edge t6It is metastable
State state may generate data sync clock signal CCLKi(1) or CCLKi(2), and the phase difference of the two clocks is corresponding
Time interval isTDCLKIndicate the period of data sync clock, T in the present embodimentDCLK=4TSCLK。
Section near each hopping edge of sampling clock SCLK, data sync clock DCLK and data work clock CCLK
There are between metastable zone, the uncertainty that datamation clock edge is shaken is denoted as σ, and (uncertainty is obtained by historical data
, measured in the present invention with phase difference corresponding time interval when the uncertainty of datamation clock jitter), then
In the reseting procedure of ADC and DCM, if reset signal is on the edge of these clocks, it is possible to cause to reset not true
Qualitative phenomenon.The present invention is using 7 couples of result CCLK resetted of synchronous identification modulei-1With CCLKiThe phase difference of clock is known
Not, then again with the phase difference result of identificationWithFeedback control length of delay Δ againAiAnd ΔBi。
In synchronous identification module 7, with deserializer according to CCLKiClock signal removes the CCLK that unstringsi-1Clock signal, so that it may
It can obtain different results.As shown in figure 5, between adjacent C CLK phase difference identification process timing diagram, the figure hypothesis unstring
The multiple K that unstrings of device is 4.
As shown in figure 5, the DCLK obtained under ADC reset casei(1) CCLK corresponding toi(1) result is according to CCLKiWhen
Clock signal removes the CCLK that unstringsi-1Clock signal, the Serial No. after unstringing are regularly repeating failing edge sequence 1 ... 1100 ....
And the DCLK obtained under ADC reset casei(2) result corresponding to is CCLKi(1) postpone a TSCLKClock CCLKi
(3), the Serial No. after unstringing is irregular failing edge sequence 3, or ... 1100 ..., or ... 1000 ..., or ... 1101 ...,
Or ... 1001 ....
No matter how both CCLK phase differences change, and postpone the Δ of control C module 71 by adjustingCiValue can be converted
For with CCLKi-1Fully synchronized reset result CCLKi(S).In the synchronous case, the result of unstringing of deserializer, which is changed into, does not advise
Failing edge sequence S then, or ... 0110 ..., or ... 1110 ..., or ... 0100 ..., or ... 1100 ..., these sequences can be used as
CCLK′i-1With clock CCLKiSynchronous flag sequence can determine whether to reach synchronous by Sequence Detection.Set by note system
Ratio T between the SCLK clock set and CCLK clock cycleCCLK/TSCLK=Q, it is clear that Q=8 in Fig. 5.It is with situation shown in Fig. 5
Example, such as CCLKi-1Delay ΔCiIt is set in section { (8z+1) TSCLK-σ,(8z+1)TSCLK+ σ } in, z is nonnegative integer, then
In CCLKi(1) the result sequence 1 of unstringing of state will be changed into CCLKi(S) the sequence S of state.Similarly, when being in
CCLKi(2) reset is as a result, the Serial No. after then unstringing is regularly repeating rising edge sequence 2 ... 0011 ....At this point, if
CCLKi-1Delay ΔCiIt is set in section { (8z+5) TSCLK-σ,(8z+5)TSCLK+ σ } in, then it is in CCLKi(2) state
Result of unstringing sequence 2 will be changed into CCLKi(S) the sequence S of state.When in CCLKi(4) reset is as a result, then unstring
Serial No. afterwards is irregular rising edge sequence 4, or ... 0110 ..., or ... 0010 ..., or ... 0111 ..., or ...
0011….At this point, if CCLKi-1Delay ΔCiIt is set in section { (8z+6) TSCLK-σ,(8z+6)TSCLK+ σ } in, then it is in
CCLKi(2) the result sequence 2 of unstringing of state will be changed into CCLKi(S) the sequence S of state.
Above four kinds of situations, when the Serial No. after unstringing is changed into sequence S for the first time, if ΔiIt further increases,
Then it is changed into the correlated series (in addition to sequence S) of intermediate state again, but in ΔCiIt is further increased to 8TSCLK, then again second turn
Become sequence S.Therefore, sequence S is known as the useful signal of failing edge, for determining CCLKi-1With CCLKiWhether in completely same
Step state.Then, the delay according to corresponding to the useful signal for receiving failing edge for the first time controls 71 regulated value Δ of C moduleCi
(1), so that it may obtain the phase difference of two CCLKAnd then pass through setting delay control A module 63 and delay control B module 64
Corresponding length of delay ΔAiAnd ΔBi, reset signal RST is issued by identification control module 74 againiMore ADC can be completed to reset
The synchronous correction of process.
Based on principles above, it is known that more ADC reset synchronization when the initialization of multi-channel parallel high speed acquisition system in the present invention
The specific works of identification and modules in correction course are as follows:
The specific work process of synchronous identification module 7 are as follows:
I-th of FPGAiIn, delay is controlled A module 63 first, prolonged by the identification control module 74 in synchronous identification module 7
Control B module 64 and the length of delay for postponing control C module 71 are set to 0 late, refer to resetting to generate B module transmission reset signal and generate
It enables, then according to predetermined period to the length of delay Δ of delay control C module 71CiCarry out periodical setting, the length of delay of moment tδ indicates that delay controls be can increase minimum step.73 real-time monitoring deserializer 72 of sequence detection module
Serial No. after conversion just exports inactive level if the sequence generated is specific regular (asynchronous), and otherwise output has
It imitates level (synchronization).The level signal that 74 monitoring data sequent detection unit of identification control unit is issued, the Δ if inactive leveli
A δ is continued growing, otherwise by current delay value ΔCiAs clock CCLKiWith clock CCLKi-1The time interval of phase difference
Stop that delay period is arranged.According to principle explanation before it is found that shouldEliminate the path delay of two CCLK clocks
Influence.
Deserializer 72 receives CCLK when unstringing to increase the precision of recognition sequenceiAfter carried out K frequency multiplication, then adopt again
With the signal after frequency multiplication to CCLKi-1Signal after delay unstrings, and resulting sequence is just by parallel K parallel-by-bit number
Word sequence composition, here it is assumed that high-order data are first in time sequencing.Thus judge the CCLK to be unstringedi-1Signal
In CCLKiRising edge state or failing edge shape are under a cycle (from rising edge to the time interval of next rising edge)
State and its phase difference between them.
Reset the specific work process of control module 6 are as follows:
Complete (i-1)-th ADCi-1It after reset, remains unchanged, then issues i-th of ADCiReset signal RSTi；Pass through
Synchronous reset module 7 detects CCLKiAnd CCLKi-1Between phase difference time intervalTo adjust delay control 63 He of A module
The length of delay Δ of delay control B module 64AiAnd ΔBi。ΔAiAnd ΔBiMethod of adjustment are as follows:
IfWherein σ indicates the uncertainty of time interval, then current delay value ΔAiAnd ΔBiIt determines；
IfIdentification control module enables length of delayLength of delay
ΔBiIt is constant, then re-start synchronous identification and obtain time CCLKiWith clock CCLKi-1The time interval of phase difference
IfIdentification control module enables length of delay ΔBi=ΔBi+TSCLK, length of delay ΔAiIt is constant, then
It re-starts synchronous identification and obtains time CCLKiWith clock CCLKi-1The time interval of phase difference
That is, whenever adjustment time lag of first order value ΔAiOr ΔBiAfterwards, it needs to re-start a subsynchronous identification, obtains
Time intervalThen time interval is rejudgedUntil
The multi-channel parallel acquisition system that there are the present invention more ADC to reset synchronous identification and calibration function, multichannel simultaneously
In the N number of ADC and FPGA module of row acquisition system, the 1st ADC and FPGA module are issued according to system reset initial order and are resetted
Signal completes the reset operation of ADC and DCM, generates stable CCLK1, as the work clock of FPGA internal data processing, together
When be sent to the 2nd ADC and FPGA module；2nd each FPGA module into n-th ADC and FPGA module separately includes one
A synchronous identification module 7 and reset control module 6.Synchronous identification module 7 initializes the length of delay of three delay control modules, hair
Synchronous reset signal RST outi, then gradually setting delay controls C module 71, completes the detection and knowledge of data sequence after unstringing
Not, and according to recognition result the length of delay for setting delay control A module 63 and delay control B module 64 again, until CCLKi-1
And CCLKiReach synchronous result.In CCLKi-1With CCLKiAfter synchronizing, corresponding CCLKiIt send into next FPGA module,
The operation for executing synchronous identification and correction again, until submodule all in system all completes the synchronous reset function of more ADC.
According to the course of work of synchronous identification and correction it is found that the method used in the present invention is since 0 according to default
Step-size change length of delay ΔCi, to the effective CCLK obtained under each length of delayi-1Signal uses K times of CCLKiThe clock of frequency into
Capable processing of unstringing, is detected according to the data sequence unstringed, to judge CCLK according to the length of delayi-1And CCLKiIt is
It is no to be in synchronous regime, suitable length of delay Δ is finally setAAnd ΔBTo achieve the purpose that synchronous correction.
As can be seen that other than the 1st FPGA module, other the 2nd when the initialization of multi-channel parallel high speed acquisition system
To n-th FPGA module, successively by the length of delay of 6 pairs of synchronous identification module therein delay control C modules 71 carry out identification and
Setting.In two adjacent FPGA modules, previous FPGA module is equivalent to main FPGA, the latter FPGA module be equivalent to from
FPGA, from FPGA according to the synchronous reset signal RST from FPGA of the data sync clock signal CCLK of main FPGA, according to synchronization
The delayed control A module 63 of reset signal afterwards is resetted with delay control B module 64 to from the corresponding ADC and DCM of FPGA.
In this way, it when there is the case where asynchronous state resets and parallel data is caused to misplace, can be identified by synchronous
It is corrected with the device for resetting control to synchronize, to guarantee the correctness of parallel data sequence.
Although the illustrative specific embodiment of the present invention is described above, in order to the technology of the art
Personnel understand the present invention, it should be apparent that the present invention is not limited to the range of specific embodiment, to the common skill of the art
For art personnel, if various change the attached claims limit and determine the spirit and scope of the present invention in, these
Variation is it will be apparent that all utilize the innovation and creation of present inventive concept in the column of protection.
Claims (1)
1. a kind of multi-channel parallel acquisition system for resetting control with synchronous correction function with more devices, including N group ADC module
And FPGA module, the value range of N is N >=2, and wherein ADC module is acquired the signal in signal condition channel, will acquire
Data are sent to FPGA module, and reset signal generates data sync clock signal DCLK to ADC module based on the received；FPGA module
In include Clock Managing Unit, serioparallel exchange module, data memory module and data processing module, Clock Managing Unit according to answer
Position signal and data synchronizing clock signals DCLK generate the datamation clock CCLK inside FPGA, are sent to data storage mould
Block；Serioparallel exchange module will acquire data and carry out serioparallel exchange, and the parallel acquisition data after conversion are sent to data storage mould
Block；Data memory module caches parallel acquisition data under datamation clock control；Data processing module is from data
It is read in memory module after data are handled and is sent to subsequent module；It is characterized by:
Include resetting to generate A module in 1st FPGA module, resets and generate A module for received reset signal RST1Carry out branch
After obtain reset signal RSTADC1And RSTDCM1, the clock pipe that is transmitted to inside the 1st ADC module and the 1st FPGA module respectively
Manage unit；
2nd into n-th FPGA module, and a reset control module and synchronous identification module is respectively configured in each FPGA module,
Resetting control module includes resetting generate B module, reset synchronization module, delay control A module and delay control B module；I-th
In FPGA, i=2,3 ..., N reset generation B module and start after the reset signal for receiving identification control module generates instruction
Generate reset signal RSTi；It resets synchronization module and receives the datamation that Clock Managing Unit generates in (i-1)-th FPGA module
Clock CCLKi-1, according to CCLKi-1To reset signal RSTiIt synchronizes, obtains synchronous reset signal RSTi', it is sent respectively to prolong
Control A module and delay control B module late；Delay control A module is to synchronous reset signal RSTi' according to length of delay ΔAiIt carries out
Delay obtains reset signal RSTADCiIt is sent to i-th of ADC module；Delay control B module is to synchronous reset signal RSTi' according to
Length of delay ΔBiPostponed to obtain reset signal RSTDCMiIt is sent to the Clock Managing Unit of i-th of FPGA module；
The length of delay Δ of delay control A module and delay control B module in i-th of FPGAAiAnd ΔBiIt is acquired in multi-channel parallel and is
It is successively determined by the synchronization identification module of each FPGA according to FPGA serial number when system initialization, synchronous identification module includes delay
Control C module, deserializer, sequence detection module and identification control module, the specific works of each module are as follows:
The length of delay of delay control A module, delay control B module and delay control C module is set to 0 by identification control module, to
It resets and generates the transmission reset signal generation instruction of B module, then according to predetermined period to the length of delay Δ of delay control C moduleCi
Carry out periodical setting, the length of delay of moment tδ indicates the increase step-length of delay control, while monitoring sequence
The level signal that column detection module is sent then continues to adjust Δ if it is inactive levelCi, otherwise by current delay value ΔCiAs
Clock CCLKiWith clock CCLKi-1The time interval of phase differenceIdentify control module according toNext step operation is carried out, is divided into
Three kinds of situations:
IfWherein σ indicates the uncertainty of datamation clock edge shake, then current delay value ΔAiAnd ΔBiReally
It is fixed；
IfTSCLKIndicate the period of sampling clock, identification control module enables length of delayTCCLKIndicate the period of datamation clock, length of delay ΔBiIt is constant, then re-start synchronization
Identification obtains time CCLKiWith clock CCLKi-1The time interval of phase difference
IfIdentification control module enables length of delay ΔBi=ΔBi+TSCLK, length of delay ΔAiIt is constant, then again into
The synchronous identification of row obtains time CCLKiWith clock CCLKi-1The time interval of phase difference
Delay control C module receives the datamation clock CCLK that Clock Managing Unit generates in (i-1)-th FPGA modulei-1, press
According to length of delay ΔCiClock CCLK ' after being postponedi-1It is sent to deserializer；
Deserializer receives the datamation clock CCLK of Clock Managing Unit output in i-th of FPGAi, carry out K frequency multiplication after to delay
Clock CCLK ' afterwardsi-1It unstrings, the Serial No. to unstring is sent to sequence detection module；
Sequence detection module detects received Serial No., if testing result is clock CCLK ' after delayi-1With when
Clock CCLKiIt is synchronous, significant level is exported to identification control module, otherwise exports inactive level to identification control module.
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