CN109088635A - A kind of multichannel clock synchronous - Google Patents
A kind of multichannel clock synchronous Download PDFInfo
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- CN109088635A CN109088635A CN201810817572.7A CN201810817572A CN109088635A CN 109088635 A CN109088635 A CN 109088635A CN 201810817572 A CN201810817572 A CN 201810817572A CN 109088635 A CN109088635 A CN 109088635A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
- H03M1/1245—Details of sampling arrangements or methods
- H03M1/1285—Synchronous circular sampling, i.e. using undersampling of periodic input signals
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/1205—Multiplexed conversion systems
- H03M1/123—Simultaneous, i.e. using one converter per channel but with common control or reference circuits for multiple converters
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- Synchronisation In Digital Transmission Systems (AREA)
Abstract
The present invention provides a kind of multichannel clock synchronous, including signal source, power divider, N number of acquisition procedure array and signal processing storage device, N is more than or equal to 1；It is divided into the identical simulation clock signal in the road N after signal source output continuous analog clock signal ingoing power distributor, the road N simulation clock signal respectively enters acquisition procedure array, acquisition procedure array is using the simulation clock signal that receives as sampling clock, the externally input sensor signal of synchronous acquisition, externally input sensor signal is converted into digital signal, frequency reducing is carried out to digital signal, down-sampled and data bit width adjustment handles to obtain digital physical quantity, later, digital physical quantity is exported to signal processing storage device, signal processing storage device stores the multi-path digital physical quantity of acquisition respectively, and multi-path digital physical quantity is identified, comprehensive analysis, and then obtain the corresponding external environment general token of digital physical quantity.
Description
Technical field
The present invention relates to multichannel clock field of synchronization, and in particular to a kind of multichannel clock synchronous.
Background technique
Clock Synchronization Technology is widely used in departments such as industry, scientific research, national defence, space flight, by provide timing with
Simultaneous techniques requires to provide different sampling rate and working frequency according to different equipment and instruments, to guarantee every equipment energy
It is enough to work in correct clock edge.With the development of the information processing technology, the requirement to data acquisition is also higher and higher.Single-pass
Road analog-digital converter (AD) sampling has been unable to meet the industry requirements such as communication, instrument, radar, electronic warfare, and this facilitate multichannels
The tremendous development and progress of high-speed AD synchronous sampling technique.
Synchronization just refers between two or more signals, certain particular kind of relationship, i.e., two are kept in frequency or phase
A or more than two signals are maintained within the allowed band of agreement in corresponding significant instant, phase difference or difference on the frequency.
Establishing synchronous purpose is in order to which its time or frequency are distributed to institute's synchronization in need in communication network as timing reference signal
Network element device and business.Synchronous to be divided into Frequency Synchronization and time synchronization again, wherein time synchronization is also referred to as Phase synchronization.Frequency
The particular kind of relationship for referring to and keeping certain stringent in frequency or phase between signal is synchronized, corresponding significant instant is with unified
Mean Speed occurs, to maintain equipment to run with identical rate.And time synchronization is in addition to requiring the signal time having the same
Interval, also wants the starting point of seeking time identical.
Relatively on the low side to the synchronous Research Literature of clock at present, the clock synchronization scheme of use has certain limitation,
It is such as synchronous between clock realizing plate by the way of exporting trigger signal from plate using mainboard, the method may be implemented between plate when
Clock is synchronous, but mainboard and synchronous from cannot keep clock between plate；It is same using high-frequency clock distribution chip design multichannel clock
Walk acquisition method, but this method controling circuit structure is complicated, while multichannel AD array veneer can not be used alone, flexibility compared with
Difference；Multiple external clock reference inputs, are allocated, and select the clock source of highest priority according to clock source accuracy priority
It as input clock, while also needing specially to design Clock management interface board, the method not only increases the hardware cost of system, together
When master control borad when being used alone, it is also necessary to carry out complicated hardware modifications, flexibility and adaptability are poor.
Summary of the invention
Technology of the invention solves the problems, such as: compared with the prior art, providing a kind of multichannel clock synchronous acquisition system
System, so that circuit structure is simple, point of no master/slave board is easily installed debugging；Simultaneity factor scalability and adaptability are good.
The technical solution of the invention is as follows: a kind of multichannel clock synchronous, which includes signal source, function
Rate distributor, N number of acquisition procedure array and signal processing storage device, N are more than or equal to 1；
Wherein, it is divided into the identical simulation in the road N after signal source output continuous analog clock signal ingoing power distributor
Clock signal, the road N simulation clock signal respectively enter acquisition procedure array, acquire simulation clock of the procedure array to receive
Externally input sensor signal is converted into counting by signal as sampling clock, the externally input sensor signal of synchronous acquisition
Word signal handles to obtain digital physical quantity to digital signal progress frequency reducing, down-sampled and data bit width adjustment, later, digital object
Reason amount is exported to signal processing storage device, and signal processing storage device deposits the multi-path digital physical quantity of acquisition respectively
Storage, and multi-path digital physical quantity is identified, comprehensive analysis, and then obtain the corresponding external environment entirety table of digital physical quantity
Sign.
The system further include: display terminal, the display terminal are connected with the signal processing storage device, read letter
Number processing storage device identification and analyze as a result, and being shown.
Acquisition procedure array is made of M signal acquisition pretreatment unit, and the acquisition pretreatment unit includes clock
Distributor, AD acquisition array and preprocessing module, wherein AD acquisition array is made of the road r AD acquisition channel, and the r is greater than
It is equal to；
Simulation clock signal enters clock distributor, and through the identical clock signal in the clock distributor output road r, AD acquires battle array
In column, the road r AD acquisition channel simultaneously under the driving of the identical clock signal in the road r, to externally input analog sensor signal
Analog-to-digital conversion is synchronized, is become digital signal, and the signal after conversion is exported to preprocessing module, preprocessing module
Down-sampled, filtering is carried out to the digital signal received and data bit width adjustment handles to obtain digital physical quantity output.
The signal acquisition pretreatment unit further includes crystal oscillator and clock selector, and crystal oscillator is used to generate second clock letter
Number, the simulation clock signal of the second clock signal and power divider output is exported after clock selector gates to clock point
Orchestration.
The acquisition procedure array is located on different boards, the input terminal and function of each acquisition procedure array
Wiring delay between rate dispenser output end is equal.
Length of arrangement wire between the output end of the clock distributor and the input terminal of each AD acquisition channel is equal.
The power divider is coaxial-type power divider.
The signal processing storage device includes signal processing module and data memory module, in which:
Signal processing module is using serial digital processing method to the multi-path digital object of the acquisition procedure array input
Reason amount carries out circulation reading, and carries out digital physical quantity identification and more physical quantity convergence analysis, and then obtain digital physical quantity
Corresponding external environment general token information；
Data memory module carries out external environment general token information corresponding to digital physical quantity using serial mode
Storage.
The power divider is coaxial-type power divider.
The signal processing storage device includes signal processing module and data memory module, in which:
Signal processing module is using serial digital processing method to the multi-path digital object of the acquisition procedure array input
Reason amount carries out circulation reading, and carries out digital physical quantity identification and more physical quantity convergence analysis, and then obtain digital physical quantity
Corresponding external environment general token information；
Data memory module carries out external environment general token information corresponding to digital physical quantity using serial mode
Storage.
Preprocessing module includes down-sampled module, filtering interpolation module, bit wide adjustment module.
Down-sampled module, for carrying out down-sampled processing to digital signal；
Digital signal after down-sampled processing is carried out interpolation and uses FIR low-pass filtering by filtering interpolation module；
Digital signal after down-sampled processing is carried out interpolation and uses FIR low-pass filtering by filtering interpolation module；
Bit wide adjusts module, carries out intercepting process to the digital signal invalid bit of filtering output.
The advantages of the present invention over the prior art are that:
(1), the multichannel clock synchronous collection method that the present invention designs, required external component is less, and highly integrated
Change, introducing noise is few, is convenient for site installation test；
(2), the multichannel clock synchronous collection method that the present invention designs, the working quantity in the channel AD can be adjusted flexibly, and
Each channel performance is consistent, can satisfy the use demand under different sampling environment；
(3), each acquisition pretreatment unit that the present invention realizes is identical, and master-slave is not present, and installation and debugging are convenient
Fast, without special mark；
(4), independent acquisition pretreatment unit of the invention can also work normally, using included external crystal-controlled oscillation, when change
The switch direction of clock selector has good adaptability.
Detailed description of the invention
Fig. 1 is a kind of schematic diagram of multichannel clock synchronous provided in an embodiment of the present invention.
Specific embodiment
Exemplary embodiments of the present disclosure are described in more detail below with reference to accompanying drawings.Although the example shown in attached drawing
Property embodiment, it being understood, however, that may be realized in various forms the disclosure and should not be limited by the embodiments set forth herein.
On the contrary, these embodiments are provided to facilitate a more thoroughly understanding of the present invention, and can be complete by the scope of the present disclosure
It is communicated to those skilled in the art.It should be noted that in the absence of conflict, embodiment and embodiment in the present invention
In feature can be combined with each other.
Fig. 1 shows a kind of multichannel clock synchronous structure chart provided in an embodiment of the present invention.Such as Fig. 1 institute
Show, which includes signal source 1, power divider 2, N number of acquisition procedure array
10, signal processing storage device 11 and display terminal 12, N are more than or equal to 1.
Signal source 1 is divided into the identical simulation clock in the road N after exporting continuous analog clock signal ingoing power distributor 2
Signal, the road N simulation clock signal respectively enter acquisition procedure array 10, acquire simulation clock of the procedure array 10 to receive
Externally input sensor signal is converted into counting by signal as sampling clock, the externally input sensor signal of synchronous acquisition
Word signal carries out frequency reducing, down-sampled and data bit width adjustment processing to digital physical quantity, later, digital physics to digital signal
To signal processing storage device 11, signal processing storage device 11 deposits the multi-path digital physical quantity of acquisition respectively for amount output
Storage helps to consult or the off-line analysis of follow-up data is handled, and identified to multi-path digital physical quantity, comprehensive analysis, into
And the corresponding external environment general token of digital physical quantity is obtained, display terminal 12 is connected with the signal processing storage device 11
It connects, read the identification of signal processing storage device 11 and analyzes as a result, simultaneously graphically being shown.When it is implemented, letter
Number source 1 has a good environmental stability, and keep frequency accuracy is less than or equal to 1.5ppm, the waveform of output signal, frequency and
Amplitude is adjustable, and signal output interface can use BNC or SMA mode；Power divider 2 suggests that selecting impedance is 50 ohm normal
With device, realize impedance matching when connecting between device, reduce signal decaying, if while acquire procedure array 10 for pair
Outdoor multisensor syste carries out signal acquisition, it is proposed that selects coaxial-type power divider, scene is convenient using debugging, convenient for behaviour
Make, and the Stability and dependability of system connection can be increased；In addition, the number of channels of 2 output signal of power divider should be big
In the quantity for being equal to signal acquisition pretreatment unit 3, while the letter between power divider 2 and signal acquisition pretreatment unit 3
Number interface uses SMA mode, and signal wire has good electromagnetic shielding action, and screening factor is made to be less than or equal to 0.8 and long
It spends identical；Acquisition procedure array 10 outputs data to signal processing storage device 11 using network interface or CPCI interface mode.
Acquisition procedure array 10 is made of M signal acquisition pretreatment unit 3, and the acquisition pretreatment unit 3 includes
Clock distributor 5, AD acquisition array 8 and preprocessing module 9, wherein AD acquisition array 8 is made of the road r AD acquisition channel 7,
The r is more than or equal to 1；When it is implemented, several signal acquisition pretreatment units 3 should belong to same batch, r phase is effectively ensured
Clock signal identical Deng, 7 sampling rate of AD acquisition channel, that acquisition 3 power consumption of pretreatment unit is equal, crystal oscillator 4 exports is mutually same
The consistency of performance and index；And several signal acquisition pretreatment units 3 need to meet electromagnetic compatibility during installation,
Within the scope of 0.5MHz~5MHz, mains terminals disturbance voltage value peak value is less than 56dB (μ V), and has good heat dissipation characteristics, protects
Use environment temperature is held less than or equal to 40 DEG C；Signal acquisition pretreatment unit 3 need to have independent external power supply interface, meet independent
Power supply requirement when work.
Simulation clock signal enters clock distributor 5, exports the identical clock signal in the road r, AD acquisition through clock distributor 5
In array 8, the road r AD acquisition channel 7 simultaneously under the driving of the identical clock signal in the road r, to externally input analog sensor
Signal synchronizes analog-to-digital conversion, is become digital signal, and the signal after conversion is exported to preprocessing module 9, pre- to locate
Reason module carries out down-sampled, filtering to the digital signal received and data bit width adjustment handles to obtain digital physical quantity output.
The signal acquisition pretreatment unit 3 further includes crystal oscillator 4 and clock selector 6, and crystal oscillator 4 is used to generate second clock
Signal, the simulation clock signal that the second clock signal and power divider 2 export after the gating of clock selector 6 output to when
Clock distributor 5.When acquiring the autonomous working of pretreatment unit 3, clock selector 6 closes the simulation letter from power divider 2
Number channel gates the clock signal from external crystal-controlled oscillation 4；After acquiring the autonomous working of pretreatment unit 3, if you need to restore most
Initial equilibrium state, only need to be by the analog signal channel of 6 gated on power distributor 2 of clock selector, and closes from external crystal-controlled oscillation 4
Clock signal；In this way, low speed signal acquisition had both may be implemented in AD acquisition channel 7, high-speed signal acquisition, while AD also may be implemented
For acquisition channel 7 in high-speed signal acquisition, acquisition rate is adjustable, to meet the requirement of different use environments.
The acquisition procedure array 10 is located on different boards, the input terminal of each acquisition procedure array 10
Wiring delay between 2 output end of power divider is equal.
The output end of the clock distributor 5 is equal with the length of arrangement wire between the input terminal of each AD acquisition channel 7.
Specifically, the circuit structure and parameter of several AD acquisition channels 7 are completely the same.
Preferably, the power divider 2 is coaxial-type power divider.
The signal processing storage device 11 includes signal processing module and data memory module, in which:
The multi-path digital that signal processing module inputs the acquisition procedure array 10 using serial digital processing method
Physical quantity carries out circulation reading, and carries out digital physical quantity identification and more physical quantity convergence analysis, and then obtain digital physics
The corresponding external environment general token information of amount；External environment general token information is either external environment one-dimension information
(temperature, humidity, pressure etc.) is also possible to the multidimensional information (orientation, shape, state etc.) of external environment physical quantity representative.
Data memory module carries out external environment general token information corresponding to digital physical quantity using serial mode
Storage.
Preprocessing module 9 includes down-sampled module, filtering interpolation module, bit wide adjustment module.
Down-sampled module, for carrying out down-sampled processing, drop to digital signal under the premise of keeping signal processing precision
Low subsequent filtering interpolation processing carries out the resources occupation rate of multiplication process.
Digital signal after down-sampled processing is carried out interpolation and uses FIR low-pass filtering by filtering interpolation module；Interpolation
The data bit width exported after filtering processing becomes larger, and the invalid position of high-order portion, does not work, uses to follow-up signal processing
The multichannel clock synchronous collection method that the position present invention designs, required external component is less, and Highgrade integration, introduces environment
Noise is few, is convenient for site installation test, and key components belong to passive device, reduce the spoilage of device；The present invention
The working quantity of the multichannel clock synchronous collection method of design, the channel AD can be adjusted flexibly, and each channel performance is consistent, can
To meet the use demand under different sampling environment, input interface is easy to operate；Each acquisition pretreatment unit that the present invention realizes
It is identical, master-slave is not present, installation and debugging are convenient and efficient, are not in acquisition pretreatment unit without special mark
The phenomenon that positional fault；Independent acquisition pretreatment unit of the invention can also work normally, the external crystal-controlled oscillation carried using device,
Change the switch direction of clock selector, there is good adaptability.
Embodiment described above is the present invention more preferably specific embodiment, and those skilled in the art is in this hair
The usual variations and alternatives carried out in bright technical proposal scope should be all included within the scope of the present invention.
Claims (10)
1. a kind of multichannel clock synchronous, it is characterised in that: including signal source (1), power divider (2), N number of adopt
Collect procedure array (10) and signal processing storage device (11), N is more than or equal to 1；
Wherein, it is divided into the identical mould in the road N after signal source (1) output continuous analog clock signal ingoing power distributor (2)
Quasi- clock signal, the road N simulation clock signal respectively enter acquisition procedure array (10), acquire procedure array (10) to receive
Simulation clock signal as sampling clock, the externally input sensor signal of synchronous acquisition believes externally input sensor
Number it is converted into digital signal, frequency reducing is carried out to digital signal, down-sampled and data bit width adjustment handles to obtain digital physical quantity, it
Afterwards, digital physical quantity is exported to signal processing storage device (11), and signal processing storage device (11) is by the multi-path digital of acquisition
Physical quantity is stored respectively, and is identified to multi-path digital physical quantity, comprehensive analysis, and then it is corresponding to obtain digital physical quantity
External environment general token.
2. a kind of multichannel clock synchronous according to claim 1, it is characterised in that further include: display is eventually
It holds (12), the display terminal (12) is connected with the signal processing storage device (11), reads signal processing storage device
(11) it identifies and analyzes as a result, and being shown.
3. a kind of multichannel clock synchronous according to claim 1, it is characterised in that acquisition pretreatment battle array
Column (10) be made of M signal acquisition pretreatment unit (3), the acquisition pretreatment unit (3) include clock distributor (5),
AD acquires array (8) and preprocessing module (9), wherein AD acquisition array (8) is made of the road r AD acquisition channel (7), the r
More than or equal to 1；
Simulation clock signal enters clock distributor (5), through the identical clock signal in clock distributor (5) output road r, AD acquisition
In array (8), the road r AD acquisition channel (7) under the driving of the identical clock signal in the road r, passes externally input simulation simultaneously
Sensor signal synchronizes analog-to-digital conversion, is become digital signal, and the signal after conversion is exported to preprocessing module
(9), preprocessing module carries out down-sampled, filtering to the digital signal received and data bit width adjustment handles to obtain digital physical quantity
Output.
4. a kind of multichannel clock synchronous according to claim 3, it is characterised in that the signal acquisition
Pretreatment unit (3) further includes crystal oscillator (4) and clock selector (6), and crystal oscillator (4) is used to generate second clock signal, this second
Clock signal and the simulation clock signal of power divider (2) output export after clock selector (6) gating to clock distribution
Device (5).
5. a kind of multichannel clock synchronous according to claim 1, it is characterised in that: the acquisition pretreatment
Array (10) is located on different boards, and the input terminal and power divider (2) of each acquisition procedure array (10) are defeated
Wiring delay between outlet is equal.
6. a kind of multichannel clock synchronous according to claim 1, it is characterised in that: the clock distributor
(5) length of arrangement wire between output end and the input terminal of each AD acquisition channel (7) is equal.
7. a kind of multichannel clock synchronous according to claim 1, it is characterised in that: the power divider
It (2) is coaxial-type power divider.
8. a kind of multichannel clock synchronous according to claim 1, it is characterised in that: the signal processing is deposited
Storage device (11) includes signal processing module and data memory module, in which:
Signal processing module is using serial digital processing method to the multi-path digital object of acquisition procedure array (10) input
Reason amount carries out circulation reading, and carries out digital physical quantity identification and more physical quantity convergence analysis, and then obtain digital physical quantity
Corresponding external environment general token information；
Data memory module stores external environment general token information corresponding to digital physical quantity using serial mode.
9. a kind of multichannel clock synchronous according to claim 1, it is characterised in that: the signal processing is deposited
Storage device (11) includes signal processing module and data memory module, in which: signal processing module uses serial digital processing side
Method carries out circulation reading to the multi-path digital physical quantity of acquisition procedure array (10) input, and carries out digital physical quantity knowledge
Other and more physical quantity convergence analysis analysis, and then obtain external environment general token information corresponding to digital physical quantity；
Data memory module stores external environment general token information corresponding to digital physical quantity using serial mode.
10. a kind of multichannel clock synchronous according to claim 1, it is characterised in that: preprocessing module (9)
Module is adjusted including down-sampled module, filtering interpolation module, bit wide.
Down-sampled module, for carrying out down-sampled processing to digital signal；
Digital signal after down-sampled processing is carried out interpolation and uses FIR low-pass filtering by filtering interpolation module；
Digital signal after down-sampled processing is carried out interpolation and uses FIR low-pass filtering by filtering interpolation module；
Bit wide adjusts module, carries out intercepting process to the digital signal invalid bit of filtering output.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109660258A (en) * | 2018-12-29 | 2019-04-19 | 四川双元智能科技有限公司 | A kind of method, apparatus and system of multichannel synchronousing collection difference sample frequency data |
| CN111077498A (en) * | 2019-11-28 | 2020-04-28 | 北京航天控制仪器研究所 | Synchronous signal acquisition and processing device based on optical fiber hydrophone array |
| CN113704159A (en) * | 2021-09-23 | 2021-11-26 | 明峰医疗系统股份有限公司 | CT detector AD array synchronous acquisition method |
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Application publication date: 20181225 |