CN107104670A

CN107104670A - Many board synchronous collection methods of base when triggering PLL based on pulse

Info

Publication number: CN107104670A
Application number: CN201710165654.3A
Authority: CN
Inventors: 谭荣华; 张印; 孟元文; 李智慧
Original assignee: Chengdu Mingda Electronic Ltd By Share Ltd
Current assignee: Chengdu Mingda Electronic Ltd By Share Ltd
Priority date: 2017-03-20
Filing date: 2017-03-20
Publication date: 2017-08-29

Abstract

The invention discloses many board synchronous collection methods of base when triggering PLL based on pulse, it is that system clock and pulse synchronous triggering signal are trigger signal to realize that many board synchronous high-speeds are gathered to use outside low-speed reference clock.The present invention has abandoned the transmission of High Speed Analog clock signal between traditional many boards, only need to its exterior and the purpose that synchronous high-speed collection can be achieved in low-speed reference clock and synchronous triggering signal is provided, the output clock frequency that system module in board manages circuit by base during control signal line traffic control PLL and synchronous trigger pulse can meet low frequency acquisition system to the utilization of high frequency acquisition system, pulse synchronous triggering signal triggering collection module and the synchronous internal clocking of system module is coordinated to ensure the synchronized relation of system, save the work of later stage algorithm, with very strong adaptability.

Description

Many board synchronous collection methods of base when triggering PLL based on pulse

Technical field

The present invention relates to synchronous technical field, many plates of base when more particularly to triggering PLL based on pulse Card synchronous collection method.

Background technology

In traditional many board synchronization systems, synchronous implementation generally uses following two methods：One is by many Board directly realizes that many boards are synchronous by the outside homologous sampling clock of high speed and synchronous control signal for providing multichannel distribution；Two It is to be based on many board synchronization scenarios of master slave relation.But traditional synchronization system is directed to high frequency sampling, particularly upper Gigahertz Sampling system, be by management circuit according to outside high-frequency clock export sampling clock, synchronous triggering signal and system it is homologous System work clock, sampling clock and synchronous triggering signal are then assigned to by each collection plate by clock and signal SIP dispatcher Sampling clock is being assigned to each acquisition module for the sampling clock that system works by card, each analog input card, is assigned to each collection The sampling clock of module to ensure with the homologous same phase of external sampling clock, to ensure the synchronization of sampling instant, system module passes through Receive synchronous triggering signal to control synchronous extraction data, to ensure the synchronism of numerical portion data.In order to ensure high frequency Clock signal reaches the clock phase, power and identical in quality, the choosing to the design of board, radio frequency connector and cable of each board The requirement taken is high, therefore, and the high-frequency clock of board input, the synchronism of synchronous control signal are the important of influence synchronous acquisition Factor.Traditional implementation synchronization accuracy and sampling performance are relatively low, and the later stage needs to correct by algorithm, and adaptability is not strong.

The content of the invention

It is an object of the invention to provide a kind of base when triggering PLL based on pulse for improving board synchronous acquisition performance Many board synchronous collection methods.

The purpose of the present invention is achieved through the following technical solutions：

Many board synchronous collection methods of base when triggering PLL based on pulse, base and synchronous are touched when PLL is provided with inside board Pulse management circuit, Acquisition Circuit and system module are sent out, it is that system clock and pulse are synchronous to use outside low-speed reference clock Trigger signal is trigger signal to realize that many board synchronous high-speeds are gathered.

Further, the low-speed reference clock by the clock distribution circuit or power splitter of a low speed by low-speed reference Base and synchronous trigger pulse management circuit output multi-channel synchronous are adopted during the PLL that the signal of clock is distributed in each board, board Sample clock, start pulse signal and homologous system work clock.

Further, the pulse synchronous triggering signal is used to ensure each board synchronously sampled data.

The present invention has abandoned the transmission of High Speed Analog clock signal between traditional many boards, it is only necessary to which its exterior provides low Fast reference clock and synchronous triggering signal are that the system module in the purpose that synchronous high-speed collection can be achieved, board is believed by controlling The output clock frequency of base and synchronous trigger pulse management circuit can meet low frequency acquisition system to high frequency during number line traffic control PLL The utilization of acquisition system, coordinates pulse synchronous triggering signal triggering collection module and the synchronous internal clocking of system module to ensure The synchronized relation of system, saves the work of later stage algorithm, with very strong adaptability.

Brief description of the drawings

Fig. 1 is work block diagram of the invention.

Fig. 2 is the connection diagram inside board.

Embodiment

As shown in figure 1, the present invention use, outside low-speed reference clock is system clock and pulse synchronous triggering signal is Trigger signal is to realize that many board synchronous high-speeds are gathered.The clock distribution circuit or simple that low-speed reference clock passes through a low speed Power splitter the signal of low-speed reference clock is distributed to each board, as shown in Fig. 2 base and synchronization when PLL is provided with inside board Base and synchronous trigger pulse management circuit output when trigger pulse manages the PLL in circuit, Acquisition Circuit and system module, board Multi-channel synchronal sampling clock, start pulse signal and homologous system work clock；Pulse synchronous triggering signal is used to protect Demonstrate,prove each board synchronously sampled data.

During work：Base and lock-out pulse management circuit are exported according to the low-speed reference clock of input during PLL inside board System module in the homologous system work clock of multi-channel high-speed sampling clock, start pulse signal and board, board according to Pulse synchronous triggering signal by control signal wire to PLL when base and synchronous trigger pulse management circuit output clock frequency Rate is configured, so as to meet the use of different system.

Described above is only the preferred embodiment of the present invention, but protection scope of the present invention is not limited thereto, any The transformation and replacement carried out based on technical scheme provided by the present invention and inventive concept should all cover the protection model in the present invention In enclosing.

Claims

1. base and synchronous triggering when being provided with PLL when triggering PLL based on pulse inside many board synchronous collection methods of base, board Pulse management circuit, Acquisition Circuit and system module, it is characterised in that：Outside low-speed reference clock is used for system clock and list Impulsive synchronization trigger signal is trigger signal to realize that many board synchronous high-speeds are gathered.

2. many board synchronous collection methods of base during the triggering PLL according to claim 1 based on pulse, its feature exists In：The low-speed reference clock is distributed the signal of low-speed reference clock by the clock distribution circuit or power splitter of a low speed To each board, base and synchronous trigger pulse management circuit output multi-channel synchronal sampling clock, trigger pulse during PLL in board Signal and homologous system work clock.

3. many board synchronous collection methods of base during the triggering PLL according to claim 1 based on pulse, its feature exists In：The pulse synchronous triggering signal is used to ensure each board synchronously sampled data.