CN202394060U

CN202394060U - Merging unit hardware core board based on PowerPC system

Info

Publication number: CN202394060U
Application number: CN2011204792035U
Authority: CN
Inventors: 蒿柯成; 白世军; 曾林翠; 马亮; 白飙
Original assignee: China XD Electric Co Ltd
Current assignee: China XD Electric Co Ltd
Priority date: 2011-11-25
Filing date: 2011-11-25
Publication date: 2012-08-22
Anticipated expiration: 2021-11-25

Abstract

The utility model discloses a merging unit hardware core board based on a PowerPC system. The merging unit hardware core board comprises a processor board and a secondary board; a central processing unit (CPU) and a storage module, a mode selection module and a first power module which are connected with the CPU are arranged on the processor board; and the processor board and the secondary board are spliced through a pin connector. A field programmable gate array (FPGA), a synchronous module, a digital sampling module, an analog sampling module, a point-to-point output module, a serial output module, a plurality of Ethernet modules, a network port debugging module and a second power module are arranged on the secondary board; the FPGA is connected with the synchronous module, the digital sampling module, the analog sampling module, the point-to-point output module, the serial output module, the CPU and the second power module; and the CPU is connected with a plurality of Ethernet modules, the network port debugging module and the FPGA. Through the core board, the problem about coexistence of analog sampling and digital sampling is solved, the problem about timing of a precision clock is solved, and the problem of synchronization difficulty of eight paths of point-to-point output power consumption is solved.

Description

Merge cells hardware core plate based on the PowerPC system

[technical field]

The utility model belongs to field of power electronics, and particularly a kind of merge cells hardware core plate based on the PowerPC system can be applicable in the DA current measurement device of various electric pressures.

[background technology]

The China national grid company proposes " strong intelligent grid " development plan in May, 2009; It is that the strong electrical network that key, at different levels electric network coordination develops is the basis that proposition will be built with the extra-high voltage grid, and its construction plan is divided into three phases: 2009-2010 works study emphasis intelligent grid development plan; 2011-2015 is the all-round construction stage; 2016-2020 is for leading the improvement stage.

Through research of primary equipment intellectualized technology and application; Conscientiously control the running status of primary equipment; The ability of various disasteies is resisted in the access of calm reply new forms of energy, the operational reliability that promotes electrical network and efficient, enhancing, realizes from original break down maintenance, prophylactic repair; Carry out the transition to repair based on condition of component, improve the utilization ratio of primary equipment and reduce maintenance cost, improve the failure message of source of early warning.Electronic mutual inductor comprises collecting unit, merge cells, and as protection, the data source of measuring and controlling equipment, importance is ready to appear!

Along with country to the strategic plan of intelligent grid, emphasis investment with build, will have increasing old station improvement project and occur, require merge cells also can receive analog sampling, analog sampling and digital sample also might occur and deposit.Communicating by letter of bus MU and circuit MU in addition, electronic type PT is with MU and the electronic type CT communication issue with MU.Often all there is difference more or less in each engineering.This just requires merge cells will have allocation plan flexibly.According to actual requirement of engineering and " intelligent substation technology guide rule " Q/GDW383-2009 standard, electronic mutual inductor and merge cells parameters thereof are had higher requirement:

1) each merge cells should be able to satisfy maximum 16 tunnel analog samplings inputs and the sampling of 12 way words.

2) support the IEEE1588v2 precision interval clock to the time agreement.

3) can carry out maximum 15 tunnel serial communication between the merge cells;

4) merge cells should be able to be supported maximum 5 tunnel open into leaving function;

5) merge cells should be able to be supported stipulations such as IEC61850-9-1, IEC61850-9-2, and 8 tunnel point-to-point outputs can flexible configuration when practical applications.

[utility model content]

The purpose of the utility model is to provide a kind of merge cells hardware core plate based on the PowerPC system, solves the newly-built intelligent transformer station and the improvement project of standing always and is combined Elementary Function and the increasingly high requirement of performance.

To achieve these goals, the utility model adopts following technical scheme:

A kind of merge cells hardware core plate based on the PowerPC system comprises processor plate and subplate; Processor plate is provided with CPU and the memory module that is connected CPU, mode selection module, first power module; Peg graft through the contact pin type connector between processor plate and the subplate.

The utility model further improves and is: subplate is provided with FPGA, synchronization module, digital sample module, analog sampling module, point-to-point output module, serial output module, some ethernet modules, network interface debugging module and second source module; FPGA connects synchronization module, digital sample module, analog sampling module, point-to-point output module, serial output module, CPU and second source module; CPU connects some ethernet modules, network interface debugging module and FPGA.

The utility model further improves and is: the model of CPU is MPC8272CZQMIBA.

The utility model further improves and is: the model of FPGA is XC3S1200E-4FG400I.

The utility model further improves and is: the model of analog sampling module is MAX11046.

The utility model further improves and is: the model of point-to-point output module is LXT9785HE.

The utility model further improves and is: the model of synchronization module is DP83640.

The utility model further improves and is: said some ethernet modules comprise first ethernet module and second Ethernet interface that is used for networking when being used for 1588 pairs.

With respect to prior art, the utlity model has following advantage: 1. different engineerings, sample mode, output channel differs greatly, and employing the utility model technical scheme only needs to change corresponding subplate, and is with low cost, solved the upgrading complicacy, the problem of the wasting of resources; 2. the problem that has solved analog sampling and digital sample and deposited; 3. solved the IEEE1588v2 precision interval clock to the time problem; 4. the point-to-point output power consumption of octuple, synchronous difficult problem have been solved.

[description of drawings]

Fig. 1 is the structured flowchart of the utility model merge cells core board.

Fig. 2 is point-to-point output synoptic diagram.

Fig. 3 is an analog sampling part synoptic diagram.

[embodiment]

Below in conjunction with accompanying drawing the utility model is done and to be described in further detail: this core board is that merge cells has proposed a kind of new solution.Not only satisfy the latest requirement that the Power System Intelligent construction is combined the unit.And multiple flexible configuration scheme is provided.Can satisfy various novel transformer substation constructions and old station improvement project.Stable and reliable for performance.

With reference to figure 1, be the framework of the utility model merge cells hardware core plate.Comprise FPGA, CPU, synchronization module, digital sample module, analog sampling module, point-to-point output module, serial output module, ethernet module 1, ethernet module 2, network interface debugging module, memory module, mode selection module and power module.FPGA connects synchronization module, digital sample module, analog sampling module, point-to-point output module, serial output module and CPU, and CPU connects ethernet module 1, ethernet module 2, network interface debugging module, memory module, mode selection module, power module and FPGA.Microprocessor is selected the MPC8272CZQMIBA of the PowerPC of Freescale for use in the utility model.FPGA selects the XC3S1200E-4FG400I of XILINX for use.MAX11046 is selected in analog sampling modules A D conversion for use, and point-to-point output module is selected LXT9785HE for use, 1588 precision interval clocks to the time select DP83640 for use.The utility model core board comprises processor plate and subplate; CPU, mode selection module, memory module and power module are arranged on the processor plate; All the other modules are arranged on the subplate; Subplate is provided with the power module to each module for power supply of subplate, and 4 groups of contact pin type connectors are installed on the processor plate; Processor plate is connected communication with subplate through 4 groups of contact pin type connectors.

The current and voltage signals of a bus samples in the plank, gets into FPGA and carries out verification, parsing, synchronous processing, and packing sends to and does linear difference among the CPU again, considers the drift processing and returns to FPGA according to the IEC61850-9-2 protocol packing then.FPGA authorizes through inner mac and send Point-to-Point Data or send serial data according to the FT3 agreement.Point-to-Point Data is sent in the monitoring and protection equipment through point-to-point output module, as the foundation of switch motion.Serial data is sent in the monitoring and protection equipment through the serial output module, as the foundation of switch motion.

Synchronization module can receive B code optical signal and pulse per second (PPS) light signal; Light signal gets into the light transceiver (model: change into corresponding electric signal HFBR-2412), deliver among the FPGA of synchronization module.

The analog sampling module: simulating signal converts specified small voltage signal to earlier through too small transducer, and (model: max11046) in the chip, this analog sampling module can receive 8 tunnel sampled datas to deliver to the analog sampling module again.The utility model core board has been used two max11046, and shared 16 bit data bus are selected through sheet, can receive 16 digit current voltage signals simultaneously.

Digital sample module:, change into electric signal to the digital quantity sampled signal and deliver among the FPGA through the light mouth.Usually can accept three road electric currents, three road voltage signals.If requirement of engineering can be expanded 4 road receiving interface of optical through other subplates.

Point-to-point module: select the lxt9785 chip for use,, send to light emission port HFBR-1414 by driving 3967 chip drives again the good data difference output of FPGA packing.Can support the point-to-point output of the different mac of octuple address.

The multi-path serial data that serial module: FPGA sends are directly through driving serial module (model: send to monitoring and protection equipment through the light mouth 74ALVC164245).

Ethernet module 1 and 2 passes to the fcc interface among the CPU through the AFBR-5803 receiving optical signals through physical chip lxt971.When two paths of data one tunnel was used for 1588 pairs, the one tunnel was used for networking.

Memory module: comprise the flash stored programme, use by two block cache sdam parallel connection.

Mode selection module: be used to switch debugging mode and practical applications pattern.

Power module (model: MAX1951) 3.3v power supply, 1.5v power supply are provided for core board.

With reference to figure 1 and shown in Figure 2, FPGA receives multi-path digital sampling and analog sampling signal, and the digital sample part adopts HFBR-2412 light mouth to receive, and after the opto-electronic conversion, delivers among the FPGA, and the analog sampling signal through the A/D conversion, is delivered among the FPGA earlier again.FPGA also wants receiving station's segment sync signal, and sampled signal is gone here and there and changed, and synchronous processing is given CPI after separating code check.And receive packet and the FT3 packet of the IEC61850-9 of CPU passback.Point-to-point output is through the mac nuclear control, and lxt9785 sends to HFBR-1414 through Physical layer, through the electric light conversion, sends in protection, the measure and control device with light signal.FPGA sends the FT3 data in addition, sends on the serial transceiver boards through motherboard with difference form.Close through difference, after the electric light conversion, send with light signal.Effective like this signal attenuation and the common mode interference of having suppressed.

With reference to figure 3, analog sampling part synoptic diagram.Electronic mutual inductor collects busbar voltage or current signal through coil, converts 1.5v (measurement passage) to through integrated small transformers earlier, and 150mv (protection passage) delivers in the core board base plate through motherboard again.Select 8 tunnel 16 A/D conversions of MAX11046 chip for use.Tolerance interval is-10V～+ 10V, simplified potential-divider network.Save the plank space, reduced the plank power consumption.

CPU adopts the mpc8272 of PowerPC in the utility model.Carry two independent mac controller, the one tunnel receives the input of GOOSE message, the one tunnel be used for the 1588v2 precision to the time.CPU reads the data that FPGA provides in addition, carries out information modeling according to IEC61850, through twoport ram passback FPGA.Also be responsible for the monitoring sampled signal, work such as drift processing.

Above content is the further explain that combines concrete preferred implementation that the utility model is done; The embodiment that can not assert the utility model only limits to this; Those of ordinary skill for technical field under the utility model; Not breaking away under the prerequisite of the utility model design, can also make some simple deduction or replace, all should be regarded as belonging to claims that the utility model submits to and confirm scope of patent protection.

Claims

1. the merge cells hardware core plate based on the PowerPC system is characterized in that: comprise processor plate and subplate; Processor plate is provided with CPU and the memory module that is connected CPU, mode selection module, first power module; Peg graft through the contact pin type connector between processor plate and the subplate.

2. a kind of merge cells hardware core plate as claimed in claim 1 based on the PowerPC system, it is characterized in that: subplate is provided with FPGA, synchronization module, digital sample module, analog sampling module, point-to-point output module, serial output module, some ethernet modules, network interface debugging module and second source module; FPGA connects synchronization module, digital sample module, analog sampling module, point-to-point output module, serial output module, CPU and second source module; CPU connects some ethernet modules, network interface debugging module and FPGA.

3. a kind of merge cells hardware core plate based on the PowerPC system as claimed in claim 1, it is characterized in that: the model of CPU is MPC8272CZQMIBA.

4. a kind of merge cells hardware core plate based on the PowerPC system as claimed in claim 2, it is characterized in that: the model of FPGA is XC3S1200E-4FG400I.

5. a kind of merge cells hardware core plate based on the PowerPC system as claimed in claim 2, it is characterized in that: the model of analog sampling module is MAX11046.

6. a kind of merge cells hardware core plate based on the PowerPC system as claimed in claim 2, it is characterized in that: the model of point-to-point output module is LXT9785HE.

7. a kind of merge cells hardware core plate based on the PowerPC system as claimed in claim 2, it is characterized in that: the model of synchronization module is DP83640.

8. a kind of merge cells hardware core plate based on the PowerPC system as claimed in claim 2 is characterized in that: said some ethernet modules comprise first ethernet module and second Ethernet interface that is used for networking when being used for 1588 pairs.