CN201781417U - Cascaded high-voltage frequency converter PWM wave generation control system - Google Patents
Cascaded high-voltage frequency converter PWM wave generation control system Download PDFInfo
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- CN201781417U CN201781417U CN2010205000842U CN201020500084U CN201781417U CN 201781417 U CN201781417 U CN 201781417U CN 2010205000842 U CN2010205000842 U CN 2010205000842U CN 201020500084 U CN201020500084 U CN 201020500084U CN 201781417 U CN201781417 U CN 201781417U
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- power cell
- pwm
- duty ratio
- programmable gate
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Abstract
The utility model discloses a cascaded high-voltage frequency converter PWM wave generation control system, which comprises a duty ratio computing unit and three PWM wave generation units. The three PWM wave generation units respectively corresponding to three phases have the same internal circuit logic structure; the duty ratio computing unit is used for computing duty ratios of power units of the three phases and transmitting data and commands to the three PWM wave generation units; the three PWM wave generation units transmit PWM wave to the respectively controlled power units by the aid of optical fibers; and the power units transmit state information back to the PWM wave generation units. After adopting the PWM wave generation control system, a high-voltage frequency converter omits complicated duty ratio receiving, decoding and PWM waveform generation process as the power units directly receive PWM waveforms, simplifies design and control of the power units, and simultaneously realizes real-time transmission of PWM waveforms and real-time control of the power units.
Description
Technical field
The utility model relates to a kind of PWM ripple generation control system, relates in particular to a kind of cascaded high-voltage frequency converter PWM ripple generation control system, belongs to the power electronic equipment technical field.
Background technology
At present, power cell plural serial stage type high voltage converter is low owing to having the single electrode voltage grade, realizes easily and, power factor (PF) advantages of higher little to electric network pollution, becomes the high-pressure frequency-conversion technology that is most widely used.The mode of power cell plural serial stage that adopts plural serial stage type high voltage converter realizes high pressure output, and each power cell requires to send certain PWM voltage waveform according to control system, then each phase power cell output voltage output high voltage source that superposes.For reaching best superimposed voltage output waveform, each phase power cell generally adopts phase-shift PWM waveform generation technique, be that the PWM waveform with certain phase shift that single-phase each power cell receives makes its output voltage that certain phase shift also be arranged, and then be superimposed as the output of comparison perfect sine wave power supply.
The power cell control transmission system of existing high voltage converter adopts all-pass news control mode more, passes through two optical fiber interfaces between control unit and the power cell.Calculate the duty ratio of each power cell by the upper strata control system, be handed down to each power cell by serial communication mode then, after power cell receives duty ratio, produce the PWM waveform by comparing unit, and then the power controlling unit sends voltage waveform.The control command of each power cell and the passback of power cell state are also handled by communication modes.So existing high-pressure frequency-conversion power cell control all is made up of two parts: one, duty ratio computing unit and serial communication issue the unit, the general mode that adopts microprocessor MCU to add on-site programmable gate array FPGA, a slice MCU chip is responsible for duty ratio and is calculated, a slice fpga chip is responsible for issuing of serial communication data, this mode communication part needs to carry out communication with tens power cells at most, make that the design of FPGA is very complicated, control system need issue various control commands and duty ratio, for preventing that data from makeing mistakes, need also that data are encoded and verification to issuing.Two, the control section of lower floor's power cell; it need special communication receiving element to data receive, decoding and verification; also need to produce required PWM ripple after receiving data by PWM ripple generating unit; add the required protective circuit of power cell self, circuit etc. is uploaded in communication; make that the design of whole system is very complicated, reduced the reliability of system.In service simultaneously owing to adopt serial communication mode to transmit, making duty ratio issue needs the transmission time, can not carry out control corresponding immediately.
Therefore, design a kind of new cascaded high-voltage frequency converter PWM ripple generation control system, it is very necessary to solve above-mentioned series of technical.
The utility model content
The purpose of this utility model is to provide a kind of new cascaded high-voltage frequency converter PWM ripple generation control system, directly produce the required PWM ripple of each lower floor's power cell by native system, give lower floor's power cell by Optical Fiber Transmission, power cell only needs directly to receive the PWM waveform by optical fiber.
The purpose of this utility model is achieved by the following technical programs:
A kind of cascaded high-voltage frequency converter PWM ripple generation control system, comprise duty ratio computing unit 1 with three respectively with the three corresponding identical PWM ripple generation units 2 of internal circuit logical construction, duty ratio computing unit 1 calculates the duty ratio of each power cell of three-phase, with data and command transfer to three a PWM ripple generation unit 2, each power cell that three PWM ripple generation units 2 are transferred to the PWM ripple separately to be controlled by optical fiber, power cell returns state information to PWM ripple generation unit 2.
The purpose of this utility model can also further realize by following technical measures:
Aforementioned a kind of cascaded high-voltage frequency converter PWM ripple generation control system, wherein said duty ratio computing unit 1 is made up of a slice digital signal processor DSP, described PWM ripple generation unit 2 is made up of on-site programmable gate array FPGA, transmit control command by data wire between digital signal processor DSP and the on-site programmable gate array FPGA, and adopt 16 parallel-by-bit data wires to carry out transfer of data, digital signal processor DSP calculates the duty ratio of each power cell of three-phase, and be transferred to on-site programmable gate array FPGA by data/address bus, every on-site programmable gate array FPGA produces and its corresponding one PWM waveform of power cell mutually, between described on-site programmable gate array FPGA and corresponding each power cell mutually of this sheet by optical-fibre communications, one end of optical fiber is connected in the serial ports of on-site programmable gate array FPGA, the other end is connected in the optical fiber interface of each power cell, on-site programmable gate array FPGA is transferred to power cell with the PWM ripple, and power cell returns state and fault message to on-site programmable gate array FPGA.
Compared with prior art, the beneficial effects of the utility model are: after high voltage converter has adopted PWM ripple generation control system of the present utility model, power cell directly receives the PWM waveform, complicated duty ratio reception, decoding and PWM waveform generation process have been saved, make the design and the control of power cell become simpler, simultaneously, owing to realized the real-time Transmission of PWM waveform and the real-time control of power cell, also improved the real-time of whole high-pressure frequency-conversion system responses.
Description of drawings
Fig. 1 is a system construction drawing of the present utility model.
Fig. 2 is the utility model electrical schematic diagram.
Embodiment
The utility model is described in further detail below in conjunction with the drawings and specific embodiments.
Native system directly produces the required PWM ripple of each lower floor's power cell, gives lower floor's power cell by Optical Fiber Transmission, and power cell only needs directly to receive the PWM waveform by optical fiber, has realized the summary responses and the control of power cell PWM ripple.As shown in Figure 1, the utility model comprise duty ratio computing unit 1 with three respectively with the three corresponding identical PWM ripple generation units 2 of internal circuit logical construction, duty ratio computing unit 1 calculates the duty ratio of each power cell of three-phase, with data and command transfer to three a PWM ripple generation unit 2, each power cell that three PWM ripple generation units 2 are transferred to the PWM ripple separately to be controlled by optical fiber, power cell returns state information to PWM ripple generation unit 2.Concrete, as shown in Figure 2, the duty ratio computing unit is made up of a slice digital signal processor DSP, described PWM ripple generation unit is made up of three on-site programmable gate array FPGAs, three on-site programmable gate array FPGA difference corresponding A, B, the C three-phase, transmit control command by data wire between digital signal processor DSP and the on-site programmable gate array FPGA, and adopt 16 parallel-by-bit data wires to carry out transfer of data, digital signal processor DSP calculates the duty ratio of each power cell of three-phase, and being transferred to on-site programmable gate array FPGA by data/address bus, every on-site programmable gate array FPGA produces and its corresponding certain PWM waveform of power cell mutually.Its process is: according to the PS-SVPWM algorithm DSP calculate each mutually each each brachium pontis of power cell dutyfactor value and write the address of the RAM appointment of FPGA by data wire; The dutyfactor value of specified power unit is removed to read in the control command that FPGA sends according to DSP according to a preconcerted arrangement address from RAM, itself and inner triangular carrier element count value is compared, thereby produce the PWM trigger impulse.Three fpga chips produce the multi-channel PWM waveform of three-phase converter module respectively, and in the present embodiment, every fpga chip produces 16 road PWM waveforms of 8 power cells of a phase.Simultaneously, because noticing the electric power system three-phase electricity is the sinusoidal waveform of 120 ° of the mutual deviations of fully symmetry, behind the PWM waveform that produces a phase power cell, the waveform of all the other two-phases only need stagger in proper order 120 ° and get final product, that is to say when only needing the duty ratio computing unit to calculate the duty ratio result of calculation of A, B, C three-phase is staggered 120 °, after being handed down to the PWM wave generating unit, the PWM waveform generation process of its three-phase is duplicate.Between on-site programmable gate array FPGA and corresponding each power cell mutually of this sheet by optical-fibre communications, one end of optical fiber is connected in the serial ports of on-site programmable gate array FPGA, the other end is connected in the optical fiber interface of each power cell, on-site programmable gate array FPGA is transferred to power cell with the PWM ripple, and power cell returns state and fault message to on-site programmable gate array FPGA.At PWM waveform duration of work, waveform is the pulse signal that a series of high-low levels are formed, maximum pulse is a carrier cycle, for reaching the requirement of power cell State Control, will be obviously in the design with the distinguishing long-time low level signal of pwm signal (greater than two carrier cycle time widths) and for a long time high level signal (greater than two carrier cycle time widths) as control signal, every road waveform has three kinds of states: grow tall, long low and PWM ripple, when the two-way waveform of delivering to each power cell left and right sides bridge all is the PWM ripple, power cell normally moves, power unit by-pass when the two-way waveform all grows tall, when the two-way waveform is all grown power cell standby when low, other situation power cell is considered as the Optical Fiber Transmission fault, thus, native system has been realized the control to power cell.The feedback procedure of power cell state information is: power cell adds condition code with oneself state and forms status signal, send to FPGA by common serial communication mode by optical fiber, only need to adopt lower-cost 8-bit microcontroller and simple programming just can realize in the power cell.Status signal is made up of data characteristics sign indicating number and data content, is latched into respectively in the corresponding data buffer register.DSP reads fault word and status word by data wire from latch, according to status signal frequency converter is made the pwm signal adjustment.
Based on above characteristics, native system has adopted the design of DSP+3 sheet FPGA, and DSP calculates the duty ratio of each power cell of three-phase as the core of duty ratio computing unit by it, and is transferred to FPGA by data/address bus.3 FPGA are as the core of PWM ripple generation unit, every FPGA produces the PWM waveform of a phase power cell, because three-phase waveform generation principle is just the same, make that the circuit design and the programming of three fpga chips are just the same, simplified the particularly complexity of the hardware and software design of FPGA of system design greatly.Adopt 16 parallel-by-bit data wires to carry out transfer of data between DSP and the FPGA, make the transmission time of duty ratio ignore substantially, and FPGA directly is transferred to power cell after producing the PWM waveform, reduce the data serial communication and issued the required time, realized the instantaneous transmission of power cell PWM waveform, instant control.After native system adopts above-mentioned design, make that PWM waveform generation process is simple, the each several part task is clear and definite, adopts the project organization of DSP+3 sheet FPGA, because circuit and the program of FPGA are identical, has simplified the circuit design and the programming of system greatly.After high voltage converter has adopted this power cell control system, power cell directly receives the PWM waveform, complicated duty ratio reception, decoding and PWM waveform generation process have been saved, make the design and the control of power cell become simpler, simultaneously, owing to realized the real-time Transmission of PWM waveform and the real-time control of power cell, also improved the real-time of whole high-pressure frequency-conversion system responses.
Present embodiment is the mode that 8 power cells of corresponding every phase are connected, and needs to change power power cell progression according to the equipment application scenario in design.Hardware only need increase or reduce output port number when progression changes, and software only need be reset and need not redesign software the relevant variable of progression.
In addition to the implementation, the utility model can also have other execution modes, and all employings are equal to the technical scheme of replacement or equivalent transformation formation, all drop in the protection range of the utility model requirement.
Claims (2)
1. cascaded high-voltage frequency converter PWM ripple generation control system, it is characterized in that, comprise duty ratio computing unit (1) with three respectively with the three corresponding identical PWM ripple generation units (2) of internal circuit logical construction, duty ratio computing unit (1) calculates the duty ratio of each power cell of three-phase, with data and command transfer to three a PWM ripple generation unit (2), each power cell that three PWM ripple generation units (2) are transferred to the PWM ripple separately to be controlled by optical fiber, power cell returns state information to PWM ripple generation unit (2).
2. a kind of cascaded high-voltage frequency converter PWM ripple generation control system as claimed in claim 1, it is characterized in that, described duty ratio computing unit (1) is made up of a slice digital signal processor DSP, described PWM ripple generation unit (2) is made up of on-site programmable gate array FPGA, transmit control command by data wire between digital signal processor DSP and the on-site programmable gate array FPGA, and adopt 16 parallel-by-bit data wires to carry out transfer of data, digital signal processor DSP calculates the duty ratio of each power cell of three-phase, and be transferred to on-site programmable gate array FPGA by data/address bus, every on-site programmable gate array FPGA produces and its corresponding one PWM waveform of power cell mutually, between described on-site programmable gate array FPGA and corresponding each power cell mutually of this sheet by optical-fibre communications, one end of optical fiber is connected in the serial ports of on-site programmable gate array FPGA, the other end is connected in the optical fiber interface of each power cell, on-site programmable gate array FPGA is transferred to power cell with the PWM ripple, and power cell returns state and fault message to on-site programmable gate array FPGA.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2010205000842U CN201781417U (en) | 2010-08-20 | 2010-08-20 | Cascaded high-voltage frequency converter PWM wave generation control system |
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| CN2010205000842U CN201781417U (en) | 2010-08-20 | 2010-08-20 | Cascaded high-voltage frequency converter PWM wave generation control system |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103202708A (en) * | 2012-01-13 | 2013-07-17 | 深圳市开立科技有限公司 | High-voltage transforming method and device for color diasonograph |
| CN103870421A (en) * | 2012-12-10 | 2014-06-18 | 上海工程技术大学 | FPGA (Field Programmable Gate Array) based serial interface and PWM (Pulse Width Modulation) combined application IP (Intellectual Property) core |
| CN110189510A (en) * | 2019-05-13 | 2019-08-30 | 厦门大学 | A kind of wireless control multichannel pwm signal generating system |
| CN110460380A (en) * | 2019-08-30 | 2019-11-15 | 上海电气富士电机电气技术有限公司 | A kind of high voltage transducer power unit optical fiber ring network communication system |
| CN110611530A (en) * | 2019-09-03 | 2019-12-24 | 珠海格力电器股份有限公司 | Optical fiber fault determination method and device and photovoltaic centrifuge equipment |
| WO2022056769A1 (en) * | 2020-09-17 | 2022-03-24 | 华为数字能源技术有限公司 | Power source system, data centre, and charging device |
| CN116827155A (en) * | 2023-06-28 | 2023-09-29 | 荣信汇科电气股份有限公司 | Control system of cascade multi-level converter and carrier synchronization method thereof |
-
2010
- 2010-08-20 CN CN2010205000842U patent/CN201781417U/en not_active Expired - Lifetime
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103202708A (en) * | 2012-01-13 | 2013-07-17 | 深圳市开立科技有限公司 | High-voltage transforming method and device for color diasonograph |
| CN103202708B (en) * | 2012-01-13 | 2015-02-11 | 深圳市开立科技有限公司 | High-voltage transforming method and device for color diasonograph |
| CN103870421A (en) * | 2012-12-10 | 2014-06-18 | 上海工程技术大学 | FPGA (Field Programmable Gate Array) based serial interface and PWM (Pulse Width Modulation) combined application IP (Intellectual Property) core |
| CN103870421B (en) * | 2012-12-10 | 2016-08-24 | 上海工程技术大学 | A kind of serial line interface based on FPGA and PWM combination application IP kernel device |
| CN110189510A (en) * | 2019-05-13 | 2019-08-30 | 厦门大学 | A kind of wireless control multichannel pwm signal generating system |
| CN110460380A (en) * | 2019-08-30 | 2019-11-15 | 上海电气富士电机电气技术有限公司 | A kind of high voltage transducer power unit optical fiber ring network communication system |
| CN110611530A (en) * | 2019-09-03 | 2019-12-24 | 珠海格力电器股份有限公司 | Optical fiber fault determination method and device and photovoltaic centrifuge equipment |
| WO2022056769A1 (en) * | 2020-09-17 | 2022-03-24 | 华为数字能源技术有限公司 | Power source system, data centre, and charging device |
| CN116827155A (en) * | 2023-06-28 | 2023-09-29 | 荣信汇科电气股份有限公司 | Control system of cascade multi-level converter and carrier synchronization method thereof |
| CN116827155B (en) * | 2023-06-28 | 2024-02-20 | 荣信汇科电气股份有限公司 | Control system of cascade multi-level converter and carrier synchronization method thereof |
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Legal Events
| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C56 | Change in the name or address of the patentee |
Owner name: CHINA ENERGY ENGINEERING GROUP ZHENJIANG EAST CHIN Free format text: FORMER NAME: ZHENJIANG EAST CHINA ELECTRIC POWER EQUIPMENT FACTORY Owner name: ZHENJIANG EAST CHINA ELECTRIC POWER EQUIPMENT FACT Free format text: FORMER NAME: CHINA ENERGY ENGINEERING GROUP ZHENJIANG EAST CHINA ELECTRIC POWER EQUIPMENT FACTORY |
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| CP01 | Change in the name or title of a patent holder |
Address after: Seven Austin 212017 Zhenjiang city of Jiangsu Province, Runzhou District Patentee after: ZHENJIANG EAST CHINA ELECTRIC POWER EQUIPMENT CO.,LTD. Address before: Seven Austin 212017 Zhenjiang city of Jiangsu Province, Runzhou District Patentee before: China Energy Engineering Group Zhenjiang East China Electric Power Equipment Factory Address after: Seven Austin 212017 Zhenjiang city of Jiangsu Province, Runzhou District Patentee after: China Energy Engineering Group Zhenjiang East China Electric Power Equipment Factory Address before: Seven Austin 212017 Zhenjiang city of Jiangsu Province, Runzhou District Patentee before: Zhenjiang East China Electric Power Equipment Factory |
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| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20110330 |