CN205647467U - Nanosecond level digit synchronization machine based on high -speed serial bus of FPGA - Google Patents
Nanosecond level digit synchronization machine based on high -speed serial bus of FPGA Download PDFInfo
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- CN205647467U CN205647467U CN201620453645.5U CN201620453645U CN205647467U CN 205647467 U CN205647467 U CN 205647467U CN 201620453645 U CN201620453645 U CN 201620453645U CN 205647467 U CN205647467 U CN 205647467U
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Abstract
The utility model discloses a nanosecond level digit synchronization machine based on high -speed serial bus of FPGA, electricity connection was in proper order drawn together to the digit synchronization press packed bale triggering signal module, signal isolation module, FPGA control timing module, signal conversion module and pulse signal output module, FPGA control timing module is connected with the host computer through 422 serial module, and this technical scheme has realized that multichannel time delay precision triggers and the pulsewidth modulation for 1ns's pulse synchronization, and small, the time delay scope is extended, and pulse width is adjustable, has satisfied many the different demands that large -scale physical unit triggered in step.
Description
Technical field
This utility model relates to digital control technology field, particularly to a kind of nanosecond digital synchronous machine based on FPGA high-speed serial bus.
Background technology
In large-scale high-energy physics scientific experiments, due to by installation site, running environment, etc. factor affected, and the transmission cable length of every road synchronous triggering signal is variant, cause every road to trigger signal and there is time delay, cannot synchronously arrive at, trigger for solving the high-precision synchronization of multiple stage physics facility or multiple passage, need to develop multi-path digital synchrodrive.
The delay synchronizer that presently, there are there is problems in that (1) is realized by the artificial transmission cable length regulating every road signal, and this method is comparatively laborious, and precision is the highest, and can not realize automatically controlling to adjust time delay；" for the research of high accuracy number synchrodrive of Ultra Short Laser Pulse Technology " of in December, (2) 2007, the mode using 8253 enumerators and analog interpolation delay technique realizes the high accuracy time delay that delay precision is 1ns, value≤500ps is rocked in output pulse, counter process is used to realize the delay precision of 1ns, its operating process too complex.
The delay precision of the utility model of CN 201893762.U is 1ns, but from the point of view of the technical scheme realized, the utility model of CN 201893762.U is that the method using the high-precision digital delay line of FPGA+ realizes, and the area of its device is relatively big, and reference time delay is narrow.
It is thus desirable to provide a kind of novel digital synchronous machine to avoid drawbacks described above.
Summary of the invention
For the deficiencies in the prior art, the purpose of this utility model is to provide a kind of nanosecond digital synchronous machine based on FPGA high-speed serial bus, realize the digital synchronous machine that light volume is little, precision height reference time delay is wide, meet time delay synchronization and pulsewidth modulation between multiple devices.
A kind of nanosecond digital synchronous machine based on FPGA high-speed serial bus, described digital synchronous machine includes that the starting signal module being sequentially connected electrically, signal isolation module, FPGA control tfi module, signal conversion module and output of pulse signal module, and described FPGA is controlled tfi module and is connected with host computer by 422 serial port module.
Preferably, described host computer arranges each passage by application software and produces time delay and the pulsewidth of triggering pulse.
Preferably, described digital synchronous machine output multi-channel ns level delay synchronization signal based on FPGA high-speed serial bus.
Preferably, the mode of operation of described digital synchronous machine based on FPGA high-speed serial bus includes that outer synchronization and motor synchronizing trigger two kinds.
When preferably pattern is outer synchronization triggering, on the basis of signal is triggered on outside input one tunnel, the pulse that exports of other all passages triggers at the rising edge inputting trigger signal pulse.
Preferably, when mode of operation is motor synchronizing triggering, the internal clocking of fpga chip produces and rise on the way along triggering multipath delay pulse.
After preferably the FPGA within digital synchronous machine receives serial ports parameter, issue delay time and the pulse width parameter controlling every road time delay output circuit.
Preferably, described FPGA controls tfi module and includes being sequentially connected electrically serial ports transceiver module, processing and control module, parallel serial conversion module and high speed serial differential output pin, and described processing and control module is also connected with triggering receiver module.
Preferably, described serial ports transceiver module receives the pulse delay parameter of Serial Port Transmission, pulse width parameter and triggering pattern, it is sent to described processing and control module, described processing and control module completes the setting to trigger module, and calculate according to the data parameters of every road pulse and described parallel serial conversion module parameter is set, control described parallel serial conversion module, export 4GHz high speed serial differential time delay synchronization pulse by FPGA specialty high speed serial differential output pin.
The technical solution of the utility model has the advantages that
This utility model provides a kind of nanosecond digital synchronous machine based on FPGA high-speed serial bus, has the advantage that
(1) volume of device is greatly reduced.Components and parts used by the circuit board that this method realizes are few, main devices is exactly fpga chip, peripheral circuit components and parts are few, the circuit board volume being achieved in that is the least, the especially realization to the synchrodrive of multichannel (multichannel) has the biggest advantage, and the equipment simultaneously required installing space is particularly suitable；
(2) reference time delay is the widest.Can be from 0 to a minute magnitude, and delay precision does not changes, and the technical specification reached is 1ns, and reference time delay is 0 minute magnitude, can arbitrarily arrange, and the time delay of setting can arrange delay parameter with upper computer software by the serial communication of digital synchronous machine.
(3) pulse width of every road output can change, and the excursion of pulsewidth is from 20ns ~ minute magnitude, and actual setting is out of question to dozens of minutes magnitude to pulsewidth.Go for, in the equipment that different pulse widths are required, carrying out pulsewidth debugging.Width parameter can be by arranging delay parameter with upper computer software by the serial communication of digital synchronous machine.
(4) digital synchronous machine of the present utility model has two kinds of working methods: motor synchronizing triggers and outer synchronization triggering mode.It is that the FPGA within digital synchronous machine produces reference trigger pulse that motor synchronizing triggers, and other pulses produce according to different time delays on the basis of this pulse；Outer synchronization triggering mode is that FPGA within digital synchronous machine receives outside triggering pulse as benchmark, then according to the time delay of setting triggers other pulses successively.
(5) under having intense radiation, strong electromagnetic interference environment, output channel can use all-fiber to transmit.
Accompanying drawing explanation
Below by drawings and Examples, the technical solution of the utility model is described in further detail.
Fig. 1 is the structured flowchart of this utility model nanosecond based on FPGA high-speed serial bus digital synchronous machine；
Fig. 2 is the FPGA internal structure block diagram of this utility model nanosecond based on FPGA high-speed serial bus digital synchronous machine.
Detailed description of the invention
In order to have a clear understanding of the technical solution of the utility model, its detailed structure be will be set forth in the description that follows.Obviously, the concrete also deficiency of implementing of this utility model embodiment is limited to specific details appreciated by those skilled in the art.Preferred embodiment of the present utility model is described in detail as follows, in addition to these embodiments described in detail, it is also possible to have other embodiments.
With embodiment, this utility model is described in further details below in conjunction with the accompanying drawings.
This utility model is for many table apparatus high-precise synchronization and pulsewidth modulation and a kind of based on FPGA high-speed serial bus nanosecond digital synchronous machine of providing in the widest reference time delay, in conjunction with Fig. 1, described digital synchronous machine includes the starting signal module being sequentially connected electrically, signal isolation module, FPGA controls tfi module, signal conversion module and output of pulse signal module, described FPGA is controlled tfi module and is connected with host computer by 422 serial port module, this digital synchronous machine is communicated with outer computer (host computer) by serial communication port RS422, outer computer arranges each passage by application software and produces time delay and the pulsewidth of triggering pulse.Ns high accuracy delay line based on FPGA high-speed serial bus can be with output multi-channel ns level delay synchronization signal.
Working method can use outer synchronization to trigger and motor synchronizing two kinds of mode of operations of triggering, and work asynchronously pattern outside, and outside input one tunnel is triggered signal and triggered at the rising edge inputting trigger signal pulse as benchmark, the output pulse of other all passages；And in internal trigger mode of operation, the internal clocking of fpga chip produce and rise on the way along triggering multipath delay pulse.
After FPGA within digital synchronous machine receives serial ports parameter, issue delay time and the pulse width parameter controlling every road time delay output circuit.Data parameters according to the pulse of every road calculates and arranges parallel serial conversion module parameter, controls parallel serial conversion module output 4G high speed serial differential time delay synchronization pulse, is then converted to single-ended signal, output multi-channel time delay lock-out pulse by signal conversion module.
Control inside tfi module at FPGA, in conjunction with Fig. 2, described FPGA controls serial ports transceiver module, processing and control module, parallel serial conversion module and the specialty high speed serial differential output pin that tfi module includes being sequentially connected electrically, and described processing and control module is also connected with triggering receiver module.Serial port module receives the pulse delay parameter of Serial Port Transmission, pulse width parameter and triggering pattern, it is sent to processing and control module, processing and control module completes the setting to trigger module, and calculate according to the data parameters of every road pulse and parallel serial conversion module parameter is set, control parallel serial conversion module, export 4GHz high speed serial differential time delay synchronization pulse by FPGA specialty high speed serial differential output pin.
Use technique scheme, greatly reduce the volume of device.Components and parts used by the circuit board that this method realizes are few, main devices is exactly fpga chip, peripheral circuit components and parts are few, the circuit board volume being achieved in that is the least, the especially realization to the synchrodrive of multichannel (multichannel) has the biggest advantage, and the equipment simultaneously required installing space is particularly suitable；Reference time delay is the widest: can be from 0 to infinity, and delay precision does not changes, the technical specification reached is 1ns, and reference time delay is 0 minute magnitude, can arbitrarily arrange, the time delay of setting can arrange delay parameter with upper computer software by the serial communication of digital synchronous machine；The pulse width of every road output can change, and the excursion of pulsewidth is from 20ns ~ minute magnitude, and actual setting is out of question to dozens of minutes magnitude to pulsewidth.Go for, in the equipment that different pulse widths are required, carrying out pulsewidth debugging.Width parameter can be by arranging delay parameter with upper computer software by the serial communication of digital synchronous machine；Digital synchronous machine of the present utility model has two kinds of working methods: motor synchronizing triggers and outer synchronization triggering mode.It is that the FPGA within digital synchronous machine produces reference trigger pulse that motor synchronizing triggers, and other pulses produce according to different time delays on the basis of this pulse；Outer synchronization triggering mode is that FPGA within digital synchronous machine receives outside triggering pulse as benchmark, then according to the time delay of setting triggers other pulses successively；Under having intense radiation, strong electromagnetic interference environment, output channel can use all-fiber to transmit.
Finally should be noted that: above example is only in order to illustrate that the technical solution of the utility model is not intended to limit; although this utility model being described in detail with reference to above-described embodiment; detailed description of the invention of the present utility model still can be modified or equivalent by those of ordinary skill in the field; these are without departing from any amendment of this utility model spirit and scope or equivalent, all within the claims that application is awaited the reply.
Claims (4)
1. a nanosecond digital synchronous machine based on FPGA high-speed serial bus, it is characterized in that, described digital synchronous machine includes that the triggering signaling module being sequentially connected electrically, signal isolation module, FPGA control tfi module, signal conversion module and output of pulse signal module, and described FPGA is controlled tfi module and is connected with host computer by 422 serial port module.
The nanosecond digital synchronous machine of FPGA high-speed serial bus the most according to claim 1, it is characterised in that described digital synchronous machine output multi-channel ns level delay synchronization signal based on FPGA high-speed serial bus.
The nanosecond digital synchronous machine of FPGA high-speed serial bus the most according to claim 1, it is characterised in that the mode of operation of described digital synchronous machine based on FPGA high-speed serial bus includes that outer synchronization and motor synchronizing trigger two kinds.
The nanosecond digital synchronous machine of FPGA high-speed serial bus the most according to claim 1, it is characterized in that, described FPGA controls serial ports transceiver module, processing and control module, parallel serial conversion module and the specialty high speed serial differential output pin that tfi module includes being sequentially connected electrically, and described processing and control module is also connected with triggering receiver module.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105827222A (en) * | 2016-05-18 | 2016-08-03 | 中国工程物理研究院应用电子学研究所 | Nanosecond grade digital synchronizer based on FPGA high-speed serial bus |
| CN109144934A (en) * | 2018-08-17 | 2019-01-04 | 长光卫星技术有限公司 | A kind of controllable RS-422 serial port communication method of delay time |
-
2016
- 2016-05-18 CN CN201620453645.5U patent/CN205647467U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105827222A (en) * | 2016-05-18 | 2016-08-03 | 中国工程物理研究院应用电子学研究所 | Nanosecond grade digital synchronizer based on FPGA high-speed serial bus |
| CN109144934A (en) * | 2018-08-17 | 2019-01-04 | 长光卫星技术有限公司 | A kind of controllable RS-422 serial port communication method of delay time |
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