CN104866008B - A kind of clock system - Google Patents
A kind of clock system Download PDFInfo
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- CN104866008B CN104866008B CN201510243923.4A CN201510243923A CN104866008B CN 104866008 B CN104866008 B CN 104866008B CN 201510243923 A CN201510243923 A CN 201510243923A CN 104866008 B CN104866008 B CN 104866008B
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Abstract
The present invention relates to electronic technology field, and in particular to a kind of clock system for electronic system, including：Host computer, is connected with pci bus, for setting the frequency for the clock for needing to export, and selects corresponding passage；Upper-layer software module is provided with the host computer, is connected with pci bus, the frequency for the clock that the needs for being set according to host computer are exported calculates the value of the control register of special clock chip；CPLD, is connected with pci bus, for obtaining the value of the control register, and sends it to the special clock chip；The special clock chip, for generating corresponding clock signal according to the value of the control register and exporting；By above-mentioned technical proposal, the present invention can set output clock frequency, clock output area ultra-wide, with high-resolution by host computer.The present invention can also control to export the dutycycle of clock, meet the system requirements required to dutycycle.
Description
Technical field
The present invention relates to electronic technology field, and in particular to a kind of clock system for electronic system.
Background technology
With the development of modern communication technology, clock type and frequency needed for communication system also become more and more various
Change.Clock is as the heart of all electronic systems, and its performance and stability directly decide the performance of whole system.Traditional is
System clock is made up of a quartz crystal and amplifier.In order to allow oscillator operation, crystal must be in a band gain amplifier
Loop in, to compensate loss measurement and matching impedance.Level conversion must also be standard logic electricity by this gain amplifier
It is flat, then the system clock distributed by system clock needed for network is produced.
With the continuous improvement of system complexity, required clock species is more and more, to the performance and stability of clock
It is required that also more and more higher, with traditional design method be difficult to the deflection to clock system, shake, I/O standards, rise and under
The index requirement such as drop time.Simultaneously as using numerous discrete components, one is also result in PCB design and wiring
Fixed difficulty, and electromagnetic interference and crosstalk are larger, make the reliability decrease of whole system.
The clock circuit being made up of FPGA can produce multichannel, the clock signal of multi-frequency, can meet certain design requirement,
But it is not special clock chip after all, its logic level for exporting clock is restricted, and some performance indications are also below special
Use clock chip.
The content of the invention
The defect existed for prior art, it is an object of the invention to a kind of clock system for electronic system, leads to
Cross host computer and output clock frequency, clock output area ultra-wide, with high-resolution are set；The dutycycle of control output clock,
Meet the system requirements required to dutycycle.
For up to above-mentioned purpose, the invention provides a kind of clock system, including：
Host computer, is connected with pci bus, for setting the frequency for the clock for needing to export, and selects corresponding passage；Should
Upper-layer software module is provided with host computer, is connected with the pci bus, what the needs for being set according to host computer were exported
The frequency of clock, calculates the value of the control register of special clock chip；
CPLD, is connected with pci bus, during for obtaining the value of the control register, and send it to described special
Clock chip；
The special clock chip, for generating corresponding clock signal according to the value of the control register and exporting；
Dutyfactor adjustment circuit, is connected with the output end of the special clock chip, for adjusting the clock signal
Clock signal after dutycycle, and output adjustment.
Optionally,
The dutyfactor adjustment circuit includes the first chip, the second chip and door, when two chips connect same reference
Zhong Yuan, and the control end of two chips is connected with the CPLD, for adjusting dutycycle according to the control signal of the CPLD；
The same reference clock source is the clock signal that the special clock chip is exported；
It is described to be included according to the control signal of CPLD adjustment dutycycle：
Second chip carries out phase shift, the second clock signal and first after phase shift according to the control signal of the CPLD
First clock signal of chip output is exported through described with door.
Further, the dutyfactor adjustment circuit also includes OR gate and selection circuit；
The selection circuit is used for the instruction according to CPLD, controls second clock signal and the first chip after the phase shift
First clock signal of output is exported through described with door, or is exported through the OR gate.
The present invention can reach following beneficial effect：
By above-mentioned technical proposal, the present invention can set output clock frequency by host computer, and clock output area surpasses
Width, with high-resolution.The present invention can also control to export the dutycycle of clock, meet the system need required to dutycycle
Ask.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
There is the accompanying drawing used required in technology description to be briefly described, it should be apparent that, drawings in the following description are only this
Some embodiments of invention, for those of ordinary skill in the art, on the premise of not paying creative work, can be with
Other accompanying drawings are obtained according to these accompanying drawings.
Fig. 1 is the structured flowchart of clock system of the present invention；
Fig. 2 is duty ratio adjusting circuit theory diagram of the present invention；
Fig. 3 is the clock output logic chart of dutyfactor adjustment circuit of the present invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation is described, it is clear that described embodiment is only a part of embodiment of the invention, rather than whole embodiments.It is based on
Embodiment in the present invention, it is every other that those of ordinary skill in the art are obtained under the premise of creative work is not made
Embodiment, belongs to the scope of protection of the invention.
Require higher because clock species is more needed for Modern Communication System, and to clock jitter, it is traditional to be produced by crystal oscillator
The method of raw clock can not be met.High-speed wideband clock-signal generator is in fiber optic communication, integrated circuit automatic testing, thunder
There is important application value up to the field such as test and wideband digital oscillograph calibration.At home, because high-end clock signal is sent out
Raw device market is monopolized by a small number of offshore companies substantially, therefore a kind of high-speed wideband clock letter with low cost, simple and reliable of exploitation
Number generator has realistic meaning very much.The present invention can produce the clock that bandwidth ultra-wide is dithered as subpicosecond level, reduce traditional design side
The cost of method, improves design efficiency.
Fig. 1 is the structured flowchart of the clock system of the present invention, as described in Figure, including：
Host computer, is connected with pci bus, for setting the frequency for the clock for needing to export, and selects corresponding passage；
Upper-layer software module is provided with the host computer, the upper-layer software module is connected with pci bus, for according to host computer
The frequency of the clock of the needs output of setting, calculates the value of the control register of special clock chip；
CPLD, is connected with pci bus, during for obtaining the value of the control register, and send it to described special
Clock chip；
The special clock chip, for generating corresponding clock signal according to the value of the control register and exporting；
Dutyfactor adjustment circuit, is connected with the output end of the special clock chip, for adjusting the clock signal
Clock signal after dutycycle, and output adjustment.
Fig. 2 is the theory diagram of dutyfactor adjustment circuit, as illustrated,
The dutyfactor adjustment circuit includes the first chip, the second chip and door, when two chips connect same reference
Zhong Yuan, and the control end of two chips is connected with the CPLD, for adjusting dutycycle according to the control signal of the CPLD；
The same reference clock source is the clock signal that the special clock chip is exported
It is described to be included according to the control signal of CPLD adjustment dutycycle：
Second chip carries out phase shift, the second clock signal and first after phase shift according to the control signal of the CPLD
First clock signal of chip output is exported through described with door.
Fig. 3 is the clock output logic chart of the dutyfactor adjustment circuit, as illustrated, CLK_A and CLK_B correspond to the respectively
One clock signal and second clock signal, CLK_out represent that first clock signal and second clock signal pass through what is exported with door
Clock signal.
Further, the dutyfactor adjustment circuit also includes OR gate and selection circuit；
The selection circuit is used for the instruction according to CPLD, controls second clock signal and the first chip after the phase shift
First clock signal of output is exported through described with door, or is exported through the OR gate.
The design output clock is ultra wide band clock, and clock output area is 33Hz~4.1GHz, and resolution ratio is 1Hz, is trembled
Move as subpicosecond level.
The present invention can reach following beneficial effect：
By above-mentioned technical proposal, the present invention can set output clock frequency by host computer, and clock output area surpasses
Width, with high-resolution.The present invention can control to export the dutycycle of clock, meet the system requirements required to dutycycle.
Those skilled in the art will also be appreciated that the various illustrative components, blocks that the embodiment of the present invention is listed
(illustrative logical block), unit, and step can be by the knots of electronic hardware, computer software, or both
Conjunction is realized.To clearly show that the replaceability (interchangeability) of hardware and software, above-mentioned various explanations
Property part (illustrative components), unit and step universally describe their function.Such work(
Can be that the design requirement depending on specific application and whole system is realized by hardware or software.Those skilled in the art
For every kind of specific application various methods can be used to realize described function, but this realization is understood not to
The scope protected beyond the embodiment of the present invention.
Above-described embodiment, has been carried out further to the purpose of the present invention, technical scheme and beneficial effect
Describe in detail, should be understood that the embodiment that the foregoing is only the present invention, be not intended to limit the present invention
Protection domain, within the spirit and principles of the invention, any modification, equivalent substitution and improvements done etc. all should be included
Within protection scope of the present invention.
Claims (2)
1. a kind of clock system, it is characterised in that including：
Host computer, is connected with pci bus, for setting the frequency for the clock for needing to export, and selects corresponding passage；This is upper
Upper-layer software module is provided with machine, is connected with the pci bus, the clock that the needs for being set according to host computer are exported
Frequency, calculate special clock chip control register value；
Complex programmable logic device (CPLD), is connected with pci bus, for obtaining the value of the control register, and is sent out
Give the special clock chip；
The special clock chip, for generating corresponding clock signal according to the value of the control register and exporting；
Dutyfactor adjustment circuit, is connected with the output end of the special clock chip, the duty for adjusting the clock signal
Than, and the clock signal after output adjustment；
The dutyfactor adjustment circuit includes the first chip, the second chip and door, and two chips connect same reference clock
Source, and the control end of two chips is connected with the CPLD, for adjusting dutycycle according to the control signal of the CPLD；
The same reference clock source is the clock signal that the special clock chip is exported；
It is described to be included according to the control signal of CPLD adjustment dutycycle：
Second chip carries out phase shift, second clock signal and the first chip after phase shift according to the control signal of the CPLD
First clock signal of output is exported through described with door.
2. clock system according to claim 1, it is characterised in that the special clock chip unit also includes OR gate and choosing
Select circuit；
The selection circuit is used for the instruction according to CPLD, controls second clock signal and the first chip after the phase shift to export
The first clock signal exported through described with door, or exported through the OR gate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510243923.4A CN104866008B (en) | 2015-05-13 | 2015-05-13 | A kind of clock system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510243923.4A CN104866008B (en) | 2015-05-13 | 2015-05-13 | A kind of clock system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104866008A CN104866008A (en) | 2015-08-26 |
| CN104866008B true CN104866008B (en) | 2017-10-03 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510243923.4A Expired - Fee Related CN104866008B (en) | 2015-05-13 | 2015-05-13 | A kind of clock system |
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Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106527577B (en) * | 2015-09-09 | 2020-10-23 | 华为技术有限公司 | Method and apparatus for adjusting clock signal |
| CN106961261A (en) * | 2017-03-30 | 2017-07-18 | 中国电子科技集团公司第二十四研究所 | A kind of Low phase noise adjustable duty cycle signal source of clock |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1321003A (en) * | 2000-04-24 | 2001-11-07 | 华为技术有限公司 | Short-delay MF or HF clock pulse width regulating circuit |
| CN101013335A (en) * | 2007-02-15 | 2007-08-08 | 杭州华为三康技术有限公司 | Method and apparatus for synchronizing clock of distributed processing system |
| CN101110590A (en) * | 2007-08-21 | 2008-01-23 | 中兴通讯股份有限公司 | Method and device for phase adjustment in the course of detecting time sequence allowance |
| CN204086415U (en) * | 2014-07-15 | 2015-01-07 | 航天科工深圳（集团）有限公司 | Fault wave recording device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI369604B (en) * | 2008-09-24 | 2012-08-01 | Asmedia Technology Inc | Clock generating device and method thereof and computer system using the same |
-
2015
- 2015-05-13 CN CN201510243923.4A patent/CN104866008B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1321003A (en) * | 2000-04-24 | 2001-11-07 | 华为技术有限公司 | Short-delay MF or HF clock pulse width regulating circuit |
| CN101013335A (en) * | 2007-02-15 | 2007-08-08 | 杭州华为三康技术有限公司 | Method and apparatus for synchronizing clock of distributed processing system |
| CN101110590A (en) * | 2007-08-21 | 2008-01-23 | 中兴通讯股份有限公司 | Method and device for phase adjustment in the course of detecting time sequence allowance |
| CN204086415U (en) * | 2014-07-15 | 2015-01-07 | 航天科工深圳（集团）有限公司 | Fault wave recording device |
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| Publication number | Publication date |
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| CN104866008A (en) | 2015-08-26 |
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