CN1321003A - Short-delay MF or HF clock pulse width regulating circuit - Google Patents
Short-delay MF or HF clock pulse width regulating circuit Download PDFInfo
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Abstract
A short-delay MF or HF clock pulse width regulator suitable for the clock signal under 400 MH2 is composed of a lag comparator for comparing a sine signal with a threshold voltage to output a clock signal, a detector for detecting the ripple signals in clock signal, and a corrector for correcting the threshold voltage of the comparator according the detected ripple signal. Its advantages are no sudden change of duty ratio, and high adaptive power.
Description
The present invention relates to a kind of delayed clock pulse width regulating circuit, particularly, relate to the short delayed clock pulse width regulating circuit of medium-high frequency that constitutes to the DC level transducer by hysteresis comparator and clock signal duty cycle.
In the modern signal processing system, clock signal is indispensable, because the development that technical fields such as communication are advanced by leaps and bounds, requirement to clock signal is also more and more higher, be mainly reflected in the following aspects: the frequency accuracy of (1) clock signal, this aspect mainly solves by crystal oscillator and atomic clock; (2) the long-time stability of clock signal, in 1 year or longer time, the error of clock signal is in one second or littler scope, and this respect is determined by the stability in clock source; (3) the duty ratio stability of clock signal, owing to external reasons such as unexpected variation, bigger skew takes place in the duty ratio of clock, can cause producing in the communication system the bigger error rate.In analog to digital converter, because the switching rate (SAMPLE RATE) in the sample/hold circuit is the value of determining in the design, change in duty cycle causes can not reaching the charging interval shortening of electric capacity the conversion precision of regulation.
Fig. 1 is the simple principle figure of existing high precision clock generator.In Fig. 1, the variation of clock duty cycle is mainly from systematic error and random error two parts.Systematic error comprises: the variation of crystal oscillator amplitude output signal, and owing to the harmonic wave that the influence of load etc. produces, the variation of direct current triggering level and temperature drift etc.Random error is mainly from the deviation of flip-flop in the sinusoidal output of: crystal oscillator, the deviation of the random deviation of comparator input stage and direct current triggering level etc.
Process for simplifying the analysis, with the sinusoidal signal output stage of all error transforms to crystal oscillator, and the deviation of putative signal is less, that is, in analytical error during to the influencing of duty ratio, according to sinusoidal wave equation, trigger along the time of taking place and be:
ΔV=Vsin(2πf
*Δt) (1)
Wherein, V represents sinusoidal wave amplitude, and f represents frequency, and Δ V represents the variation of flip-flop in the sine wave.Suppose: V〉Δ V, according to the approximate equation of SIN function, by above-mentioned formula (1), the time variation approximate expression that can obtain to trigger along taking place is:
Δt=ΔV/V
*2πf (2)
Trigger along identical time variation all takes place with descending owing to trigger the edge in rising, according to formula (2), the variation of duty ratio can be expressed as:
ΔD=ΔV/πV (3)
By above-mentioned formula (3), can obtain signal as shown in Figure 2.
In Fig. 2, desirable clock signal, if duty=t2/ (t1+t2), its DC level overlaps with the sine DC composition.Actual clock signal, then the direct current triggering level does not overlap with the sine DC composition, shown in dotted line among this Fig. 2.At this moment, the variation of the flip-flop in the sine of crystal oscillator output is negative polarity, that is to say, the polarity that changes composition is uncertain.
The object of the present invention is to provide a kind of clock signal that can handle below the assigned frequency; the short delayed clock pulse width regulating circuit of medium-high frequency with adaptive ability; make the duty ratio of clock signal not have macromutation; reduce pressure to Digital Signal Processing; even clock signal duty cycle is during with respect to set point change; also can in 1 to 2 clock, obtain proofreading and correct; and make the adjustment circuit be suitable for the submicron integrated circuit manufacturing process; to reduce the influence of the random error in the chip manufacturing proces; thereby can satisfy the high information quantity that the hybrid digital-analog integrated circuit chip is used in Modern Communication System; low error rate, and to the stable higher requirement of the duty ratio of clock signal.
In order to achieve the above object, according to the short delayed clock pulse width regulating circuit of medium-high frequency of the present invention, have hysteresis comparator and a plurality of power supply, also comprise: a hysteresis comparator, be used for the sine wave signal of an input input and the threshold voltage of another input input are compared, and output has the clock signal of regulation duty ratio; A circuit for detecting, whether the described clock signal that is used for detecting the described hysteresis comparator output of input fluctuation signal occurs; And a correcting circuit, be used for according to the detected fluctuation signal of described circuit for detecting, proofread and correct the described threshold voltage that described clock signal converts described hysteresis comparator input to.
According to the short delayed clock pulse width regulating circuit of medium-high frequency of the present invention, the duty ratio of clock signal can be set at a definite numerical value, any variation that deviates from this set point, comprise and changing slowly and violent sudden change, can be detected and obtain immediately to proofread and correct, the cycle of correction be 1 to 2 clock signal period.
Duty ratio circuit for detecting of the present invention has adopted two kinds of structures, at the fast reaction passage bottleneck problem in the integrated circuit, to one of them embodiment, adopts the way of reciprocity constant-current source to proofread and correct.
In circuit of the present invention, the output of clock signal directly is used in the duty ratio circuit for detecting, eliminated since the imbalance that causes because of the coupling of device etc. in the integrated circuit manufacturing to the shadow of clock signal duty cycle to.
Rapid-action sudden change amount carries out though the adjustment circuit of clock signal duty cycle of the present invention is aimed at, and for the change that is departed from the clock signal duty cycle that causes by low speed, this circuit also can be adjusted and be compensated equally.
The short delayed clock pulse width regulating circuit of medium-high frequency of the present invention in a word can be handled the following frequently clock signal of 400MHz; duty ratio with clock signal does not have macromutation; adaptive ability is strong; and be suitable for the advantage of submicron integrated circuit manufacturing process; thereby adapt to modern communications to high information quantity, low error rate and in the digital-to-analogue hybrid system, to the high requirement of the duty ratio stability of clock signal.
Below, with reference to the accompanying drawings, describe embodiments of the invention in detail, wherein:
Fig. 1 represents the clock-signal generator schematic diagram;
Fig. 2 represents that the output signal of desirable clock-signal generator and actual clock-signal generator relatively schemes;
Fig. 3 represents the block diagram of clock signal duty cycle adjustment circuit;
Fig. 4 represents that the embodiments of the invention circuit departs from immune schematic diagram to level;
Fig. 5 represents clock signal duty cycle detecting and the correcting circuit schematic diagram (MOS) of embodiment 1;
Fig. 6 represents clock signal duty cycle detecting and the correcting circuit schematic diagram (bipolar) of embodiment 2;
Fig. 7 represents the clock signal duty cycle detecting of the embodiment of the invention 1 and the concrete structure figure of correcting circuit;
Fig. 8 has eliminated the clock signal duty cycle detecting and the correcting circuit schematic diagram of effect of parasitic capacitance;
Fig. 9 represents the clock signal duty cycle detecting of the embodiment of the invention 2 and the concrete structure figure of correcting circuit;
Figure 10 represents clock signal duty cycle rapid adjustment process schematic diagram.
At first, with reference to Fig. 3, the basic structure block diagram of clock signal duty cycle adjustment circuit of the present invention is described.This adjustment circuit is detected by hysteresis comparator module and clock signal duty cycle and the correcting circuit module is formed.VCC and gnd are respectively power supply and ground, and VinP is that sine wave input, the Vout of oscillator is that clock signal output, Vref are that reference level input, Vbias1, Vbias2 and Vbias3 are 3 bias voltage inputs.Power supply VCC and ground gnd are connected with earth terminal with the power end of detecting and correcting circuit with hysteresis comparator respectively.Bias voltage Vbias1 is connected with the reference level input Vref of hysteresis comparator.Reference voltage Vref, bias voltage Vbias2 and Vbias3 are connected with the respective end of detecting and correcting circuit respectively.Sinusoidal wave output is connected to the P end of hysteresis comparator, and the output of detecting and correcting circuit is connected to the N end of hysteresis comparator, and the output of hysteresis comparator is connected to the input of detecting and correcting circuit.
Sinusoidal wave output is connected to the input P of hysteresis comparator, and when the input voltage of this input P during greater than the input voltage of its input N, this hysteresis comparator is output as 1; Otherwise this hysteresis comparator is output as 0.Simultaneously, because the output of clock signal is connected to the input of detecting and correcting circuit, the output of detecting and correcting circuit is connected to the input N of hysteresis comparator, so circuit has adaptation function.
When stable output, detecting and correcting circuit are output as set point, and the duty ratio of clock signal is in prescribed limit.When for a certain reason, when the duty ratio of hysteresis comparator output signal increases, the output of circuit for detecting also will raise, thereby change the threshold voltage of hysteresis comparator, and at the hysteresis comparator output, the duty ratio of clock signal changes thereupon.With the clock signal duty cycle increase is example, and at this moment, the output of circuit for detecting will raise (referring to following shown in Figure 10), and the duty ratio of clock signal will fall after rise.
In addition, the clock signal duty cycle of the invention described above embodiment is adjusted circuit, can be applied in the digital CMOS process, solves the requirement of in the digital-to-analogue hybrid system clock signal duty cycle being adjusted preferably.
Below, the present embodiment will be described, the DC offset voltage that causes for reasons such as device mismatch has immunologic function.For this reason, will adjust circuit and further be reduced to schematic diagram 4.
Shown in Fig. 4 in, all circuit are thought what no-voltage departed from, with might produce offset voltage factor represent with Vos, Vsin is the sine wave input that comprises DC component, Vth is the threshold voltage of hysteresis comparator, the output of pulse duty factor detecting just and correcting circuit, it is input as the clock signal after the shaping.
When Vos is timing, at the signal input port of hysteresis comparator, signal will on move, cause the duty ratio of the clock signal exported to increase; After increasing the clock signal input detecting and correcting circuit of duty ratio, make Vth raise.At the circuit steady-working state, value that Vth raises and Vos payment, so system has the function that self adaptation is eliminated to the random error by introducing in the manufacture process that exists in the circuit, reach to departing from of level be immune.
The transfer function of setting duty ratio detecting and correcting circuit is:
H(D)=Vdc+K
*ΔV
In the following formula, Vdc is a DC component, and K is the gain of correcting circuit.
The duty cycle transmissions function of setting hysteresis comparator is:
Δduty=F(V)
*ΔV
In following formula, suppose that hysteresis comparator is linear to the response of duty ratio, the duty ratio coefficient when F (V) is level constant.
The change in duty cycle that causes because of the introducing of offset voltage is:
Δduty=F(V)
*Vos
The hysteresis comparator threshold voltage that offset voltage causes is changed to:
Vth=Vdc+K
*Δduty=Vdc+F(V)
*Vos (4)
From the influence that formula (4) is removed DC component, only consider the response of offset voltage, can obtain four kinds of situations, just:
1、K
*F(V)=1
The change in duty cycle that offset voltage causes can be eliminated fully;
2、K
*F(V)＜1
Offset voltage will cause the variation of clock signal duty cycle, but variation can reduce;
3、1＜K
*F(V)＜2
Offset voltage causes the variation of clock signal duty cycle, and variation reduces and is opposite polarity;
4、K
*F(V)＞2
Offset voltage causes the variation of clock signal duty cycle, variation be increase and be opposite polarity.
Hence one can see that, and except that above-mentioned (4) this situation, the present invention can eliminate the change in duty cycle that offset voltage causes fully by the adjustment circuit that detecting and correcting circuit constitute.
Fig. 5 represents being detected and the correcting circuit schematic diagram by the integrated clock signal duty cycle of MOS transistor of embodiment 1.In Fig. 5, Vin is the clock signal input, and Vout is the output of duty ratio detecting and correcting circuit, as the threshold voltage of hysteresis comparator.
Circuit for detecting comprises: current switch, the 1st biasing circuit, the 1st current mirroring circuit, the 2nd current mirroring circuit and the 3rd current mirroring circuit.The 1st biasing circuit M6 ＇ output offset electric current I 1.The 1st current mirroring circuit by M27 ＇ and M26 ＇ form, the 2nd current mirroring circuit is made up of M10 ＇ and M9 ＇ and the 3rd current mirroring circuit is made up of M28 ＇ and M29 ＇, output current is I2 and I7 respectively, I3 and I4, I5 and I6.The 1st current mirroring circuit of this circuit for detecting and the input termination power of the 2nd current mirroring circuit, its separately output join with an input of current switch respectively, another output of the 1st current mirroring circuit is received the grid of MOS transistor M30 ＇ and as an end of the capacitor C of current-to-voltage convertor, an input of another output termination the 3rd current mirroring circuit of the 2nd current mirroring circuit.Another input of the 3rd current mirroring circuit and an end of capacitor C join.And the input of the 1st biasing circuit and the public output of current switch join.The other end ground connection of the output of the output of the 3rd current mirroring circuit, the 1st biasing circuit and capacitor C.
Correcting circuit partly has change-over circuit and the comparison circuit of electric current to voltage, constitutes specifically to comprise: the 2nd biasing circuit M24 ＇, the 3rd biasing circuit M33 ＇, the 4th current mirroring circuit, MOS transistor M30 ＇ and resistance R 1, R2 and capacitor C.The 4th current mirroring circuit is made up of the gentle M32 ＇ of M31 ＇, output current is I8 and I9 respectively, its input termination power, the drain electrode of one output termination MOS transistor M30 ＇, and another output is received the input of the 2nd biasing circuit M33 ＇ and the node of the 3rd biasing circuit and resistance R 2, i.e. the Vout of PWM filter.The end of the source electrode connecting resistance R1 of MOS transistor M30 ＇, the other end ground connection of resistance R 1.Electric current has by MOS transistor M30 ＇ and capacitor C built-up circuit to the transducer of voltage, according to the height of the voltage level on the capacitor C, controls the grid of M30 ＇, determines the size of its conducting electric current.
Clock signal is from Vin input current switch, in order to the flow direction of the electric current I 1 of Control current switch.Work as Vin=1, I2=I1, I3=0; When Vin=0, I2=0, I3=I1.With x=y=1 is example, and the clock signal duty cycle of this moment is 50%.When because certain reason, the duty ratio of clock signal increases, then the I1 of the 1st biasing circuit insert time of the I2 of the 1st current mirroring circuit and I7 will be greater than I3 that inserts the 2nd current mirroring circuit and the time of I4, therefore, in each clock cycle, the I7 of the 1st current mirror injects the electric charge that the electric charge of capacitor C will discharge greater than I6; Because the injection of unnecessary net charge, the voltage on the capacitor C can raise gradually; The rising of voltage on the electric capacity causes the rising of transistor M30 ＇ grid voltage, and the carrying voltage of resistance R 1 increases, and makes that the channel current among the transistor M30 ＇ increases, and electric current I 8 increases; Because I8 and I9 are current mirror, the I9 electric current increases along with the increase of I8 electric current, and the carrying voltage of resistance R 2 raises, and Vout raises; Because Vout is the threshold voltage of hysteresis comparator, as shown in figure 10, the threshold voltage of rising can cause the falling of duty ratio; Through after the adjustment in several cycles, duty ratio is adjusted to the value of setting, and at this moment, adjustment process finishes.
The value of x, y among the setting of clock signal duty cycle and Figure 10 is relevant.Below analyze, provided the relation of clock signal duty cycle and x, y value, and the duty ratio of setting is only relevant with x, y.
Setting Vin and be time of 1 is t1, is that 0 time is t2, and then the cycle of signal is T=t1+t2.Being changed to of voltage on the electric capacity:
ΔV=(t1
*y-t2
*x)
*I1/C
Vout=(Ibias-I10)
*R2+R2
*ΔV/R1
ΔVout=R2
*ΔV/R1
D=t1/(t1+t2)
When steady operation, the PWM filter is output as direct current, and promptly variable quantity is 0, and then the duty ratio of clock signal is the function of x and y.
ΔVout=0←→t1
*y=t2
*x
D=t1/(t1+t2)=x/(x+y)
Can obtain from following formula, when x=y, the duty ratio of clock signal is 50%; When x=2y, the duty ratio of clock signal is 66.7% ...More than, calculating obtains under perfect condition, and for side circuit, because leakage current and transistor-matched influence, the result is slightly variant.
Fig. 6 is a kind of clock signal duty cycle detecting that is made of bipolar transistor and the schematic diagram of correcting circuit.More as can be seen, wherein replace MOS transistor 30 ＇ from Fig. 6 and above-mentioned Fig. 5 with bipolar transistor T1, but all the other elements also be by bipolar transistor constitute and its circuit connecting mode all identical, therefore no longer repeat specification.
Because bipolar transistor needs current drives, so its control precision error ratio MOS transistor is wanted greatly.
Below, provide a kind of according to circuit diagram shown in Figure 5, constitute the detecting of clock duty cycle and the concrete structure of correcting circuit by MOS transistor.
At first, the structure of circuit for detecting part is described, as shown in Figure 7, this circuit includes: inverter, a pair of current switch, the 1st, the 2nd and the 3rd current mirroring circuit and the 1st biasing circuit.This inverter is to be composed in series by PMOS transistor M14 and nmos pass transistor M13, that is, the source ground of transistor M13, its drain and gate is connected with the drain and gate of this M14 respectively, and the source electrode of transistor M14 meets power supply VCC and forms.This current switch is made up of pair of NMOS transistors M8, M136, the grid difference input clock signal Vin of its transistor M8 and M136 and the inversion clock signal of inverter output, the source electrode of this transistor M8, M136 is received the source electrode of nmos pass transistor M19 together, and its drain electrode is connected with the drain electrode of PMOS transistor M27, M10 respectively.The 1st current mirroring circuit is made up of transistor M27, PMOS transistor M26, the grid of grid, drain electrode and the M26 of this transistor M27 joins, its source electrode is all received power supply VCC, and the M26 drain electrode connects the drain electrode of the transistor M28 of the 3rd current mirroring circuit, in addition, the grid of transistor M28 is connected with the M29 grid, and its source electrode is ground connection gnd all.The 2nd current mirroring circuit is made up of transistor M10, PMOS transistor M9 and the 3rd current mirroring circuit is made up of nmos pass transistor M29 and M28, and its connected mode is identical with the 1st current mirroring circuit, and Vbias2 provides gate bias voltage to M20.Nmos pass transistor M19 and M6 constitute the 1st biasing circuit.
In addition, the drain electrode of above-mentioned transistor M8 is to the correcting circuit output current, and capacitor C 1 ground connection of passing through to arrive as electric current electric pressure converter.It is that 1 o'clock electric current carries out conversion in 1: 1 and to capacitor C 1 charging that current mirroring circuit is used for clock signal.The constant-current source that nmos pass transistor M34, M35 and M36, M37 constitute can be setovered to improve the response speed of system to current mirror.And PMOS transistor M25, nmos pass transistor M19, M37 are common the moon grid amplifications (CASCODE) levels altogether, provide biasing by Vbias to its grid.This grade circuit can reduce the channel length modulation effect effectively.
The structure of correcting circuit part below is described, this correcting circuit has transducer and the comparison circuit from the electric current to voltage.The 4th current mirroring circuit comprises transistor M32 and M31, and the grid of this transistor M32, the grid of M31 are connected with drain electrode, and its source electrode is all received power supply.Nmos pass transistor M30 connects resistance R 14, and the source electrode of nmos pass transistor M33 connects resistance R 15 and constitutes the 2nd biasing circuit.The drain electrode that PMOS transistor M32, M31 are received in this transistor M33, M30 drain electrode respectively, its grid is received the grid of PMOS transistor M25 and the drain electrode of M8 respectively, and the other end ground connection of this two resistance R 14, R15.This transistor M30, M33 carry out conversion and the comparison of voltage to electric current, and its spill current forms the threshold voltage of hysteresis comparator the duty ratio of clock signal is adjusted on resistance R 13.
PMOS transistor M11, M24 and M12 are the 3rd biasing circuit, it provides bias current, its source electrode meets power supply VCC jointly, and the drain electrode of its grid and M11 is connected with the drain electrode of nmos pass transistor M22 jointly, and the drain electrode of this M24 and M12 is connected with the source electrode of resistance R 13, PMOS transistor M25 respectively.Transistor M25 source electrode connects PMOS transistor M12 drain electrode, and its grid meets reference voltage Verf, and drain electrode connects the drain electrode of nmos pass transistor M23.The source ground of transistor M23, its grid is connected with the transistor M6 grid of circuit for detecting together with drain electrode.
And the electric current source generating circuit is made of operational amplifier, nmos pass transistor M22 and resistance R 12.The vinP end of this operational amplifier adds reference voltage Vref, and its output vout is connected with the M22 grid, and the vinN end is connected with the source electrode of M22 and an end of resistance R 12, and the other end ground connection gnd of resistance R 12.
And the tie point of the drain electrode of PMOS transistor M24 and M33 and resistance R 13 is as DC level output Vout node.
In above circuit, clock signal is imported from Vin, clock signal and inversion clock thereof, and respectively oxide-semiconductor control transistors M8, M136 current switch, transistor M26, M27 are that 1 o'clock electric current carries out conversion in 1: 1 and to capacitor C 1 charging with clock signal; Transistor M10, M9 and M28, M29 are that 0 o'clock electric current carries out conversion in 1: 1 and capacitor C 1 is discharged with clock signal.Transistor M30, M33 carry out conversion and the comparison of voltage to electric current, and its spill current forms the threshold voltage of hysteresis comparator the duty ratio of clock signal is adjusted on resistance R 13.
The electric current of setting among transistor M6, the M19 is I, and then clock signal is 1 o'clock, to being charged as of capacitor C 1:
Cl
*(dV/dt)=I
*Duty
When the clock signal is 0, be to capacitance discharges:
C1
*(dV/dt)=I
*(1-Duty)
In 1 clock signal period, be to the pure charge volume of electric capacity:
C1
*(dV/dt)=I
*(2
*Duty-1) (5)
When the clock signal dutyfactor greater than 50% the time, the voltage on the electric capacity is raising; When the clock signal dutyfactor less than 50% the time, the voltage on the electric capacity is descending.And from following formula (5) was analyzed, during stable state, DUTY=50%, the voltage on the electric capacity kept stable.
Minor variations has taken place in initialization system sinewave output when stable state, with the small-signal operation principle and the application of formula of derivation circuit.Near the minor variations that system takes place steady-working state causes the minor variations of voltage on the electric capacity to be:
C1
*(dVc/dt)=2
*I
*ΔDuty
The minor variations of voltage causes that the threshold voltage of hysteresis comparator is changed on the electric capacity:
ΔVcom=(ΔVc/R14)
*R13
The variation of setting clock signal duty cycle is caused that by the minor variations of sine wave by the analysis of front, the formula that can obtain causing clock signal duty cycle to change is:
Δduty=ΔV/π
*V
In the following formula, V is the amplitude of sine wave signal.
When system constituted a closed loop, the minor variations of the sine voltage of any polarity can cause the minor variations of an identical polar, appears at the input N of hysteresis comparator, and this minor variations voltage is:
ΔVcom=K
*ΔV
In following formula, the gain in initialization system loop is K, and then the computing formula of K is:
K={2
*I/(f
*C1
*R14
*π
*V)}
*R13
At the value of K, following 3 kinds of situations can be arranged.
1、K=1
In such cases, the minor variations of any duty ratio of clock signal all can be compensated completely in the next clock cycle, thereby make duty ratio return to set point;
2、K＜1
In such cases, be to carry out to the adjustment of clock signal duty cycle according to the ratio of geometric progression, be 90% as the precision of each adjustment, then through after two clock cycle, adjust precision and can reach 1%;
3、K＞1
In such cases, toning is appearred in the duty ratio of clock signal, duty ratio can not converge on set point.Increase as duty ratio, after then adjusting for the first time, duty ratio will be less than set point, again will be greater than set point after adjusting the second time.The rest may be inferred, and the duty ratio of clock signal will swing back and forth.
Embodiment 2
The inventor is at the bottleneck problem of parasitic capacitance to response speed, adjust in the circuit at the clock signal duty cycle of present embodiment 2, the employing measure, removed the influence of parasitic capacitance in the current conversion path, this circuit system response time further improved, so that can be applied in the clock circuit of 100MHz to 400MHz.
Below, with reference to Fig. 8, clock signal duty cycle detecting and the correcting circuit of having eliminated effect of parasitic capacitance are described.In Fig. 8, same with Fig. 5, Vin is the clock signal input, and Vout is the output of duty ratio detecting and correcting circuit, as the threshold voltage of hysteresis comparator.
Circuit for detecting comprises: inverter, the 1st current switch the 1, the 2nd current switch 2, as the M26 ＂ of the 1st current source circuit with as the 2nd current source circuit M6 ＂.The M26 ＂ input termination power VCC of the 1st current source circuit, output termination current switch 1.The M6 ＂ input termination switch 2 of the 2nd current source circuit, output head grounding GND.Current source circuit M26 ＂ provide electric current I 1=m*I, and current source circuit M6 ＂ provide bias current I2=n*I.One end ground connection GND of the 1st switch 1, the other end is connected with an end of the 2nd switch 2, another termination power VCC of switch 2, the inversion clock signal difference control switch 1 of clock signal input Vin and inverter output and the operating state of switch 2.In addition, the common node of switch 1 and switch 2 is received the capacitor C as current-to-voltage converting circuit.
Fully identical with Fig. 5 as for correcting circuit, therefore explanation is omitted.
When Vin was high level, this switch 1 was connected, charge to capacitor C with the output current I1 of current source circuit M26 ＂, otherwise, electric current I 1 is inserted ground; When Vin was low level, this switch 2 was connected, and made the speed discharge of capacitor C with the electric current I 2 of current source circuit M6 ＂, otherwise, electric current I 2 is inserted VCC.
Set m=n=1, promptly set duty ratio and be set at 50% and describe the work of foregoing circuit for example.
When because certain reason, when the duty ratio of clock signal increases, in each clock cycle, the electric charge that the electric charge that current source circuit M26 ＂ injects will discharge greater than current source circuit M6 ＂; Because the increase of unnecessary net charge, the voltage on the capacitor C can raise; The grid of the voltage access transistor M30 ＇ of capacitor C carrying causes transistorized bias voltage to raise, and the voltage of resistance R 1 carrying is raise; The rising of resistance R 1 carrying voltage causes the increase of channel current among the transistor M30 ＇ again, and the electric current I 2 that flows through current source circuit M6 ＇ increases; Because M32 ＇ and M31 ＇ constitute current mirror, so its electric current I 4 increases along with the increase of I3; The increase of electric current I 4 causes the carrying voltage of resistance R 2 ＇ to raise, and promptly exports Vout and raises; This output Vout is the threshold voltage of comparator, and according to Figure 10, the threshold voltage of rising causes the falling of clock signal duty cycle; Through after the adjustment of several clock cycle, the duty ratio of clock signal falls back to set point, and at this moment, adjustment process finishes.When the duty ratio of clock signal reduced, adjustment process was similar to the above, and just the variation of signal is opposite.
In the adjustment circuit of present embodiment, the duty ratio of clock signal is to be determined by the value of m, n, and is irrelevant with other factor in the circuit.Below analyze the relation that has provided duty ratio and m, n.For this reason, the setting clock signal is that the time of high level is t1, and for the low level time is t2, the cycle of clock signal is T=t1+t2.At this moment being changed to of voltage on the electric capacity in a clock cycle:
ΔQ=I1
*t1-I2
*t2=(m
*t1-n
*t2)
*I
Because of Δ V=Δ Q/C, D=t1/ (t1+t2), so when steady operation, the duty ratio of clock signal is:
D=n/(n+m)
Below, provide a kind of according to circuit diagram shown in Figure 8, constitute the detecting of clock duty cycle and the concrete structure of correcting circuit by MOS transistor.
The clock signal duty cycle detecting and the correcting circuit of the embodiment of the invention 2, as shown in Figure 9.Because the correcting circuit of Fig. 7 is same fully among the circuit structure of correcting circuit part and the embodiment 1, and the response of system was also as above-mentioned embodiment 1 said, so illustrated here and be omitted in the lump.
Now, only the circuit for detecting to present embodiment carries out, as shown in Figure 6, this circuit includes: inverter, the 1st and the 2nd current switch, a current mirroring circuit (being above-mentioned the 1st current source circuit that is equivalent to) and a biasing circuit (promptly being equivalent to above-mentioned the 2nd current source circuit).Inverter is made up of CMOS transistor M14 and M13, that is, the source ground of transistor M13, its drain and gate is connected with the drain and gate of this M14 respectively, and the source electrode of transistor M14 meets power supply VCC and forms.That the 1st and the 2nd current switching circuit is made up of pair of NMOS transistors M8, M136 and a pair of PMOS transistor M34, M35 respectively or the door.The grid of transistor M8, the M34 of the 1st switch is connected with the transistor M136 of the 2nd switch, the grid of M35, respectively the inversion clock signal and the clock signal Vin of input inverter output.This M8 is connected with the drain electrode of M34, the grounded drain GND of this M35, and the source electrode of this M136 meets power supply VCC.The source electrode of this M8, M136 is received the drain electrode of PMOS transistor 19 together.The source electrode of this M34, M35 is received the drain electrode of PMOS transistor M26 together.Current mirror (source) circuit comprises PMOS transistor M26 and M27, and the grid of this M26 is connected with grid, the drain electrode of PMOS transistor M27, and its source electrode meets power supply VCC, and the M27 drain electrode connects the M37 drain electrode.Nmos pass transistor M19 and M6 constitute biasing circuit, and the grid of this M19 and M37 meets bias voltage Vbias, and its source electrode connects the drain electrode of nmos pass transistor M6 and M36 respectively.The grid of this M23, M6 and M23 is received the drain electrode of the nmos pass transistor M23 of correcting circuit part together.In addition, the drain electrode of above-mentioned transistor M8 is exported charging current to the capacitor C 1 of correcting circuit, and by capacitor C 1 ground connection GND.
The correcting circuit part, being used for clock signal is that 1 o'clock electric current carries out conversion in 1: 1 and to capacitor C 1 charging.Transistor M8, M136 are that clock signal is 0 o'clock a current changeover switch; Transistor M34, M35 are that clock signal is 1 o'clock a current changeover switch.The biasing circuit that transistor M34, M35 and M36, M37 constitute can be setovered to improve the response speed of system to current mirror.And PMOS transistor M25, nmos pass transistor M19, M37 are common the moon grid amplifications (CASCODE) levels altogether, and this grade circuit can reduce the channel length modulation effect effectively.
Below, with reference to reference to Figure 10, illustrate that adjustment circuit of the present invention is to the quick-adjustsing process of clock signal duty cycle.
The change in duty cycle of clock signal is by temperature, the stress of the uneven distribution during encapsulation, and factors such as low-frequency noise cause.Because causing the factor of change in duty cycle is slowly to change, so, also be slowly to change to the duty ratio of clock signal.In the circuit that has improved, the clock signal that duty ratio slowly changes is considered to pulse-width signal (abbreviating PWM as, i.e. pulse width modulation).In abominable applied environment, the duty ratio of clock signal also can acute variation, as strong electromagnetic interference, also can cause violent shake etc. because of medium character or the sudden change that distributes when synchronizing clock signals is propagated in medium.
The duty ratio of clock signal can be set at a definite numerical value, and any variation that deviates from this set point comprises changing slowly and violent sudden change, and can be detected and obtain immediately to proofread and correct, the cycle of correction be 1 to 2 clock signal period.Duty ratio circuit for detecting of the present invention has adopted two kinds of structures, at the fast reaction passage bottleneck problem in the integrated circuit, to embodiment 1 wherein, adopts the way of reciprocity constant-current source to proofread and correct.
In circuit of the present invention, the output of clock signal directly is used in the duty ratio circuit for detecting, eliminated since the imbalance that causes because of the coupling of device etc. in the integrated circuit manufacturing to the influence of clock signal duty cycle.
Figure 10 has briefly drawn the response of clock signal when two different fixing DC level compositions, and as seen from the figure, sinusoidal wave flip-flop is suddenlyd change, and is in actual applications, suitable equally for the situation of DC level composition gradual change.
Shown in Figure 10 in, sinusoidal wave at T1 the DC component direct mutation takes place constantly, at this moment because the DC level of hysteresis comparator is not followed variation at once, so the duty ratio of clock signal will be undergone mutation, still, affected just clock cycle.At T2 constantly, the threshold voltage of hysteresis comparator has compensated the clock signal duty cycle that sinusoidal wave DC component direct mutation causes to be changed, so through after clock cycle only, it is normal that the duty ratio of clock signal will be recovered.
After the threshold voltage of hysteresis comparator rises slightly because of the DC component direct mutation that compensates sine wave, if the sudden change component in the sinewave output remains unchanged, then the threshold voltage of hysteresis comparator is also kept its current potential that is elevated and is remained unchanged, shown in T2--T3 moment waveform among Figure 10.
At T3 constantly, negative sudden change takes place in the DC component of sinewave output, because the DC level of hysteresis comparator can not be followed variation at once, so, the duty ratio of clock signal will be undergone mutation, because sinusoidal wave DC component is to depart from from positive direction, will become to negative direction and will depart from, so affected clock signal may be 1 to 2 cycle (this depends on the maximum step-length that the clock signal duty cycle circuit for detecting may be adjusted).And, figure 10 illustrates affected two clock signals, and T3--T4 cycle and T4--T5 cycle.
At T5 constantly, the variation of the DC level of hysteresis comparator has compensated the variation of the clock signal duty cycle that the negative sudden change of sinusoidal wave DC component causes, thus T5 constantly after, it is normal that the duty ratio of clock signal will be recovered.Simultaneously, if the composition that departs from of negative sinusoidal wave DC component remains unchanged, the departing from composition and also will remain unchanged of the DC level of hysteresis comparator, hysteresis comparator is at the constantly later waveform of T5 as shown in Figure 10.
In above introduction, the adjustment of clock signal duty cycle is aimed at that rapid-action sudden change amount carries out; For the change that is departed from the clock signal duty cycle that causes by low speed, this circuit also can be adjusted and be compensated equally.
In circuit of the present invention, the low pass filter that causes low speed response is removed, so the adjustment of clock signal duty cycle is not subjected to the influence of other partial circuits, and only with the clock signal duty cycle detecting with to adjust the device performance of critical path in the circuit relevant.
In above adjustment circuit, the error between clock signal duty cycle and the required value decays according to index law.The adjusting range of setting each time is 80%, and after then adjusting through N time, the error between the duty ratio of actual clock signal and the value of setting is: (1-80%) N.Be set at 1% as the error of adjusting, then under 80% adjusting range each time, only need 3 clock cycle can finish the target of adjustment.
Above analysis is for by temperature, and the flip-flop that factors such as device mismatch cause departs from same being suitable for, and is to occur in a sinusoidal wave end no matter direct current departs from, or the DC level of hysteresis comparator one end.
Adjust circuit according to clock signal duty cycle of the present invention, can be used for nearly all clock circuit, clock signal duty cycle is adjusted.Since in the Modern Communication System, the extensive use of PLL and crystal oscillator, and the application of this clock dutyfactor adjustment circuit will be very extensive.Can be widely used in digital communication system fields such as multimedia.Characteristics such as it is fast owing to having response speed that clock signal duty cycle of the present invention is adjusted circuit, and anti-electromagnetic interference capability is strong also can be applied to electronic countermeasures, in the equipment such as radar.
Above, with reference to accompanying drawing, disclosed most preferred embodiment of the present invention, but the present invention and be limited to the particular content of the foregoing description.Those skilled in the art accept inspiration of the present invention; be easy to the present invention is made various improvement, modification or replacement; these all should not be considered as and have broken away from spiritual scope of the present invention, and the protection range of patent of the present invention should be limited by affiliated claims.
Claims (9)
1, a kind of long-delay clock pulse width regulating circuit has hysteresis comparator and power supply, it is characterized in that also comprising:
A hysteresis comparator be used for the sine wave signal of an input input and the threshold voltage of another input input are compared, and output has the clock signal of regulation duty ratio;
A circuit for detecting, whether the described clock signal that is used to detect the described hysteresis comparator output of input exists floating sign, and according to floating sign output difference voltage; And
A correcting circuit is used for the difference voltage according to described circuit for detecting output, proofreaies and correct the described threshold voltage of the described hysteresis comparator of input.
2, long-delay clock pulse width regulating circuit according to claim 1 is characterized in that described circuit for detecting has an inverter, the clock signal of input is carried out anti-phase, output inversion clock signal; A current switch carries out switch according to clock signal and inversion clock signal; The 1st current mirroring circuit, described the 1st current mirroring circuit is connected with current switch one input, when described clock signal is high level, the electric capacity of described correcting circuit is charged; The 2nd current mirroring circuit, described the 2nd current mirroring circuit is connected with another input of described current switch; And the 3rd current mirroring circuit, described the 3rd current mirroring circuit is connected with the 2nd current mirroring circuit, when described clock signal is low level, the electric capacity of described correcting circuit is discharged.
3, long-delay clock pulse width regulating circuit according to claim 2 is characterized in that described circuit for detecting also has current source circuit, provides bias current to described current switch.
4, long-delay clock pulse width regulating circuit according to claim 1 is characterized in that described circuit for detecting has: an inverter, carry out anti-phasely to the clock signal of input, and the inversion clock signal is provided; Pair of series the 1st and the 2nd current switch carry out switch according to the inversion clock signal that clock signal and described inverter provide simultaneously; The 1st current source circuit, described the 1st current source circuit one termination power, another termination the 1st current switch when described clock signal is high level, charges to the electric capacity of described correcting circuit; And the 2nd current source circuit, described the 2nd current source circuit one termination the 2nd current switch, other end ground connection when described clock signal is low level, is discharged to the electric capacity of described correcting circuit.
5, according to claim 2,3 or 4 each described long-delay clock pulse width regulating circuits, it is characterized in that described current switch be constitute by two MOS transistor or the door.
6, according to claim 2,3 or 4 each described long-delay clock pulse width regulating circuits, it is characterized in that described current mirroring circuit is that drain electrode, the grid of a MOS transistor is connected with the grid of another MOS transistor, the source electrode of described two MOS transistor connects power supply, and the drain electrode of described another MOS transistor is an output.
7,, it is characterized in that described correcting circuit is to be made of the change-over circuit and the comparison circuit of voltage to electric current according to each described long-delay clock pulse width regulating circuit of claim 1 to 4.
8, long-delay clock pulse width regulating circuit according to claim 7 is characterized in that described correcting circuit has the current source circuit that is made of operational amplifier, nmos pass transistor and resistance.
9, long-delay clock pulse width regulating circuit according to claim 7 is characterized in that comprising the circuit that MOS transistor and electric capacity are formed by described electric current to the change-over circuit of voltage.
Priority Applications (10)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB001059971A CN1152288C (en) | 2000-04-24 | 2000-04-24 | Short-delay MF or HF clock pulse width regulating circuit |
| KR1020027014213A KR100651150B1 (en) | 2000-04-24 | 2001-04-19 | Delay clock pulse-width adjusting circuit for intermediate frequency or high frequency |
| AU62015/01A AU6201501A (en) | 2000-04-24 | 2001-04-19 | Delay clock pulse-width adjusting circuit for intermediate frequency or high frequency |
| PCT/CN2001/000563 WO2001082485A1 (en) | 2000-04-24 | 2001-04-19 | Delay clock pulse-width adjusting circuit for intermediate frequency or high frequency |
| EP01935925A EP1289149B1 (en) | 2000-04-24 | 2001-04-19 | Delay clock pulse-width adjusting circuit for intermediate frequency or high frequency |
| AT01935925T ATE302504T1 (en) | 2000-04-24 | 2001-04-19 | DELAY CLOCK PULSE WIDTH ADJUSTMENT CIRCUIT FOR INTERMEDIATE FREQUENCY OR HIGH FREQUENCY |
| JP2001579456A JP4354145B2 (en) | 2000-04-24 | 2001-04-19 | Delay clock pulse width adjustment circuit for intermediate frequency or high frequency |
| DE60112749T DE60112749D1 (en) | 2000-04-24 | 2001-04-19 | DELAY ACTUATING PULSE WIDE ADJUSTMENT CIRCUIT FOR INTERMEDIATE FREQUENCY OR HIGH FREQUENCY |
| FI20021878A FI20021878A (en) | 2000-04-24 | 2002-10-21 | Delay clock pulse width control circuit for intermediate frequencies or high frequencies |
| US10/278,888 US6801068B2 (en) | 2000-04-24 | 2002-10-24 | Delay clock pulse-width adjusting circuit for intermediate frequency or high frequency |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB001059971A CN1152288C (en) | 2000-04-24 | 2000-04-24 | Short-delay MF or HF clock pulse width regulating circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1321003A true CN1321003A (en) | 2001-11-07 |
| CN1152288C CN1152288C (en) | 2004-06-02 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB001059971A Expired - Fee Related CN1152288C (en) | 2000-04-24 | 2000-04-24 | Short-delay MF or HF clock pulse width regulating circuit |
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| Country | Link |
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| CN (1) | CN1152288C (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104866008A (en) * | 2015-05-13 | 2015-08-26 | 中国电子科技集团公司第四十一研究所 | Clock system |
| CN109100564A (en) * | 2017-06-21 | 2018-12-28 | 浙江大华技术股份有限公司 | A kind of signal fluctuation detection circuit |
| CN112382078A (en) * | 2020-12-07 | 2021-02-19 | 北京博纳电气股份有限公司 | Automatic correction method for communication waveform pulse width of instrument |
| US11196408B2 (en) | 2017-06-21 | 2021-12-07 | Zhejiang Dahua Technology Co., Ltd. | System and method for mixed transmission of signals and power supply through a single cable |
-
2000
- 2000-04-24 CN CNB001059971A patent/CN1152288C/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104866008A (en) * | 2015-05-13 | 2015-08-26 | 中国电子科技集团公司第四十一研究所 | Clock system |
| CN104866008B (en) * | 2015-05-13 | 2017-10-03 | 中国电子科技集团公司第四十一研究所 | A kind of clock system |
| CN109100564A (en) * | 2017-06-21 | 2018-12-28 | 浙江大华技术股份有限公司 | A kind of signal fluctuation detection circuit |
| US11196408B2 (en) | 2017-06-21 | 2021-12-07 | Zhejiang Dahua Technology Co., Ltd. | System and method for mixed transmission of signals and power supply through a single cable |
| CN112382078A (en) * | 2020-12-07 | 2021-02-19 | 北京博纳电气股份有限公司 | Automatic correction method for communication waveform pulse width of instrument |
| CN112382078B (en) * | 2020-12-07 | 2022-09-27 | 北京博纳电气股份有限公司 | Automatic correction method for communication waveform pulse width of instrument |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1152288C (en) | 2004-06-02 |
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