CN215956362U - Jitter frequency adjusting circuit and chip - Google Patents
Jitter frequency adjusting circuit and chip Download PDFInfo
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- CN215956362U CN215956362U CN202121777712.6U CN202121777712U CN215956362U CN 215956362 U CN215956362 U CN 215956362U CN 202121777712 U CN202121777712 U CN 202121777712U CN 215956362 U CN215956362 U CN 215956362U
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Abstract
The utility model provides a frequency jitter regulating circuit and a chip, wherein the circuit comprises a sampling module, a frequency jitter regulating circuit and a frequency jitter regulating circuit, wherein the sampling module is connected with an external load circuit provided with a switching tube and is configured to acquire an electric power signal of the external load circuit; the oscillation module is configured to output an oscillation signal; the control module is connected with the sampling module and the oscillation module respectively, and is configured to control a jitter interval of the frequency of the oscillation signal according to the load degree represented by the power signal and generate a driving signal based on the frequency of the oscillation signal; and the driving module is respectively connected with the switch tube and the control module, and is configured to control the on-off state of the switch tube according to the driving signal. When the voltage at two ends of the load is high or the current flowing through the load is large, the jitter interval of the frequency of the driving signal for controlling the switching tube is reduced, and when the wire mesh compensation is performed, the obtained duty ratio of the switching tube is accurate, the error is small, and therefore the accuracy of the wire mesh compensation is improved.
Description
Technical Field
The utility model relates to the technical field of integrated circuits, in particular to a jitter frequency adjusting circuit and a chip.
Background
In the conventional driving circuit for driving the switch, since the frequency of the driving switch is in a fixed state (as shown in fig. 1 a), circuit noise generated in the circuit is too concentrated (as shown in fig. 1 b), so that the circuit noise is too large, electromagnetic interference is generated on electronic components in the circuit, and the circuit performance is affected.
In order to improve this problem, the prior art usually configures a frequency jittering function in the circuit, so that the frequency of the driving switch is in a certain range. As shown in fig. 2a, when the circuit is configured with the frequency jittering function, the frequency of the driving switch fluctuates within a fixed range. As shown in fig. 2b, the circuit noise driving the switch is reduced since the frequency is in a certain range, rather than concentrated on a certain frequency.
In order to provide more balanced electric energy to a load, a net compensation function is usually configured for a circuit, and generally, the duty ratio of a driving switch in the circuit is obtained, a net voltage input by a power supply is obtained, a required adjustment ratio is determined based on the net voltage, and then the duty ratio of the driving switch is determined, so that net compensation is realized.
However, when the frequency of the driving switch is in a fluctuating state, the period of the driving switch also changes simultaneously, and the duty cycle of the driving switch is obtained on the premise that the period of the driving switch is obtained, and the duty cycle of the driving switch in the period of the obtained changing state is obviously inaccurate, so that the precision of the wire mesh compensation is seriously affected, balanced electric energy cannot be provided for the load, and the voltage and the current of the load are not favorably and stably controlled.
SUMMERY OF THE UTILITY MODEL
Therefore, an object of the present invention is to provide a jitter frequency adjusting circuit and a chip, which can improve the precision of the compensation of the wire mesh, avoid the problem of excessive noise caused by the over-concentrated frequency of the circuit, and prevent the generation of electromagnetic interference on the electronic components in the circuit.
In a first aspect, a jitter frequency adjustment circuit includes:
the sampling module is connected with an external load circuit provided with a switching tube and is configured to acquire a power signal of the external load circuit;
an oscillation module configured to output an oscillation signal;
the control module is connected with the sampling module and the oscillation module respectively, and is configured to control a jitter interval of the frequency of the oscillation signal according to the load degree represented by the power signal and generate a driving signal based on the frequency of the oscillation signal;
and the driving module is respectively connected with the switch tube and the control module, and is configured to control the on-off state of the switch tube according to the driving signal.
Preferably, the jitter frequency adjusting circuit further comprises:
the frequency jittering control module is respectively connected with the control module and the oscillation module;
the control module is also configured to compare the power signal with a reference signal and generate a comparison result;
the frequency-shaking control module is configured to generate frequency-modulated current according to the comparison result;
the oscillation module is further configured to receive the frequency modulated current and output an oscillation signal.
Preferably, the jitter frequency adjusting circuit further comprises:
the network compensation module is connected with the control module and is configured to acquire the duty ratio of the driving signal and generate a compensation signal based on the duty ratio and the standard power signal;
the control module is further configured to generate a drive signal as a function of the compensation signal and the frequency.
Preferably, the oscillation module includes:
the constant current source is respectively connected with the external constant current power supply circuit and the frequency jitter control module;
one end of the switch unit is connected with the constant current source;
and one end of the capacitor unit is connected with the other end of the switch unit and the control module respectively, and the other end of the capacitor unit is connected with the reference ground end.
Preferably, the constant current source comprises a first constant current source and a second constant current source, the switch unit comprises a first switch and a second switch, the first constant current source, the first switch, the second switch and the second constant current source are sequentially connected in series, a common junction formed by the first switch and the second switch is connected with one end of the capacitor unit, and the first constant current source and the second constant current source are respectively connected with the external constant current power supply circuit.
Preferably, the jitter frequency control module includes:
the first adjusting unit is connected with the first constant current source and the control module respectively, and is configured to adjust the current flowing through the first switch according to the comparison result;
the second adjusting unit is connected with the second constant current source and the control module respectively, and the second adjusting unit is configured to adjust the current flowing through the second switch according to the comparison result.
Preferably, the control module comprises:
the first comparison unit is connected with one end of the capacitor unit and configured to acquire a voltage at one end of the capacitor unit and compare the voltage with a preset voltage interval to generate a first comparison result;
and the second comparison unit is connected with the sampling module and is configured to acquire the power signal and compare the power signal with a preset power value to generate a second comparison result.
Preferably, the oscillation module further includes:
and the switch control unit is connected with the first comparison unit and is configured to generate a switch control signal for controlling the switch unit according to the comparison result, and the period of the switch control signal is the same as that of the oscillation signal.
Preferably, the dither frequency control module includes a digital-to-analog converter.
In a second aspect, a dither regulation chip includes the dither regulation circuitry of the first aspect.
The frequency jitter regulating circuit and the chip provided by the utility model can skillfully use the voltage/current signal of an external load circuit as the independent variable for regulating the output frequency of the driving signal, thereby realizing the adjustment of the on-off frequency of the switching tube, when the load degree represented by the power signal is larger, the jitter interval of the frequency of the oscillation signal can be controlled to be reduced, so that when the voltage at two ends of the load is higher or the current flowing through the load is larger, the jitter interval of the frequency of the driving signal for controlling the switching tube is reduced, when the wire mesh compensation is carried out, the obtained duty ratio of the switching tube is more accurate and the error is smaller, thereby improving the accuracy of the wire mesh compensation, meanwhile, when the voltage at two ends of the load is higher or the current flowing through the load is larger, the jitter interval of the frequency of the driving signal for controlling the switching tube is larger, and the problem of overlarge noise caused by the over-concentrated frequency of the circuit can be avoided, electromagnetic interference to electronic components in the circuit is prevented.
Drawings
In order to more clearly illustrate the detailed description of the utility model or the technical solutions in the prior art, the drawings that are needed in the detailed description of the utility model or the prior art will be briefly described below. In the drawings, elements or portions are not necessarily drawn to scale.
Fig. 1a is a frequency diagram of a driving switch provided in the background art.
Fig. 1b is a schematic diagram of noise generated by the driving switch provided in the background art.
Fig. 2a is a schematic frequency diagram of a driving switch configured with a frequency jittering function provided in the prior art.
Fig. 2b is a schematic diagram of noise generated by the driving switch after the frequency jittering function is configured as provided in the prior art.
Fig. 3 is a block diagram of a jitter frequency adjusting circuit after adding a jitter frequency control module.
FIG. 4 is a block diagram of a jitter frequency adjustment circuit with the addition of a net compensation module.
Fig. 5 is a block diagram of the jitter frequency adjusting circuit in fig. 3.
Fig. 6 is a circuit diagram of the jitter frequency adjusting circuit in fig. 3.
FIG. 7 is a block diagram of the control module of FIG. 3.
FIG. 8 is a timing diagram of the circuit of FIG. 5.
Fig. 9 is a diagram illustrating a conversion of the power signal magnitude and the jitter interval of the oscillation signal frequency.
Fig. 10 is another conversion diagram of the jitter interval of the power signal magnitude and the oscillation signal frequency.
Detailed Description
Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. The following examples are only for illustrating the technical solutions of the present invention more clearly, and therefore are only examples, and the protection scope of the present invention is not limited thereby.
The first embodiment is as follows:
a jitter frequency regulating circuit 1, see fig. 3, comprises a sampling module 10, an oscillation module 20, a control module 30 and a driving module 40. Wherein, the sampling module 10 is connected with an external load circuit 50 provided with a switch tube 51, and the sampling module 10 is configured to obtain a power signal of the external load circuit 50. An oscillation module 20 configured to output an oscillation signal. And the control module 30 is connected with the sampling module 10 and the oscillation module 20 respectively, and the control module 30 is configured to control a jitter interval of the frequency of the oscillation signal according to the load degree represented by the power signal and generate the driving signal based on the frequency of the oscillation signal. And the driving module 40 is connected with the switch tube 51 and the control module 30 respectively, and the driving module 40 is configured to control the on-off state of the switch tube 51 according to the driving signal.
It should be noted that the "external load circuit 50" described in the present embodiment is "external" with respect to the dither frequency adjusting circuit 1, is not "external" to the carrier on which the dither frequency adjusting circuit 1 is located, and does not limit the specific location of the "external load circuit 50". Similarly, the present embodiment is similarly applicable to the following external peripheral circuit, external electronic components, and the like.
In this embodiment, the switch tube 51 may be a triode, a field effect transistor, or the like, and in actual application, a manufacturer may select a type of the switch tube 51 according to an actual application requirement of the load circuit 50, so as to determine a connection relationship of the switch tube 51.
In this embodiment, the external load circuit 50 may include a load 52, the load 52 may be connected to the switch tube 51, and the duty ratio of the switch tube 51 may be controlled to control the voltage across the load 52 and the current flowing through the load 52.
In this embodiment, the power signal of the external load circuit 50 may be a voltage signal and/or a current signal at the sampling output terminal of the external load circuit 50, which is used to indicate the power consumption of the load 52. For example, assuming that the acquired power signal is a voltage value, the greater the voltage value is, the greater the power consumption of the load 52 is. The smaller the voltage value, the lighter the power consumption of the load 52. Assuming that the acquired power signal is a current value, the greater the power consumption level of the load 52. The smaller the current value, the lighter the power consumption of the load 52.
In this embodiment, the oscillating module 20 may include a square wave generating circuit, a triangular wave generating circuit, a sawtooth wave generating circuit, and the like, and the type of the circuit for generating the oscillating signal in the oscillating module 20 is not particularly limited. In addition, the oscillation signal may be applied to the same type of signal generated by the circuit type, for example, when the oscillation module 20 is a square wave generating circuit, the oscillation signal may be a square wave signal.
In the present embodiment, the control module 30 is configured to control the jitter interval of the frequency of the oscillation signal according to the load degree characterized by the power signal. The jitter interval of the frequency can be regarded as an interval formed by an upper frequency limit and a lower frequency limit of the oscillation signal.
It should be noted that the oscillation signal may be regarded as a reference clock signal, and the period of the driving signal may be consistent with the period of the oscillation signal, that is, the frequency of the driving signal may be the same as the frequency of the oscillation signal. When the jitter interval controlling the frequency of the oscillation signal changes, the jitter interval controlling the frequency of the drive signal may also change correspondingly.
In the present embodiment, the control module 30 also generates the driving signal based on the frequency of the oscillation signal. The driving module 40 is configured to control an on-off state of the switching tube 51 according to the driving signal. For example, the on-off state of the switching tube 51 is controlled by the high-low level of the driving signal to adjust the power signal flowing through the external load circuit 50, when the switching tube 51 is an N-type MOS tube, the switching tube 51 is controlled to be on when the driving signal is high level, and the switching tube 51 is controlled to be off when the driving signal is low level.
In addition, as described in the background art, in the line network compensation process, the duty ratio of the driving switch needs to be acquired, and since the rising edge or the falling edge of the gate voltage of the driving switch generally needs to be acquired in the duty ratio acquisition process, the duty ratio of the driving switch is further determined. However, when the jitter interval of the frequency of the driving switch is large, the duty ratio of the driving switch is not accurately obtained, and the accuracy of the net compensation is affected. When the jitter interval of the frequency of the driving switch is small, the noise of the circuit is too concentrated and the noise is too large.
In the frequency jitter adjusting circuit 1 of this embodiment, the voltage/current signal of the external load circuit 50 can be skillfully used as an independent variable for adjusting the output frequency of the driving signal, so as to adjust the on-off frequency of the switching tube 51, when the load represented by the power signal is larger, the jitter interval of the frequency of the oscillating signal can be controlled to be reduced, so that when the voltage at two ends of the load 52 is higher or the current flowing through the load 52 is larger, the jitter interval of the frequency of the driving signal for controlling the switching tube 51 is reduced, when the wire mesh compensation is performed, the obtained duty ratio of the switching tube 51 is more accurate and the error is smaller, thereby improving the accuracy of the wire mesh compensation, and meanwhile, when the voltage at two ends of the load 52 is higher or the current flowing through the load 52 is larger, the jitter interval of the frequency of the driving signal for controlling the switching tube 51 is larger, thereby avoiding the problem of excessive noise caused by over-concentrated frequency of the circuit, and electromagnetic interference to electronic components in the circuit and the outside is reduced.
Further, in some embodiments, referring to fig. 3, the jitter frequency adjusting circuit 1 may further include a jitter frequency control module 60. The dither frequency control module 60 is connected to the control module 30 and the oscillation module 20, respectively. The control module 30 is further configured to compare the power signal with a reference signal, and generate a comparison result. The frequency-dithering control module 60 is configured to generate a frequency-modulated current according to the comparison result. The oscillation module 20 is further configured to receive the frequency modulated current and output an oscillation signal.
In the present embodiment, the reference signal may be set according to actual conditions, and the number of the reference signals may be one or more. For example, when there is one reference signal, the comparison result may include that the power signal is greater than the reference signal, the power signal is equal to the reference signal, the power signal is greater than the reference signal, and the like; when the reference signal is plural, the plural reference signals include a first reference signal and a second reference signal, the comparison result may include that the power signal is less than or equal to the first reference signal, the power signal is between the first reference signal and the second reference signal, the power signal is greater than or equal to the second reference signal, and the like.
In this embodiment, the jitter frequency control module 60 may include a digital-to-analog converter that converts a digital signal representing the comparison result into an analog signal representing the frequency-modulated current. For example, when the reference signal includes a first reference signal and a second reference signal, a digital signal "01" may indicate that the power signal is less than or equal to the first reference signal, a digital signal "10" may indicate that the power signal is between the first reference signal and the second reference signal, a digital signal "11" may indicate that the power signal is greater than or equal to the second reference signal, a frequency modulation current corresponding to the digital signal "01" is-4 μ Α, a frequency modulation current corresponding to the digital signal "10" is-2 μ Α, and a frequency modulation current corresponding to the digital signal "11" is-1 μ Α. Therefore, when the digital signal "01" is acquired, the digital-to-analog converter outputs a frequency-modulated current having a current of-4 μ a to the oscillation module 20.
In this embodiment, the frequency modulation current may be output to the oscillation module 20 according to a comparison result generated by comparing the power signal with the reference signal, and the oscillation module 20 adjusts a jitter interval of the frequency of the oscillation signal based on the frequency modulation current, so as to change the jitter interval of the frequency of the driving signal.
It should be noted that the reference signal may also be regarded as curve data that changes linearly or nonlinearly, so that the power signal may be compared with the curve to generate a comparison result, and further change the jitter interval of the frequency of the driving signal.
In the present embodiment, the dither frequency adjusting circuit 1 can be preferentially applied to an environment where a voltage across the load 52 is large, a current flowing through the load 52 is large, a constant current circuit, a constant voltage circuit, or the like.
Further, in some embodiments, the oscillation module 20 includes a constant current source, a switching unit, and a capacitance unit 23. The constant current source is connected to the external constant current supply circuit 24 and the dither frequency control module 60, respectively. One end of the switch unit is connected with the constant current source. One end of the capacitor unit 23 is connected to the other end of the switch unit and the control module 30, respectively, and the other end of the capacitor unit 23 is connected to the reference ground.
In this embodiment, the number of the constant current sources may be one or more, and the constant current sources may include current sources. The switching unit includes one or more switches. The oscillation module 20 adjusts the frequency of the oscillation signal by charging and discharging the capacitor unit 23.
Further, in some embodiments, referring to fig. 5, the constant current source may comprise a first constant current source IPAnd a second constant current source INThe switching unit may comprise a first switch 21 and a second switch 22, a first constant current source IPA first switch 21, a second switch 22, a second constant current source INIn series, a common node formed by the first switch 21 and the second switch 22 can be connected to one end of the capacitor unit 23, and the first constant current source IPA second constant current source INMay be connected to the external constant current supply circuit 24, respectively.
Note that the "common node" in the present embodiment is also used to describe the circuit configuration of the dither control circuit 1, and should not be limited to a specific cross point formed by connecting the wire connected to the first switch 21 and the wire connected to the second switch 22, but may be a wire extending beyond the specific cross point formed by connecting the wire connected to the first switch 21 and the wire connected to the second switch 22, and the circuit configuration of the oscillation module 20 will be described here by using only the "common node".
It should be noted that, in the present embodiment, the external constant current supply circuit 24 may supply the first constant current sources I to the first switches 21 respectivelyPA second constant current source I is supplied to the second switch 22N. First constant current source IPAnd a secondConstant current source INMay or may not be the same, where for the first constant current source IPAnd a second constant current source INThe size of (d) is not particularly limited.
As shown in fig. 6, the capacitor unit 23 may be a capacitor C. The first switch 21 may be a switch S1, the second switch 22 may be a switch S2, and the voltage forming the common junction between the switch S1 and the switch S2 may be regarded as VC. The switch S1 and the switch S2 form a common node to connect the control module 30, and the control module 30 further receives an upper voltage threshold VthHAnd lower voltage threshold limit VthL。
In this embodiment, when the switch S1 is turned on and the switch S2 is turned off, the capacitor C is charged, and the control voltage Vc rises; when the switch S1 is turned off and the switch S2 is turned on, the capacitor C is discharged and the control voltage Vc drops.
In this embodiment, the frequency-modulated current may include a first frequency-modulated current CTRipAnd a second frequency-modulated current CTRin. First frequency modulation current CTRipAnd a first constant current source IPThe magnitude of the current flowing through the switch S1 is determined, the larger the current flowing through the switch S1 is, the shorter the charging time of the capacitor C is, and the shorter the period of the oscillation signal is, the larger the frequency of the oscillation signal is. Similarly, the second current CTRiAnd a second constant current source INThe magnitude of the current flowing through the switch S2 is determined, and the larger the current flowing through the switch S2 is, the shorter the discharge time of the capacitor C is, and the shorter the period of the oscillation signal is, the larger the frequency of the oscillation signal is.
Further, in some embodiments, the jitter frequency control module 60 may include a first adjusting unit 61 and a second adjusting unit 62. Wherein, the first adjusting unit 61 and the first constant current source IPThe control module 30 is respectively connected, and the first adjusting unit 61 is configured to adjust the magnitude of the current flowing through the first switch 21 according to the comparison result. A second regulating unit 62 and a second constant current source INThe control module 30 is respectively connected, and the second adjusting unit 62 is configured to adjust the current flowing through the second switch 22 according to the comparison result.
In the present embodiment, assuming that the constant current source is 100 μ a, when the power signal is smaller than the reference signal, the first frequency modulation current is adjusted from ± 3uA to ± 5uA, and the current interval flowing through the switch is [95uA, 105uA ]. When the power signal is larger than the reference signal, the first frequency modulation current is adjusted to +/-3 uA from +/-5 uA, and the current flowing through the switch is in a range of [97uA, 103uA ].
Further, in some embodiments, referring to fig. 7, the control module 30 includes:
the first comparing unit 31 is connected with one end of the capacitor unit 23, and the first comparing unit 31 is configured to obtain a voltage at one end of the capacitor unit 23 and compare the voltage with a preset voltage interval to generate a first comparison result;
and a second comparing unit 32 connected to the sampling module 10, wherein the second comparing unit 32 is configured to obtain the power signal and compare the power signal with a preset power value to generate a second comparison result.
In this embodiment, the preset voltage interval may be defined by an upper voltage threshold limit VthHAnd lower voltage threshold limit VthLIs determined. Specifically, the upper voltage threshold limit V may be set based on actual demandthHAnd lower voltage threshold limit VthLThe upper limit of voltage threshold V is shown in the following formulas (1) and (2)thHAnd lower voltage threshold limit VthLIs related to the charging and discharging periods of the capacitor unit 23. When the first comparison result indicates that the voltage Vc of one end of the capacitor unit 23 is the upper limit V of the voltage thresholdthHWhen the voltage Vc of one end of the capacitor unit 23 is decreased, the first switch 21 may be controlled to be turned off, and the second switch 22 may be controlled to be turned on, so that the capacitor unit 23 discharges; when the first comparison result indicates that the voltage Vc of one end of the capacitor unit 23 is the lower limit V of the voltage thresholdthLAt this time, the first switch 21 is controlled to be turned on, the second switch 22 is controlled to be turned off, the capacitor unit 23 is charged, and the voltage Vc at one end of the capacitor unit 23 is increased. The sum of the charging period of the capacitor unit 23 and the discharging period of the capacitor unit 23 is the period of the oscillation signal, and the period of the oscillation signal is consistent with the period of the driving signal. Therefore, when the sum of the charging period and the discharging period of the capacitor unit 23 is changed, the period of the driving signal is also changed accordingly.
In addition, the first comparing unit 31 may include a plurality of comparators, wherein one comparator is used for comparing the voltage Vc of one end of the capacitor unit 23 with the upper limit V of the voltage thresholdthHComparing; the other comparator is used for comparing the voltage Vc at one end of the capacitor unit 23 with the lower limit V of the voltage thresholdthLA comparison is made.
In this embodiment, the preset power value may be set based on the actual requirement, for example, the preset power value may be a value, and the second comparison result may include power represented by a power signal greater than the preset power value and power represented by a power signal less than or equal to the preset power value. That is, the larger the power signal is, the smaller the jitter interval of the frequency of the oscillation signal can be.
In addition, the preset power value may also be a plurality of values, and the plurality of values may be combined to form a plurality of intervals, in this case, the second comparison result may include an interval in which the power signal is located, and the magnitudes of the first frequency modulation current and the second frequency modulation current may be adjusted based on the interval in which the power signal is located, so as to adjust the magnitudes of the currents flowing through the first switch 21 and the second switch 22, as shown in the following expressions (1) and (2), when the magnitudes of the currents flowing through the first switch 21 and the second switch 22 are changed, the charging period and the discharging period of the capacitor unit 23 are also changed, and the sum of the charging period and the discharging period of the capacitor unit 23 is also changed accordingly, so that the period and the frequency of the oscillation signal are changed, and further the frequency of the driving signal is changed, so that the jitter interval of the frequency of the driving signal is reduced.
It should be noted that, in the present embodiment, the sampling module may include a voltage sampling unit and/or a current sampling unit. The voltage sampling unit is connected to the external load circuit 50 and the control module 30, respectively, and is configured to acquire a voltage of the load 52 and transmit the voltage to the control module 30. The current sampling unit is connected to the external load circuit 50 and the control module 30, respectively, and is configured to acquire a current flowing through the load 52 and transmit the current to the control module 30.
Further, in some embodiments, the oscillation module further comprises:
and a switching control unit connected to the first comparing unit 31, the switching control unit being configured to generate a switching control signal for controlling the switching unit according to the comparison result, the period of the switching control signal being the same as the period of the oscillation signal.
In this embodiment, the control module 30 can also output the first switch control signal SPThe first switch 21 is controlled to be turned on or off, and the second switch control signal S can be outputtednThe second switch 22 is controlled to be turned on or off.
In this embodiment, the switch control signal is used to control the switch to be turned on or off. When the switch control signal outputs high and low levels, the corresponding switch is controlled to be conducted. The effective level of the switch on and off is determined according to the type and connection mode of the actual switch. For example, when the first comparison result is that the voltage Vc of one end of the capacitor unit 23 is the upper limit V of the voltage thresholdthHAt this time, the first switch 21 is turned off, the second switch 22 is turned on, and the capacitor unit 23 is discharged. When the first comparison result indicates that the voltage Vc of one end of the capacitor unit 23 is the lower limit V of the voltage thresholdthLAt this time, the first switch 21 is controlled to be on, and the second switch 22 is controlled to be off, so that the capacitor unit 23 is charged.
Referring to FIG. 8, when the common node voltage Vc formed between the switch S1 and the switch S2 is the upper limit V of the voltage thresholdthHFirst switch control signal SPOutput a low level, second switch control signal SnAnd outputting high level, and reducing the control voltage Vc. When the voltage Vc is the lower limit of the jitter frequency, the first switch control signal SPOutput a high level, second switch control signal SnThe output is low level and the control voltage Vc rises. At this time, the first switch control signal SPA second switch control signal SnThe periods of the driving signal CLK are all T1+ T2, and the calculation formulas of T1 and T2 are shown in formula (1) and formula (2).
Wherein T1 represents the time for charging the capacitor C, i.e. the voltage VCThe rising period, T2, represents the time for discharging the capacitor C, i.e. the period during which the voltage VC falls, VthHDenotes the upper voltage threshold, VthLDenotes the lower voltage threshold, APIndicates the magnitude of the current flowing through switch S1, AnIndicating the magnitude of the current flowing through switch S2.
In the present embodiment, the switch tube 51 may be driven based on the driving signal CLK, and the frequency of the driving signal CLK and the frequency of the driving switch tube 51 are in a positive correlation. Therefore, when the frequency range of the driving signal CLK is small, the frequency of the driving switch 51 is also small. Meanwhile, based on the above description, the frequency of the driving signal CLK and the capacity of the capacitor C, the upper limit of the voltage threshold VthHLower voltage threshold limit VthLThe magnitude of the current flowing through the switch S1 and the magnitude of the current flowing through the switch S2.
Further, in some embodiments, the magnitude of the power signal and the magnitude of the jitter interval of the frequency of the oscillating signal are inversely related.
In the present embodiment, when the power signal V isFBWhen the frequency is high, the jitter frequency control module 60 may output the first frequency-modulated current CTRipAnd a first frequency-modulated current CTRinTo control the magnitude of current flowing through switch S1 and switch S2, and thus adjust the magnitude of T1 and T2. Referring to fig. 9, in practical application, when the power signal V is appliedFBThe larger the frequency range of the oscillation signal, the smaller.
In order to more clearly illustrate the power signal VFBA first frequency modulation current CTRipA second frequency modulation current CTRinThe following examples can be cited as the relationship between the frequency f of the oscillation signal, as shown in the following table (1):
table (1):
| VFB | CTRip | CTRin | interval f |
| V1 | ±N×M | ±N×M | [-F(N)，F(N)] |
| V2 | ±(N-1)×M | ±(N-1)×M | [-F(N-1)，F(N-1)] |
| ... | ... | ... | ... |
| VN | ±M | ±M | [-F(1)，F(1)] |
Wherein V1 to VN are from small to large, and F (1) to F (N) are from small to large. Based on the table, it can be seen that the power signal VFBThe larger the first frequency-modulated current CTRipAnd a second frequency-modulated current CTRinThe smaller the f interval. The smaller the f interval is, the smaller the period floating of the driving switch is, and therefore the accuracy of obtaining the duty ratio can be improved.
For example, the first current source IPAnd a second current source InAre all 100uA, when the first frequency modulation current CTRipAnd a second frequency-modulated current CTRinWhen the current is +/-5 uA, the first current source IPAnd a second current source InAll intervals of (1) are [95uA, 105uA]. When the first frequency modulation current CTRipAnd a second frequency-modulated current CTRinWhen the current is +/-4 uA, the first current source IPAnd a second current source InAll intervals of (1) are [96uA, 104uA]. When the first frequency modulation current CTRipAnd a second frequency-modulated current CTRinWhen all are +/-3 uA, the first current source IPAnd a second current source InAll intervals of (1) are [97uA, 103uA]. The interval of f is also changed according to the above formula (1) and formula (2).
Besides the linear variation shown in fig. 9, the adjustment of the frequency of the oscillation signal may also be performed by the step variation shown in fig. 10, and the adjustment principles are the same.
Further, in some embodiments, referring to fig. 4, the jitter frequency adjusting circuit 1 further includes:
a net compensation module 70 connected to the control module 30, wherein the net compensation module 70 is configured to obtain a duty ratio of the driving signal and generate a compensation signal based on the duty ratio and the standard power signal;
the control module 30 is further configured to generate a drive signal based on the compensation signal and the frequency.
In this embodiment, the input power source 80 may be configured to provide power to the external load circuit 50, so as to control the switch tube 51 to adjust the voltage/current of the external load circuit 50. However, since the voltage/current inputted by the input power 80 may have a certain deviation from the standard voltage/current, it needs to be compensated by the net compensation module 70, so that the voltage/current inputted by the input power 80 to the external load circuit 50 meets the preset requirement.
The sampling module 10 can acquire the power signal V at both ends of the external load circuit 50FBThe power signal V is converted intoFBThe control module 30, the oscillation module 20 and the dither control module 60 may be based on VFBThe frequency of the driving signal is adjusted, and the driving module 40 controls the on-off frequency of the switching tube 51 based on the frequency of the driving signal. The net compensation module 70 can obtain the duty ratio of the driving signal, determine the voltage/current inputted by the input power 80, and compare the voltage/current with the standard power signal to generate the compensation signal. For example, when the voltage/current is lower than the standard power signal, a compensation signal is generated to compensate the voltage/current input by the input power 80, so that the voltage/current input by the input power 80 can be increased to the standard power signal. When the voltage/current is higher than the standard power signal, a compensation signal is generated to compensate the voltage/current input by the input power source 80, so that the voltage/current input by the input power source 80 can be reduced to the standard power signal.
In this embodiment, the standard power signal may be set according to an actual usage scenario, and the standard power signal may be a voltage signal or a current signal. In the jitter frequency adjusting circuit 1, the on-off frequency of the switch tube 51 can be based on VFBAnd (6) adjusting. Therefore, in the process of line network compensation, the fluctuation of the on-off period of the switching tube 51 is small, so that the duty ratio of the switching tube 51 can be accurately obtained, and the result of line network compensation is more expected.
Example two:
a jitter frequency regulation chip comprises the jitter frequency regulation circuit.
For a brief description, the chip provided in the embodiment may refer to the corresponding content in the foregoing embodiments.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the utility model has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the present invention, and they should be construed as being included in the following claims and description.
Claims (10)
1. A jitter frequency adjustment circuit, comprising:
the sampling module is connected with an external load circuit provided with a switching tube and is configured to acquire a power signal of the external load circuit;
an oscillation module configured to output an oscillation signal;
the control module is connected with the sampling module and the oscillation module respectively, and is configured to control a jitter interval of the frequency of the oscillation signal according to the load degree represented by the power signal and generate a driving signal based on the frequency of the oscillation signal;
and the driving module is respectively connected with the switch tube and the control module, and is configured to control the on-off state of the switch tube according to the driving signal.
2. The jitter adjustment circuit of claim 1, wherein the jitter adjustment circuit further comprises:
the frequency jittering control module is respectively connected with the control module and the oscillation module;
the control module is further configured to compare the power signal with a reference signal, and generate a comparison result;
the frequency jitter control module is configured to generate a frequency modulation current according to the comparison result;
the oscillation module is further configured to receive the frequency modulated current and output the oscillation signal.
3. The jitter adjustment circuit of claim 2, wherein the jitter adjustment circuit further comprises:
a net compensation module connected to the control module, the net compensation module configured to obtain a duty cycle of the driving signal and generate a compensation signal based on the duty cycle and a standard power signal;
the control module is further configured to generate the drive signal as a function of the compensation signal and the frequency.
4. The jitter frequency adjustment circuit of claim 2, wherein the oscillation module comprises:
the constant current source is respectively connected with the external constant current power supply circuit and the frequency jitter control module;
one end of the switch unit is connected with the constant current source;
and one end of the capacitor unit is connected with the other end of the switch unit and the control module respectively, and the other end of the capacitor unit is connected with a reference ground end.
5. The frequency jitter regulating circuit of claim 4, wherein the constant current source comprises a first constant current source and a second constant current source, the switch unit comprises a first switch and a second switch, the first constant current source, the first switch, the second switch and the second constant current source are sequentially connected in series, a common junction formed by the first switch and the second switch is connected with one end of the capacitor unit, and the first constant current source and the second constant current source are respectively connected with the external constant current supply circuit.
6. The jitter frequency adjustment circuit of claim 5, wherein the jitter frequency control module comprises:
the first adjusting unit is respectively connected with the first constant current source and the control module, and is configured to adjust the magnitude of current flowing through a first switch according to the comparison result;
the second adjusting unit is connected with the second constant current source and the control module respectively, and the second adjusting unit is configured to adjust the magnitude of the current flowing through the second switch according to the comparison result.
7. The jitter frequency adjustment circuit of claim 4, wherein the control module comprises:
the first comparison unit is connected with one end of the capacitor unit and configured to acquire a voltage at one end of the capacitor unit and compare the voltage with a preset voltage interval to generate a first comparison result;
the second comparison unit is connected with the sampling module and is configured to acquire the power signal and compare the power signal with a preset power value to generate a second comparison result.
8. The jitter frequency adjustment circuit of claim 7, wherein the oscillation module further comprises:
a switch control unit connected to the first comparison unit, the switch control unit being configured to generate a switch control signal for controlling the switch unit according to the comparison result, wherein a period of the switch control signal is the same as a period of the oscillation signal.
9. The jitter frequency adjustment circuit of any one of claims 2-8, wherein the jitter frequency control module comprises a digital-to-analog converter.
10. A jitter frequency regulation chip comprising the jitter frequency regulation circuit of any one of claims 1 to 9.
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|---|---|---|---|
| CN202121777712.6U CN215956362U (en) | 2021-07-30 | 2021-07-30 | Jitter frequency adjusting circuit and chip |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202121777712.6U CN215956362U (en) | 2021-07-30 | 2021-07-30 | Jitter frequency adjusting circuit and chip |
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| CN215956362U true CN215956362U (en) | 2022-03-04 |
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| CN (1) | CN215956362U (en) |
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