CN101013335A - Method and apparatus for synchronizing clock of distributed processing system - Google Patents
Method and apparatus for synchronizing clock of distributed processing system Download PDFInfo
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Abstract
It is a distributed processing system clock synchronization method, in which the programmable logic device of the control unit sends the counting clock and interrupt signal to the programmable logic device of the business processing unit, and according to the interrupt signal, the business processing unit resets the counter to its initial value, and in accordance with the said counting clock, achieves the cycle counting of the counter, thus achieving clock synchronization of the control unit and the business unit. The invention solves the precise clock synchronization problem, and the advantage is due to the clock to generate accurate time is the same clock source and therefore no time deviation, and no need frequently synchronization action, and meanwhile, as the synchronization using hardware signal line interruption, it can ignore the synchronized delay.
Description
Technical field
The present invention relates to distributed processing system(DPS), relate in particular to the clock synchronizing method and the device of distributed processing system(DPS).
Background technology
Distributed processing system(DPS) mainly is made up of two parts: be responsible for carrying out the main control unit of system's control and the Service Processing Unit that adopts the distributed work mode.Each unit has clock separately, the clock that early stage technology can only guarantee all unit second level be identical, can not accomplish more accurate unanimity, but, in some demand of realization, need main control unit and Service Processing Unit to finish jointly, in each cell processing, all can add the time tag of oneself, be necessary to guarantee therefore that all unit clocks are accurately consistent.
In view of this, prior art provides following technical scheme, is used to satisfy the more accurate consistent requirement of unit clock.
In the prior art, most distributed processing system(DPS)s have a RTC (RealTime Clock at main control unit, real-time clock) chip, what store on this RTC chip is the temporal information of date Hour Minute Second, and this RTC chip generally has battery, can accomplish the not drop-out that cuts off the power supply, operating personnel are in case well just can read time modification at any time the current time afterwards.
But Service Processing Unit does not have the RTC chip in system, and Service Processing Unit generally is to receive current level time second by an IPC who is connected with main control unit (Inter-Process Communication, interprocess communication) passage from main control unit.
Each unit in the system all needs to obtain current precise time, and this time is to use the external clock of CPU on each unit (Central Processing Unit, central processing unit) to count to get.
Level clock second that such scheme sends by main control unit can be accomplished between the unit consistent by methods such as compensation, but the precision clock that some business processing need be used can not be accomplished unanimity.This is because each Service Processing Unit is used for producing the precision difference of the CPU external clock crystal oscillator of precision clock, the crystal oscillator precision that common communications equipment CPU uses is ± 50ppm about.When two unit use the clock crystal oscillator of 5/1000000ths precision to produce precise time respectively, be no more than 1ms if guarantee the difference of precise time between two unit, then according to T=1ms/50ppm=20s, the time that promptly exceeds the permissible variation of 1ms is 20s, in other words, the time that assumes synchronization needs is far smaller than 1ms, and then system need carry out one subsynchronously every 20s, otherwise the precision of system will be lower than 1ms.And in actual applications, promptly carry out one subsynchronous too frequent every 20s, because if need synchronous processing unit too much in the distributed processing system(DPS), can cause then that software repeatedly carries out synchronous task in 20 seconds, thereby reduce management plane efficient, system resource is caused waste, crystal oscillator is a temperature sensor simultaneously, Temperature Influence also can be aggravated this phenomenon, so this phenomenon is the critical defect of prior art.
Therefore, desirable situation is, the time that exceeds deviation is that adjacent two time intervals between subsynchronous should be greater than one month.Simultaneously, send precise time by using the IPC passage, it is longer to delay time, the consistance of therefore same influence time.
In sum, there are two point defects in prior art: one, if use the crystal oscillator of common communications equipment CPU to come synchronous distributed processing system(DPS), then synchronous operation is too frequent, influences system effectiveness; Its two, if use the IPC passage to send precise time, then time-delay is longer, the consistance of influence time.
Summary of the invention
In view of above problem, the object of the present invention is to provide a kind of clock synchronizing method of distributed processing system(DPS), this method can need not frequently to carry out synchronous operation can make the clock of main control unit and Service Processing Unit reach precise synchronization, and effectively avoids channel time delay.
In order to realize goal of the invention of the present invention, the present invention discloses a kind of clock synchronizing method of distributed processing system(DPS), wherein, the programmable logic device (PLD) of main control unit sends counting clock and look-at-me to the programmable logic device (PLD) of Service Processing Unit, Service Processing Unit is realized the cycle count of counter with its counter reset to initial value and according to described counting clock according to this look-at-me, thereby reaches the clock synchronization of main control unit and business unit.
Clock synchronizing method as the described distributed processing system(DPS) of preferential specific embodiment of the present invention, wherein, when Service Processing Unit inserts, main control unit sends a look-at-me for when its counter overflows zero clearing next time the programmable logic device (PLD) of the Service Processing Unit of described insertion, and the programmable logic device (PLD) of this Service Processing Unit receives after this look-at-me its counter reset to initial value and begin to count.
Clock synchronizing method as the described distributed processing system(DPS) of preferential specific embodiment of the present invention, wherein, when Service Processing Unit inserts, its insertion of main control unit energy perception, its detailed process is: the programmable logic device (PLD) of main control unit as signal on the throne, is found the ground signalling line of Service Processing Unit this signal on the throne when main control unit and is judged that effectively then the Service Processing Unit insertion is arranged.
As the clock synchronizing method of the described distributed processing system(DPS) of preferential specific embodiment of the present invention, wherein, the programmable logic device (PLD) of described each unit to initial value and after beginning counting, is provided with synchronous complement mark with himself counter reset.
As the clock synchronizing method of the described distributed processing system(DPS) of preferential specific embodiment of the present invention, wherein, main control unit and each Service Processing Unit obtain current precise time by its CPU and local bus between the programmable logic device (PLD) separately respectively.
As the clock synchronizing method of the described distributed processing system(DPS) of preferential specific embodiment of the present invention, wherein, CPU reads before the precise time by the described synchronous complement mark of visit and whether determines synchronously complement mark.
As the clock synchronizing method of the described distributed processing system(DPS) of preferential specific embodiment of the present invention, wherein, described look-at-me is the effective hardware interrupt of level or edge.
In order to realize goal of the invention of the present invention, the present invention discloses a kind of clock synchronization apparatus of distributed processing system(DPS) in addition, wherein, comprise first programmable logic device (PLD) that is connected with the CPU of main control unit and second programmable logic device (PLD) that is connected with the CPU of Service Processing Unit, described first programmable logic device (PLD) links to each other with second programmable logic device, first programmable logic device (PLD) sends look-at-me and counting clock to second programmable logic device (PLD), and second programmable logic device (PLD) realizes the clock synchronization of Service Processing Unit and main control unit according to above-mentioned look-at-me and counting clock.
Clock synchronization apparatus as the described distributed processing system(DPS) of preferential specific embodiment of the present invention, wherein, described clock synchronization apparatus comprises detection module, when this detection module knows that Service Processing Unit inserts, report this information to give main control unit CPU, main control unit CPU notifies first programmable logic device (PLD) to send look-at-me for when counting zero clearing second programmable logic device (PLD) according to this information next time, makes second programmable logic device (PLD) carry out the counting synchronous with first programmable logic device (PLD).
Clock synchronization apparatus as the described distributed processing system(DPS) of preferential specific embodiment of the present invention, wherein, described Service Processing Unit comprises the set module, and when second programmable logic device (PLD) acquisition look-at-me entered count status, the set module put 1 or 0 with synchronous complement mark.
The invention solves the synchronous problem of precision clock, its advantage is, because producing the clock of precise time is same clock source, so deviation that can generation time, and need not frequently to carry out synchronization action, owing to adopt the mode of hardware signal line interruption synchronously, can allow synchronous time-delay ignore simultaneously.
Description of drawings
Fig. 1 is the process flow diagram of the clock synchronizing method of distributed processing system(DPS) of the present invention; And
Fig. 2 is the module map of the clock system of distributed processing system(DPS) of the present invention.
Embodiment
In specific embodiments of the invention, (ComplexProgrammable Logic Device CPLD) cooperates and realizes precision clock, but is that example is not represented the restriction to other programmable logic device (PLD) with CPLD to use CPLD.
Main control unit sends a clock and the effective hardware interrupt INT in level/edge that formulates frequency such as 10KHz for the programmable logic device (PLD) of Service Processing Unit by the programmable logic device (PLD) of main control unit, in the programmable logic device (PLD) of Service Processing Unit, realize a counter cycle count thus, the clock information of storage designated precision.
As shown in Figure 1, the concrete steps of this method are as follows:
S1. the programmable logic device (PLD) of main control unit sends counting clock and look-at-me to the programmable logic device (PLD) of Service Processing Unit, and the programmable logic device (PLD) of Service Processing Unit is utilized look-at-me that its meter applicator is reset to initial value and used the counting clock of the programmable logic device (PLD) transmission of main control unit to realize cycle count.
The clock source of the counter of the programmable logic device (PLD) of each unit is the clock that is sent by main control unit, and main control unit clock counter to all Service Processing Units when system initialization carries out synchronously.
Requirement to precision in this specific embodiment is 1ms, and selection can reach the clock of the 10K frequency of 0.1ms precision so.The programmable logic device (PLD) of main control unit has the reference clock input of himself, this reference clock is 100MHz at this specific embodiment medium frequency, this reference clock frequency division in the programmable logic device (PLD) of main control unit obtains the 10KHz clock, and the 10KHz clock that the programmable logic device (PLD) of main control unit obtains this frequency division by the pin that links to each other with programmable logic device (PLD) on each Service Processing Unit sends to the programmable logic device (PLD) on each Service Processing Unit.
The cycle counter of main control unit and Service Processing Unit all is to use its programmable logic device (PLD) separately to realize, and described cycle counter is all counted by the clock that its programmable logic device (PLD) sends the programmable logic device (PLD) of each Service Processing Unit to according to main control unit.
In this distributed processing system(DPS), the CPU of each unit obtains precision clock by reading programmable logic device (PLD), uses logical method to avoid overflowing to reading the influence of correctness when reading.
In this specific embodiment, the programmable logic device (PLD) logic realization of each unit be the cycle counter of one 16 bit, software reads 8 bits at every turn, read least-significant byte earlier and read most-significant byte then, the carry from the 8th to the 9th takes place when if software has read least-significant byte just, make a mistake in the time of then can causing reading most-significant byte, therefore be necessary to adopt logical method to avoid the type mistake.Avoid this type of wrong logical method to be: the programmable logic device (PLD) of main control unit with its most-significant byte locking storage, reads these data when software reads most-significant byte when its counter overflows zero clearing, so just can avoid data to overflow influence to correctness.
S2. the programmable logic device (PLD) of main control unit judges whether that new Service Processing Unit inserts.
This step S2 is a deterministic process, and in this process, main control unit detects the state of Service Processing Unit, if the new Service Processing Unit that has that detects in this distributed processing system(DPS) occurs inserting operation, then carries out the operation of next step S3; If each unit in this distributed processing system(DPS) is on the throne, then system keeps the state of the work lasting detection of the main control unit simultaneously Service Processing Unit of counter.
In this specific embodiment, Service Processing Unit has a signal wire on the throne, is low level when this signal line is effective, is high level during this invalidating signal.Main control unit plate and business processing unit board all are inserted on the backboard, and when Service Processing Unit inserted, the main control unit plate can be learnt the insertion operation of Service Processing Unit by the signal on the throne of this business processing unit board.For example the main control unit plate finds that aforementioned signal on the throne transfers low level to from high level, promptly from invalid to effectively, then main control unit just finds have business processing unit board to insert, so carry out next step S3; If signal on the throne keeps low level state, promptly effective status then need not carry out next step S3, but proceed detecting operation.
When S3. the counter of the programmable logic device (PLD) of main control unit overflows zero clearing next time, the programmable logic device (PLD) of main control unit sends a look-at-me for the programmable logic device (PLD) of the new Service Processing Unit that inserts, and the programmable logic device (PLD) of the Service Processing Unit of this new insertion receives after this look-at-me himself counter reset to initial value and restart to count.
Detecting Service Processing Unit take place to insert operation be signal on the throne from invalid after effectively, when overflowing zero clearing the first time after this insertion operation, the counter of the programmable logic device (PLD) of main control unit sends a look-at-me to Service Processing Unit, the programmable logic device (PLD) of notifying this Service Processing Unit with its counter reset to initial value, if initial value is zero, that just is equivalent to its counter O reset, restarts counting and synchronous complement mark is set.The value of counter that reaches the programmable logic device (PLD) of main control unit and Service Processing Unit thus is on all four result.
In other words, the programmable logic device (PLD) of main control unit sends a look-at-me counter of the programmable logic device (PLD) of Service Processing Unit also is reset to initial value when himself counter is returned to initial value.Meanwhile, the programmable logic device (PLD) of Service Processing Unit is provided with a synchronous complement mark and represents to finish synchronizing process.In this specific embodiment, the synchronous complement mark of the programmable logic device (PLD) of Service Processing Unit is set to 1 and represents to finish synchronizing process.
As shown in Figure 1, through above-mentioned three steps, this distributed processing system(DPS) is finished a clock synchronization operation, and this clock synchronization operates under the situation that operation appears inserting in system carries out this clock synchronization operation, has therefore significantly reduced the number of times of synchronous operation.Because main control unit and processing unit all are to use same clock to count, deviation when therefore not needing to consider to use the different clocks counting need not be synchronous repeatedly, and only need carry out a synchronous operation, in this specific embodiment, the time-delay of method for synchronous is in the 1ns rank.
Main control unit and each Service Processing Unit obtain current precise time by its CPU and local bus between the programmable logic device (PLD) (Local Bus) separately respectively, CPU needs to determine earlier whether synchronizing process is finished before reading precise time, this operation realizes by the described synchronous complement mark of accessing step S3, is in this specific embodiment and determines whether synchronous complement mark is set to 1.
The present invention also provides a kind of clock synchronization apparatus of distributed processing system(DPS).With embodiment illustrated in fig. 2 this device is described in detail below.The clock synchronization apparatus that Fig. 2 has disclosed a kind of distributed system comprises programmable logic device (CPLD) 1 that is connected with the CPU of main control unit and the programmable logic device (CPLD) 2 that is connected with the CPU of Service Processing Unit, CPLD1 links to each other with CPLD2, wherein, programmable logic device (CPLD) 1 sends look-at-me and counting clock to programmable logic device (CPLD) 2, and CPLD2 realizes the clock synchronization of Service Processing Unit and main control unit according to above-mentioned look-at-me and counting clock.
The clock source of the counter of programmable logic device (CPLD) 1 and CPLD2 is the clock that is sent by main control unit, and main control unit clock counter to all Service Processing Units when system initialization carries out synchronously.
Requirement to precision in this specific embodiment is 1ms, and selection can reach the clock of the 10K frequency of 0.1ms precision so.The programmable logic device (CPLD) 1 of main control unit has the reference clock input of himself, this reference clock is 100MHz at this specific embodiment medium frequency, this reference clock frequency division in the programmable logic device (CPLD) 1 of main control unit obtains the 10KHz clock, and the 10KHz clock that the programmable logic device (CPLD) 1 of main control unit obtains this frequency division by the pin that links to each other with programmable logic device (PLD) on each Service Processing Unit that comprises programmable logic device (CPLD) 2 sends to the programmable logic device (PLD) on each Service Processing Unit.
The cycle counter of main control unit and Service Processing Unit all is to use its programmable logic device (PLD) separately to realize, and described cycle counter is all counted by the clock that its programmable logic device (CPLD) 1 sends the programmable logic device (PLD) of each Service Processing Unit that comprises programmable logic device (CPLD) 2 to according to main control unit.
In this distributed processing system(DPS), the CPU of each unit obtains precision clock by reading programmable logic device (PLD), uses logical method to avoid overflowing to reading the influence of correctness when reading.
In this specific embodiment, the programmable logic device (PLD) logic realization of each unit be the cycle counter of one 16 bit, software reads 8 bits at every turn, read least-significant byte earlier and read most-significant byte then, the carry from the 8th to the 9th takes place when if software has read least-significant byte just, make a mistake in the time of then can causing reading most-significant byte, therefore be necessary to adopt logical method to avoid the type mistake.Avoid this type of wrong logical method to be: the programmable logic device (PLD) of main control unit with its most-significant byte locking storage, reads these data when software reads most-significant byte when its counter overflows zero clearing, so just can avoid data to overflow influence to correctness.
The clock synchronization apparatus of distributed processing system(DPS) as shown in Figure 2 also comprises detection module DETECTOR, when this detection module DETECTOR knows that Service Processing Unit inserts, report this information to give main control unit CPU, main control unit CPU sends look-at-mes for when counting zero clearing programmable logic device (CPLD) 2 according to this information notice programmable logic device (CPLD) 1 next time, makes programmable logic device (CPLD) 2 carry out the counting synchronous with programmable logic device (CPLD) 1.
In this specific embodiment, Service Processing Unit has a signal wire on the throne, is low level when this signal line is effective, is high level during this invalidating signal.Main control unit plate and business processing unit board all are inserted on the backboard, and when Service Processing Unit inserted, the detection module DETECTOR that is connected with main control unit can learn the insertion operation of Service Processing Unit by the signal on the throne of this business processing unit board.For example, the detection module DETECTOR of main control unit finds that aforementioned signal on the throne transfers low level to from high level, promptly from invalid to effectively, then the detection module DETECTOR of main control unit finds to have business processing unit board to insert, so with this information notification main control unit CPU; If the detection module DETECTOR of main control unit finds signal on the throne and keeps low level state that promptly effective status is then proceeded to detect.
As mentioned above, detect Service Processing Unit take place to insert operation be signal on the throne from invalid after effectively at the detection module DETECTOR of main control unit, when overflowing zero clearing the first time after this insertion operation, the counter of the programmable logic device (CPLD) 1 of main control unit sends a look-at-me to Service Processing Unit, the programmable logic device (CPLD) 2 of notifying this Service Processing Unit with its counter reset to initial value, if initial value is zero, that just is equivalent to its counter O reset, restarts counting.The value of counter that reaches the programmable logic device (CPLD) 2 of main control unit programmable logic device (CPLD) 1 and Service Processing Unit thus is on all four result.
As shown in Figure 2, Service Processing Unit comprises set module SET, and when programmable logic device (CPLD) 2 acquisition look-at-mes entered count status, the set module put 1 or 0 with synchronous complement mark.
The programmable logic device (CPLD) 1 of main control unit sends a look-at-me counter of the programmable logic device (CPLD) 2 of Service Processing Unit also is reset to initial value when himself counter is returned to initial value, meanwhile, the programmable logic device (CPLD) 2 of Service Processing Unit is provided with a synchronous complement mark with set module SET and represents to finish synchronizing process.In this specific embodiment, the programmable logic device (CPLD) 2 set module SET of Service Processing Unit are set to 1 and represent to finish synchronizing process, and the programmable logic device (CPLD) 2 set module SET of Service Processing Unit are set to 0 and represent not finish as yet synchronizing process.
Main control unit and each Service Processing Unit obtain current precise time by its CPU and local bus between the programmable logic device (PLD) (Local Bus) separately respectively, CPU needs to determine earlier whether synchronizing process is finished before reading precise time, this operation is to realize by visiting above-mentioned synchronous complement mark, is to determine whether synchronous complement mark is set to 1 in this specific embodiment.
What need statement is that foregoing invention content and embodiment are intended to prove the practical application of technical scheme provided by the present invention, should not be construed as the qualification to protection domain of the present invention.Those skilled in the art are in spirit of the present invention and principle, when doing various modifications, being equal to and replacing or improve.Protection scope of the present invention is as the criterion with appended claims.
Claims (10)
1, a kind of clock synchronizing method of distributed processing system(DPS), it is characterized in that, the programmable logic device (PLD) of main control unit sends counting clock and look-at-me to the programmable logic device (PLD) of Service Processing Unit, Service Processing Unit is realized the cycle count of counter with its counter reset to initial value and according to described counting clock according to this look-at-me, thereby reaches the clock synchronization of main control unit and business unit.
2, the clock synchronizing method of distributed processing system(DPS) as claimed in claim 1, it is characterized in that, when Service Processing Unit inserts, main control unit sends a look-at-me for when its counter overflows zero clearing next time the programmable logic device (PLD) of the Service Processing Unit of described insertion, and the programmable logic device (PLD) of this Service Processing Unit receives after this look-at-me its counter reset to initial value and begin to count.
3, the clock synchronizing method of distributed processing system(DPS) as claimed in claim 2, it is characterized in that, when Service Processing Unit inserts, its insertion of main control unit energy perception, its detailed process is: the programmable logic device (PLD) of main control unit as signal on the throne, is found the ground signalling line of Service Processing Unit this signal on the throne when main control unit and is judged that effectively then the Service Processing Unit insertion is arranged.
4, the clock synchronizing method of distributed processing system(DPS) as claimed in claim 2 is characterized in that, the programmable logic device (PLD) of described each unit to initial value and after beginning counting, is provided with synchronous complement mark with himself counter reset.
5, as the clock synchronizing method of the arbitrary described distributed processing system(DPS) of claim 1 to 4, it is characterized in that main control unit and each Service Processing Unit obtain current precise time by its CPU and local bus between the programmable logic device (PLD) separately respectively.
6, the clock synchronizing method of distributed processing system(DPS) as claimed in claim 5 is characterized in that, CPU reads before the precise time by the described synchronous complement mark of visit and whether determines synchronously complement mark.
7, the clock synchronizing method of distributed processing system(DPS) as claimed in claim 1 is characterized in that, described look-at-me is the effective hardware interrupt of level or edge.
8, a kind of clock synchronization apparatus of distributed processing system(DPS), it is characterized in that, comprise first programmable logic device (PLD) that is connected with the CPU of main control unit and second programmable logic device (PLD) that is connected with the CPU of Service Processing Unit, described first programmable logic device (PLD) links to each other with second programmable logic device, first programmable logic device (PLD) sends look-at-me and counting clock to second programmable logic device (PLD), and second programmable logic device (PLD) realizes the clock synchronization of Service Processing Unit and main control unit according to above-mentioned look-at-me and counting clock.
9, the clock synchronization apparatus of distributed processing system(DPS) as claimed in claim 8, it is characterized in that, described clock synchronization apparatus comprises detection module, when this detection module knows that Service Processing Unit inserts, report this information to give main control unit CPU, main control unit CPU notifies first programmable logic device (PLD) to send look-at-me for when counting zero clearing second programmable logic device (PLD) according to this information next time, makes second programmable logic device (PLD) carry out the counting synchronous with first programmable logic device (PLD).
10, the clock synchronization apparatus of distributed processing system(DPS) as claimed in claim 8 or 9, it is characterized in that, described Service Processing Unit comprises the set module, and when second programmable logic device (PLD) acquisition look-at-me entered count status, the set module put 1 or 0 with synchronous complement mark.
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101982959A (en) * | 2010-11-24 | 2011-03-02 | 电子科技大学 | Network demand time synchronization method |
| CN104866008A (en) * | 2015-05-13 | 2015-08-26 | 中国电子科技集团公司第四十一研究所 | Clock system |
| WO2015180150A1 (en) * | 2014-05-30 | 2015-12-03 | 深圳市英威腾电气股份有限公司 | Method for multi-machine frequency converter generating synchronization signal, and multi-machine frequency converter |
| CN105425662A (en) * | 2015-11-06 | 2016-03-23 | 北京广利核系统工程有限公司 | Main processor in DCS (distributed control system) based on FPGA, and control method of main processor |
| CN107809168A (en) * | 2016-09-09 | 2018-03-16 | 中核兰州铀浓缩有限公司 | A kind of gas centrifuge intermediate frequency power supply sychronisation |
| CN111211855A (en) * | 2020-01-03 | 2020-05-29 | 中国船舶重工集团公司第七0七研究所 | Mixed clock synchronization method for distributed processing system |
| CN111600670A (en) * | 2019-02-20 | 2020-08-28 | 阿里巴巴集团控股有限公司 | Inductive data calculation control method and time service device |
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2007
- 2007-02-15 CN CN200710005170A patent/CN100595716C/en active Active
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101982959A (en) * | 2010-11-24 | 2011-03-02 | 电子科技大学 | Network demand time synchronization method |
| CN101982959B (en) * | 2010-11-24 | 2013-02-13 | 电子科技大学 | Network demand time synchronization method |
| WO2015180150A1 (en) * | 2014-05-30 | 2015-12-03 | 深圳市英威腾电气股份有限公司 | Method for multi-machine frequency converter generating synchronization signal, and multi-machine frequency converter |
| CN105612465A (en) * | 2014-05-30 | 2016-05-25 | 深圳市英威腾电气股份有限公司 | Method for multi-machine frequency converter generating synchronization signal, and multi-machine frequency converter |
| CN104866008A (en) * | 2015-05-13 | 2015-08-26 | 中国电子科技集团公司第四十一研究所 | Clock system |
| CN104866008B (en) * | 2015-05-13 | 2017-10-03 | 中国电子科技集团公司第四十一研究所 | A kind of clock system |
| CN105425662A (en) * | 2015-11-06 | 2016-03-23 | 北京广利核系统工程有限公司 | Main processor in DCS (distributed control system) based on FPGA, and control method of main processor |
| CN105425662B (en) * | 2015-11-06 | 2019-04-09 | 北京广利核系统工程有限公司 | Primary processor and its control method in Distributed Control System based on FPGA |
| CN107809168A (en) * | 2016-09-09 | 2018-03-16 | 中核兰州铀浓缩有限公司 | A kind of gas centrifuge intermediate frequency power supply sychronisation |
| CN111600670A (en) * | 2019-02-20 | 2020-08-28 | 阿里巴巴集团控股有限公司 | Inductive data calculation control method and time service device |
| CN111211855A (en) * | 2020-01-03 | 2020-05-29 | 中国船舶重工集团公司第七0七研究所 | Mixed clock synchronization method for distributed processing system |
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| CN100595716C (en) | 2010-03-24 |
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