CN116032411A - Time stamp synchronization method, system, terminal and storage medium - Google Patents
Time stamp synchronization method, system, terminal and storage medium Download PDFInfo
- Publication number
- CN116032411A CN116032411A CN202310265986.4A CN202310265986A CN116032411A CN 116032411 A CN116032411 A CN 116032411A CN 202310265986 A CN202310265986 A CN 202310265986A CN 116032411 A CN116032411 A CN 116032411A
- Authority
- CN
- China
- Prior art keywords
- time
- time difference
- historical
- current
- difference value
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Electric Clocks (AREA)
Abstract
The application provides a timestamp synchronization method, a timestamp synchronization system, a terminal and a storage medium, and relates to the technical field of communication, wherein the method comprises the following steps: acquiring NTP time information and local time keeping time information of a current period; calculating the time difference between the NTP time information and the local time keeping time information to obtain a first time difference value of the current period; acquiring n historical time differences of n continuous historical periods, wherein n continuous historical periods comprise a previous period of a current period; comparing the first time difference value with n historical time difference values, and confirming a stepping fine adjustment parameter according to a comparison result, wherein the stepping fine adjustment parameter comprises a positive fine adjustment action parameter and a negative fine adjustment action parameter; and according to the stepping fine tuning parameters, adjusting the local time keeping accumulation logic and outputting the current time stamp information. The method and the device can improve the accuracy of time stamp synchronization and avoid time stamp rollback.
Description
Technical Field
The present disclosure relates to the field of communications technologies, and in particular, to a method, a system, a terminal, and a storage medium for synchronizing a timestamp.
Background
The PCIE (Peripheral Component Interconnect Express, high-speed serial computer expansion bus standard) network card based on the FPGA (Field Programmable Gate Array) is adopted for traffic capture, which is usually a large-traffic scene, and a large data analysis manufacturer needs to obtain the time captured by each data message when analyzing the captured large-traffic, so that the analysis data can restore the whole communication flow of the current data flow according to the time sequence, and once the time stamp is inaccurate or the time stamp is wrong, the time rollback is caused, the current analysis flow can be influenced, so that the traffic restoration is abnormal, and some of the network cards even pay extra calculation resources for correcting the time error, so that the calculation burden of a CPU is increased, and the function of attaching the time stamp to the captured traffic on all lines by the network card is particularly important.
In the current mainstream time synchronization scheme, local time keeping after acquiring the time of the ethernet time server according to NTP (Network Time Protocol ) is not performed, and synchronization is not performed, which has the consequence that the absolute time error of local time keeping becomes larger and larger according to time accumulation. The other is to time the local time keeping after the Ethernet time is acquired according to the NTP (for example, once every 1 second or once every day), and because the NTP synchronous time issued by the CPU floats near the accurate time, the error can reach within +/-1 ms, and when the error is negative, the action of the time stamp callback is necessarily generated, so that the network card acquires the time stamp rollback.
Therefore, based on the NTP synchronization protocol, how to improve the accuracy of timestamp synchronization and avoid timestamp rollback at the same time is a technical problem to be solved by those skilled in the art.
Disclosure of Invention
In order to solve the technical problems, the application provides a timestamp synchronization method, which is based on an NTP synchronization protocol, can improve the accuracy of timestamp synchronization and simultaneously avoid timestamp rollback. The application also provides a timestamp synchronization system, a terminal and a storage medium, which have the same technical effects.
A first object of the present application is to provide a time stamp synchronization method.
The first object of the present application is achieved by the following technical solutions:
a timestamp synchronization method applied to a field programmable gate array FPGA high-speed serial computer expansion bus standard PCIE network card, the method comprising:
acquiring Network Time Protocol (NTP) time information and local time keeping time information of a current period;
calculating the time difference between the NTP time information and the local time keeping time information to obtain a first time difference value of the current period;
obtaining n historical time differences of n continuous historical periods, wherein each historical time difference is obtained by pre-calculating the time difference between NTP time information and local time keeping time information of the historical period corresponding to each historical time difference, the n continuous historical periods comprise the previous period of the current period, and n is a positive integer greater than 1;
comparing the first time difference value with n historical time difference values, and confirming a stepping fine adjustment parameter according to a comparison result, wherein the stepping fine adjustment parameter comprises a positive fine adjustment action parameter and a negative fine adjustment action parameter;
and according to the stepping fine tuning parameters, adjusting the local time keeping accumulation logic and outputting the current time stamp information.
Preferably, in the timestamp synchronization method, after calculating the time difference between the NTP time information and the local time keeping time information to obtain a first time difference value of the current period, the method further includes:
judging whether the first time difference value is larger than or equal to a preset threshold value,
if yes, covering the current local time keeping time information according to the NTP time information, and outputting the current time stamp information;
if not, executing the step of acquiring n historical time differences of n continuous historical periods.
Preferably, in the timestamp synchronization method, the comparing the first time difference value with n historical time difference values, and determining a step trimming parameter according to a comparison result includes:
comparing the first time difference value and n historical time difference values,
when the first time difference value and the n historical time difference values are positive or negative, arranging the first time difference value and the n historical time difference values according to a periodic sequence to obtain a first sequence, wherein the first time difference value is positioned at the last position of the first sequence;
calculating a first-order difference of the first sequence to obtain a second sequence;
taking absolute values of the numerical values in the second sequence to obtain a third sequence;
calculating the first-order difference of the third sequence to obtain a fourth sequence;
judging whether the values in the fourth sequence are all greater than or equal to 0,
if yes, outputting positive fine tuning action parameters when the first time difference value and the n historical time difference values are positive, or outputting negative fine tuning action parameters when the first time difference value and the n historical time difference values are negative;
if not, maintaining the current step fine tuning parameters;
when the first time difference value is positive and the historical time difference value corresponding to the previous period of the current period is negative, the current stepping fine adjustment parameter is maintained;
and when the first time difference value is negative and the historical time difference value corresponding to the previous period of the current period is positive, maintaining the current stepping fine adjustment parameter.
Preferably, in the timestamp synchronization method, the adjusting the local time keeping accumulation logic according to the step trimming parameter, and outputting current timestamp information includes:
and modifying the offset parameter of the time keeping timer according to the stepping fine tuning parameter, and outputting the current time stamp information.
Preferably, in the timestamp synchronization method, the time-keeping timer is composed of an integer part and a decimal floating point part, and the modifying the offset parameter of the time-keeping timer according to the step trimming parameter includes:
accumulating the step fine tuning parameter in the fraction floating point portion of the watch dog timer.
Preferably, in the timestamp synchronization method, the time keeping timer is a 96-bit counter.
Preferably, in the timestamp synchronization method, the step trimming parameter adopts 0.1PPM of the current crystal oscillator as a trimming step length, wherein PPM represents parts per million.
A second object of the present application is to provide a time stamp synchronizing system.
The second object of the present application is achieved by the following technical solutions:
a timestamp synchronization system for a field programmable gate array FPGA high-speed serial computer expansion bus standard PCIE network card, the system comprising:
the first acquisition module is used for acquiring Network Time Protocol (NTP) time information and local time keeping time information of the current period;
the difference value calculation module is used for calculating the time difference between the NTP time information and the local time keeping time information to obtain a first time difference value of the current period;
the second acquisition module is used for acquiring n historical time differences of n continuous historical periods, wherein each historical time difference is obtained by pre-calculating the time difference between the NTP time information and the local time keeping time information of the historical period corresponding to each historical time difference, the n continuous historical periods comprise the previous period of the current period, and n is a positive integer greater than 1;
the step fine adjustment module is used for comparing the first time difference value with n historical time difference values and confirming step fine adjustment parameters according to comparison results, wherein the step fine adjustment parameters comprise positive fine adjustment action parameters and negative fine adjustment action parameters;
and the local timekeeping module is used for adjusting the local timekeeping accumulation logic according to the stepping fine adjustment parameter and outputting the current timestamp information.
A third object of the present application is to provide a time stamp synchronizing terminal.
The third object of the present application is achieved by the following technical solutions:
a timestamp synchronization terminal, comprising: a storage medium and a processor;
computer-executable instructions are stored in the storage medium;
the processor executes computer-executable instructions stored on the storage medium to implement any of the methods described above for timestamp synchronization.
A fourth object of the present application is to provide a computer-readable storage medium.
The fourth object of the present application is achieved by the following technical solutions:
a computer readable storage medium having stored therein computer executable instructions for implementing any one of the above-described timestamp synchronization methods when executed by a processor.
According to the technical scheme, the FPGA PCIE network card platform is adopted as a basis, all functions are realized in programmable logic, periodic NTP time information is adopted for issuing synchronization, and NTP time information and local time keeping time information of the current period are obtained; calculating the time difference between the NTP time information and the local time keeping time information to obtain a first time difference value of the current period; obtaining n historical time differences of n continuous historical periods, wherein each historical time difference is obtained by pre-calculating the time difference between NTP time information and local time keeping time information of the historical period corresponding to each historical time difference, the n continuous historical periods comprise the previous period of the current period, and n is a positive integer greater than 1; comparing the first time difference value with n historical time difference values, and confirming a stepping fine adjustment parameter according to a comparison result; and according to the stepping fine tuning parameters, adjusting the local time keeping accumulation logic and outputting the current time stamp information. The technical scheme adopts a mode of comparing multiple time difference values to generate a stepping fine adjustment action, can be necessarily converged to an adjustment value under the fine adjustment of multiple periodical time synchronization actions, cannot be influenced by the temperature change of the crystal oscillator, and achieves the purpose of stabilizing and accurately keeping time. The step fine tuning parameters comprise positive fine tuning action parameters and negative fine tuning action parameters, and the current fine tuning judgment adopts a local time-keeping accumulation logic progressive mode, so that only the adjustment of time-keeping acceleration and deceleration is performed, and the problem of time stamp rollback coverage does not occur. In addition, the technical scheme is low in deployment cost, good in portability, free of additional hardware support and suitable for scenes requiring accurate relative time information.
In summary, according to the above technical solution, based on the NTP synchronization protocol, the accuracy of time stamp synchronization can be improved, and the occurrence of time stamp rollback is avoided.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments described in the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a PCIE network card working data flow diagram based on FPGA;
fig. 2 is a flowchart of a timestamp synchronization method in an embodiment of the present application;
FIG. 3 is a schematic diagram of one case of time difference comparison;
FIG. 4 is a schematic diagram of another case of time difference comparison;
FIG. 5 is another flow chart of a method for synchronizing time stamps according to an embodiment of the present application;
FIG. 6 is a diagram showing a parameter trimming process of a 96-bit time-keeping counter;
fig. 7 is a schematic structural diagram of a timestamp synchronization system according to an embodiment of the present application;
fig. 8 is a schematic structural diagram of a timestamp synchronization terminal in an embodiment of the present application.
Detailed Description
In order to better understand the technical solutions in the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below, and it is obvious that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
In the embodiments provided in the present application, it should be understood that the disclosed method and system may be implemented in other manners. The system embodiments described below are merely illustrative, and for example, the division of modules is merely a logical function division, and other divisions may be implemented in practice, such as: multiple modules or components may be combined, or may be integrated into another system, or some features may be omitted, or not performed. In addition, the various components shown or discussed may be coupled or directly coupled or communicatively coupled to each other via some interface, whether indirectly coupled or communicatively coupled to devices or modules, whether electrically, mechanically, or otherwise.
It should be appreciated that the terms "system," "apparatus," "unit," and/or "module," if used herein, are merely one method for distinguishing between different components, elements, parts, portions, or assemblies at different levels. However, if other words can achieve the same purpose, the word can be replaced by other expressions.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present application, the meaning of "a plurality" or "a number" is two or more, unless explicitly defined otherwise.
If a flowchart is used in the present application, the flowchart is used to describe the operations performed by the system according to embodiments of the present application. It should be appreciated that the preceding or following operations are not necessarily performed in order precisely. Rather, the steps may be processed in reverse order or simultaneously. Also, other operations may be added to or removed from these processes.
It should also be noted that, in this document, terms such as "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such article or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in an article or apparatus that comprises such element.
The embodiment of the application is written in a progressive manner.
The timestamp synchronization method provided by the embodiment of the application is mainly applied to the FPGA PCIE network card; the English of FPGA is named Field Programmable Gate Array and the Chinese name is field programmable gate array. The internal functional logic is developed by adopting a hardware description language of Verilog or VHDL, and the logic can be arbitrarily customized according to the requirements of a developer. With the explosive growth of network bandwidth, the network interface of the PCIE network card of the host gradually evolves from the first ten megabytes to hundred megabytes and gigabytes, and with the higher and higher demand of big data analysis on network traffic grabbing, the existing network interface needs to be accessed by 40G and 100G. The FPGA chip is provided with a high-speed serial interface and a built-in interface hard core IP, so that the data access of the Ethernet flow of 10G/40G/100G can be easily realized, and is provided with a high-speed PCIE interface, and therefore, at present, PCIE network card designs based on the FPGA are adopted by many factories and merchants. PCIE network card work data flow diagram based on FPGA is shown in figure 1. The method is limited by the current hardware condition, no matter what network card is made by a platform, the difference between the time stamp precision of the data and the absolute time is not within 1ns, the difference between the local time and the absolute time is not required to be extremely small in most of time of the time stamp required by a big data analysis manufacturer, and more, the time difference between the time stamps of the whole grabbed data stream is required to be precise.
As shown in fig. 2, an embodiment of the present application provides a timestamp synchronization method, where the method is applied to an FPGA PCIE network card, and the method includes:
s101, acquiring NTP time information and local time keeping time information of a current period;
in S101, NTP refers to network time protocol, english name: network Time Protocol, which is a protocol for time synchronizing a computer, can synchronize the computer to its server or clock source (e.g., quartz clock, GPS, etc.), can provide highly accurate time correction, and can prevent a malicious protocol attack by means of encryption validation. The purpose of NTP is to provide accurate and robust time services in an unordered Internet environment. NTP provides an accurate time, first of all, an accurate time source, which should be international standard time UTC (Universal Time Coordinated). The time source of UTC obtained by NTP can be atomic clock, astronomical station, satellite, or obtained from Internet. Specifically, the PCIE interface performs synchronization through time information obtained by periodically issuing (for example, 1 second for 1 time) NTPs, so that NTP time information of a current period may be obtained from the PCIE interface; in order to obtain a time keeping result, the FPGA needs to accumulate time values by means of a timer, specifically, the local time keeping time information of the current period can be obtained through the time keeping timer.
S102, calculating the time difference between the NTP time information and the local time keeping time information to obtain a first time difference value of the current period;
in S102, specifically, a time difference obtained by subtracting a time value in the local time keeping time information of the current period from a time value in the NTP time information of the current period is used as the first time difference value.
S103, obtaining n historical time differences of n continuous historical periods, wherein each historical time difference is obtained by pre-calculating the time difference between NTP time information and local time keeping time information of the historical period corresponding to each historical time difference, the n continuous historical periods comprise the previous period of the current period, and n is a positive integer greater than 1;
in S103, the historical time difference may be calculated in advance with reference to specific implementation details of S101 and S102; for example, it can be achieved by the following steps: acquiring NTP time information and local time keeping time information of a current history period; and calculating the time difference between the NTP time information and the local time keeping time information of the current historical period to obtain the historical time difference value of the current historical period. The value of n can be confirmed according to the precision and efficiency requirement of the time stamp synchronization, for example, n can be 2 in consideration of the balance of the efficiency and precision of the time stamp synchronization.
S104, comparing the first time difference value with n historical time difference values, and confirming a stepping fine adjustment parameter according to a comparison result, wherein the stepping fine adjustment parameter comprises a positive fine adjustment action parameter and a negative fine adjustment action parameter;
in S104, step fine tuning parameters may be determined according to the comparison result of the comparison between the first time difference value and the n historical time difference values, specifically, if it is determined that the difference between the local time keeping and the standard time is expanding according to the comparison result, the frequency of the current crystal oscillator running is slower, and then the forward fine tuning action parameters are output; if the difference between the local time keeping and the standard time is enlarged according to the comparison result, the current crystal oscillator operates at a higher frequency, and negative fine tuning action parameters are output. From the step fine tuning parameters, ppm (Parts Per Million ) compensation may be performed; for example, if the standard frequency of the current crystal oscillator is 100MHz, the current crystal oscillator is 100.00001MHz if the current crystal oscillator has an error of +0.1ppm, and the step trimming parameter is set to eliminate the error of 0.00001 MHz.
S105, according to the stepping fine tuning parameters, adjusting the local time keeping accumulation logic, and outputting current time stamp information.
In S105, to obtain a time keeping result, the FPGA needs to accumulate time values by means of a timer, and the internal local time keeping accumulation logic of the FPGA is operated under the driving of the system clock. For example, the working clock of the current time keeping logic is 100M, and then the time keeping logic accumulates 10ns for each working clock, and if the working clock of the current time keeping logic is 200M, the time keeping logic accumulates 5ns for each working clock. The reason that the FPGA is higher in timekeeping precision than the PC software is that all logic of the FPGA is processed in parallel under the drive of a clock, the work of each logic function is not influenced by other functions, the precision can reach ns level only under the influence of clock precision, the PC software is timekeeping for reasons such as instruction execution arbitration and pipeline of a CPU, and the timekeeping precision can only reach millisecond level. The step fine tuning parameters comprise positive fine tuning action parameters and negative fine tuning action parameters, and the current fine tuning judgment adopts a local time-keeping accumulation logic progressive mode, so that only the adjustment of time-keeping acceleration and deceleration is performed, the problem of time stamp rollback coverage cannot occur, and the time stamp information can be used for the data stamping logic. One implementation of this step includes: and modifying the offset parameter of the time keeping timer according to the stepping fine tuning parameter, and outputting the current time stamp information.
In the current mainstream time synchronization scheme, local time keeping is performed after the ethernet time server is acquired according to NTP, and synchronization is not performed, so that an absolute time error of local time keeping becomes larger and larger according to time accumulation. The other is to time the local time keeping after the Ethernet time is acquired according to the NTP (for example, once every 1 second or once every day), and because the NTP synchronous time issued by the CPU floats near the accurate time, the error can reach within +/-1 ms, and when the error is negative, the action of the time stamp callback is necessarily generated, so that the network card acquires the time stamp rollback.
In the above embodiment, the FPGA PCIE network card platform is adopted as a base, all functions are implemented in the programmable logic, and the periodic NTP time information is adopted to issue synchronization, so that the NTP time information and the local time keeping time information of the current period are obtained; calculating the time difference between the NTP time information and the local time keeping time information to obtain a first time difference value of the current period; obtaining n historical time differences of n continuous historical periods, wherein each historical time difference is obtained by pre-calculating the time difference between NTP time information and local time keeping time information of the historical period corresponding to each historical time difference, the n continuous historical periods comprise the previous period of the current period, and n is a positive integer greater than 1; comparing the first time difference value with n historical time difference values, and confirming a stepping fine adjustment parameter according to a comparison result; and according to the stepping fine tuning parameters, adjusting the local time keeping accumulation logic and outputting the current time stamp information. The above embodiment adopts a mode of comparing multiple time difference values to generate a stepping fine adjustment action, and can be necessarily converged to an adjustment value under the fine adjustment of multiple periodical time synchronization actions, so that the purpose of stable and accurate time keeping is achieved without being influenced by the temperature change of the crystal oscillator. The step fine tuning parameters comprise positive fine tuning action parameters and negative fine tuning action parameters, and the current fine tuning judgment adopts a local time-keeping accumulation logic progressive mode, so that only the adjustment of time-keeping acceleration and deceleration is performed, and the problem of time stamp rollback coverage does not occur. In addition, the embodiment has low deployment cost and good portability, does not need additional hardware support, and is suitable for scenes needing accurate relative time information. In summary, according to the above embodiments, based on the NTP synchronization protocol, the accuracy of timestamp synchronization can be improved, and timestamp rollback is avoided.
In other embodiments of the present application, one implementation manner of the step of comparing the first time difference value with n historical time difference values and determining the step of trimming parameters according to the comparison result is specifically:
comparing the first time difference value and n historical time difference values,
when the first time difference value and the n historical time difference values are positive or negative, arranging the first time difference value and the n historical time difference values according to a periodic sequence to obtain a first sequence, wherein the first time difference value is positioned at the last position of the first sequence;
calculating a first-order difference of the first sequence to obtain a second sequence;
taking absolute values of the numerical values in the second sequence to obtain a third sequence;
calculating the first-order difference of the third sequence to obtain a fourth sequence;
judging whether the values in the fourth sequence are all greater than or equal to 0,
if yes, outputting positive fine tuning action parameters when the first time difference value and the n historical time difference values are positive, or outputting negative fine tuning action parameters when the first time difference value and the n historical time difference values are negative;
if not, maintaining the current step fine tuning parameters;
when the first time difference value is positive and the historical time difference value corresponding to the previous period of the current period is negative, the current stepping fine adjustment parameter is maintained;
and when the first time difference value is negative and the historical time difference value corresponding to the previous period of the current period is positive, maintaining the current stepping fine adjustment parameter.
Specifically, taking n as 2 as an example, recording the previous cycle of the current cycle as a first history cycle, the previous cycle of the first history cycle as a second history cycle, recording the first time difference of the current cycle as DeltaT 3, the history time difference of the first history cycle as DeltaT 2, the history time difference of the second history cycle as DeltaT 1,
comparing deltat 1, deltat 2 and deltat 3,
if the delta T1, the delta T2 and the delta T3 are all positive, and the |delta T3-delta T2| is not less than the |delta T2-delta T1|, outputting a forward fine adjustment action parameter; specifically, as shown in fig. 3, the first time difference value of the current period corresponds to Δt3 in fig. 3, the history time difference value of the first history period corresponds to Δt2 in fig. 3, the history time difference value of the second history period corresponds to Δt1, Δt3, Δt2 and Δt1 in fig. 3 are all positive, and |Δt3- Δt2|is not less than |Δt2- Δt1|, as can be seen from the figure, the difference between the local time conservation and the standard time is enlarged, the frequency of the current crystal oscillator operation is slower, ppm compensation is needed, and the forward fine tuning action parameter is output;
if the delta T1, the delta T2 and the delta T3 are all positive, and the absolute delta T3-delta T2 absolute value is less than the absolute delta T2-delta T1 absolute value, the current stepping fine adjustment parameter is maintained; the difference between the local time keeping and the standard time is reduced under the current situation, which means that the current time keeping time is converging to the standard time, and the current stepping fine tuning parameters are kept;
if DeltaT 3 is positive and DeltaT 2 is negative, maintaining the current step fine tuning parameter; the difference between the local time keeping and the standard time under the current situation is converged, and the current stepping fine tuning parameters are kept;
if the delta T1, the delta T2 and the delta T3 are all negative, and the |delta T3-delta T2| is not less than the |delta T2-delta T1|, outputting a negative fine adjustment action parameter; specifically, as shown in fig. 4, the first time difference value of the current period corresponds to Δt3 in fig. 4, the history time difference value of the first history period corresponds to Δt2 in fig. 4, the history time difference value of the second history period corresponds to Δt1, Δt3, Δt2 and Δt1 in fig. 4 are all negative, and |Δt3- Δt2|is not less than |Δt2- Δt1|, as can be seen from the figure, the difference between the local time conservation and the standard time is enlarged, the frequency of the current crystal oscillator operation is faster, ppm compensation is required, and negative fine tuning action parameters are output;
if Δt1, Δt2, and Δt3 are all negative, and |Δt3- Δt2| < Δt2- Δt1|, maintaining the current step fine tuning parameters; the difference between the local time keeping and the standard time is reduced under the current situation, which means that the current time keeping time is converging to the standard time, and the current stepping fine tuning parameters are kept;
if delta T3 is negative and delta T2 is positive, maintaining the current step fine tuning parameter; under the current situation, the difference between the local time keeping and the standard time is converged, and the current stepping fine tuning parameters are kept.
According to the implementation step, whether the current step fine tuning parameters are increased or decreased is determined by comparing the time difference values of n+1 periods continuously, the condition that the running frequency of the current crystal oscillator is slower or faster can be accurately identified based on the difference between the local time keeping and the standard time, the corresponding step fine tuning parameters are output, meanwhile, large step adjustment fluctuation can be avoided, and the effect of stable convergence can be achieved under the fine tuning of multiple periodic time synchronization actions. Based on the implementation steps, the timestamp synchronization method can achieve good time keeping convergence and time keeping precision.
As can be seen from the foregoing, in the step of calculating and using the first time difference value to determine that the error is very critical in the timestamp synchronization method, in other embodiments of the present application, before comparing the first time difference value with the n historical time difference values, the first time difference value may be compared with a preset threshold value, as shown in fig. 5, in other embodiments of the present application, another timestamp synchronization method is further provided, where the method is applied to an FPGA PCIE network card, and the method includes:
s201, acquiring NTP time information and local time keeping time information of a current period;
s202, calculating the time difference between the NTP time information and the local time keeping time information to obtain a first time difference value of the current period;
for details of specific implementation of S201 and S202, reference may be made to S101 and S102 described above.
S203, judging whether the first time difference value is larger than or equal to a preset threshold value, if so, executing S204, and if not, executing S205;
in S203, the preset threshold may be determined according to the actual application requirement, for example, 1 second may be taken; correspondingly, if the time difference between the received time value in the NTP time information and the time value in the local time keeping time information is greater than or equal to 1 second, executing S204; otherwise, S205 is performed.
S204, covering current local time keeping time information according to the NTP time information, and outputting current time stamp information;
in S204, when the first time difference value is greater than or equal to the preset threshold, the current local time keeping time information is covered according to the NTP time information of the current period, and the current time stamp information is output, and the scene generally occurs in the first synchronization.
S205, obtaining n historical time differences of n continuous historical periods, wherein each historical time difference is obtained by pre-calculating the time difference between NTP time information and local time keeping time information of the historical period corresponding to each historical time difference, the n continuous historical periods comprise the previous period of the current period, and n is a positive integer greater than 1;
s206, comparing the first time difference value with n historical time difference values, and confirming a stepping fine adjustment parameter according to a comparison result, wherein the stepping fine adjustment parameter comprises a positive fine adjustment action parameter and a negative fine adjustment action parameter;
s207, according to the stepping fine tuning parameters, adjusting local time keeping accumulation logic and outputting current time stamp information.
For details of the specific implementation of S205 to S207, reference may be made to S103 to S105 described above.
In this embodiment, the first time difference value is compared with a preset threshold value, when the first time difference value is greater than or equal to the preset threshold value, the current local time keeping time information is covered according to the NTP time information of the current period, and the current time stamp information is output, and the scene generally occurs in the first synchronization; when the first difference value is smaller than the preset threshold value, the local timekeeping is continuously adjusted by comparing the first time difference value with n historical time difference values.
In order to improve the compensation precision, in other embodiments of the present application, the time keeping timer is composed of an integer part and a fractional floating point part, and one implementation manner of modifying the offset parameter of the time keeping timer according to the step fine tuning parameter includes: accumulating the step fine tuning parameter in the fraction floating point portion of the watch dog timer. And the carry of the integer is adjusted in a floating point decimal carry mode, so that the adjustment compensation precision is high.
Specifically, taking the time keeping timer as a 96-bit counter as an example, as shown in fig. 6, the high 64 bits are nanosecond integer values, and the low 32 bits are fraction of nanoseconds. Taking 156.25m as an example, the timing period is 6.4ns, then the high 64bit accumulates 6ns every clock period, and the low 32bit fraction portion needs to accumulate 0.4ns and is converted into 32bit floating point number to be 0x66666666, when the 32bit floating point number accumulates and overflows, then an extra accumulated 1 is output for the integer time of the high 64 bit.
In order to achieve fine tuning of the crystal oscillator, in other embodiments of the present application, the step fine tuning parameter uses 0.1PPM of the current crystal oscillator as a fine tuning step, that is, feq×2ζ2×0.1PPM. For example, a 156.25m crystal oscillator adopts a trim value of 2749 (decimal), the trim value is subjected to positive and negative trimming by adding or subtracting the lower 32bit fraction to or from each clock, and when 128 steps are required to be subjected to positive trimming, each clock adds up the fraction to 128 x 2749. The fine tuning step length of 0.1ppm represents that the time keeping precision can reach 1 kilomillion of the crystal oscillator frequency, and the time keeping error of each day is reduced from the original 4.32s to 0.1us. And the current fine tuning judgment adopts an accumulation progressive mode, only the adjustment of time keeping acceleration and deceleration is adopted, and the problem of time stamp rollback coverage can not occur. In addition, although the accuracy range of the NTP issue time is 1ms, after single-time synchronization fine adjustment, the time keeping counter will converge on the average median value of the NTP synchronization time, and the current time keeping logic will not change severely due to the excessive error time issued by the NTP at a time, and the fine adjustment value will perform fine adjustment convergence in real time according to the frequency offset caused by the working temperature of the current crystal oscillator. Thus, a stable convergent high precision time keeping logic with temperature compensation can be obtained.
Based on the setting of the timekeeping timer and the stepping fine tuning parameters, the high-precision timekeeping scheme of local crystal oscillator PPM fine tuning is realized, the error time information with the precision of 1ms can be obtained through an NTP network, the relative time information with the error lower than 0.1us can be obtained through a fine tuning synchronization mode, the occurrence of a timestamp callback can be prevented, the error caused by crystal oscillator temperature drift can be automatically adjusted, and the precision is further improved.
As shown in fig. 7, in another embodiment of the present application, there is further provided a timestamp synchronization system, where the system is applied to a field programmable gate array FPGA high-speed serial computer expansion bus standard PCIE network card, the system includes:
a first obtaining module 10, configured to obtain network time protocol NTP time information and local time keeping time information of a current period;
the difference calculating module 11 is configured to calculate a time difference between the NTP time information and the local time keeping time information, so as to obtain a first time difference value of the current period;
a second obtaining module 12, configured to obtain n historical time differences of n continuous historical periods, where each historical time difference is obtained by pre-calculating a time difference between NTP time information and local time keeping time information of a historical period corresponding to each historical time difference, and n continuous historical periods include a previous period of a current period, and n is a positive integer greater than 1;
a step fine adjustment module 13, configured to compare the first time difference value with n historical time difference values, and confirm step fine adjustment parameters according to a comparison result, where the step fine adjustment parameters include a positive fine adjustment action parameter and a negative fine adjustment action parameter;
the local time keeping module 14 is configured to adjust the local time keeping accumulation logic according to the step fine adjustment parameter, and output current timestamp information.
As shown in fig. 8, in another embodiment of the present application, there is also provided a timestamp synchronization terminal, including: a storage medium 20 and a processor 21;
computer-executable instructions are stored within the storage medium 20;
the processor 21 executes computer-executable instructions stored on the storage medium 20 to implement any of the methods described above for timestamp synchronization.
Wherein the processor 21 may comprise one or more processing cores. The processor 21 performs various functions of the present application and processes data by executing or executing instructions, programs, code sets, or instruction sets stored in the storage medium 20, invoking data stored in the storage medium 20. The processor 21 may be at least one of an application specific integrated circuit, a digital signal processor, a digital signal processing device, a programmable logic device, a field programmable gate array, a central processing unit, a controller, a microcontroller, and a microprocessor. It will be appreciated that the electronics for implementing the functions of the processor 21 described above may also be other for different devices.
Wherein the storage medium 20 may be used to store instructions, programs, code sets, or instruction sets. The storage medium 20 may include a storage program area and a storage data area, wherein the storage program area may store instructions for implementing an operating system, instructions for at least one function, instructions for implementing any of the above-described timestamp synchronization methods, and the like; the storage data area may store data or the like involved in any of the above-described timestamp synchronization methods.
In another embodiment of the present application, there is also provided a computer-readable storage medium having stored therein computer-executable instructions that, when executed by a processor, are configured to implement any one of the above-described methods of timestamp synchronization.
The computer readable storage medium may be various media capable of storing program codes, such as a usb disk, a removable hard disk, a read-only memory, a random access memory, or an optical disk.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. The timestamp synchronization method is characterized by being applied to a Field Programmable Gate Array (FPGA) high-speed serial computer expansion bus standard PCIE network card, and comprises the following steps:
acquiring Network Time Protocol (NTP) time information and local time keeping time information of a current period;
calculating the time difference between the NTP time information and the local time keeping time information to obtain a first time difference value of the current period;
obtaining n historical time differences of n continuous historical periods, wherein each historical time difference is obtained by pre-calculating the time difference between NTP time information and local time keeping time information of the historical period corresponding to each historical time difference, the n continuous historical periods comprise the previous period of the current period, and n is a positive integer greater than 1;
comparing the first time difference value with n historical time difference values, and confirming a stepping fine adjustment parameter according to a comparison result, wherein the stepping fine adjustment parameter comprises a positive fine adjustment action parameter and a negative fine adjustment action parameter;
and according to the stepping fine tuning parameters, adjusting the local time keeping accumulation logic and outputting the current time stamp information.
2. The method of claim 1, wherein said calculating the time difference between the NTP time information and the local time keeping time information, after obtaining the first time difference value of the current period, further comprises:
judging whether the first time difference value is larger than or equal to a preset threshold value,
if yes, covering the current local time keeping time information according to the NTP time information, and outputting the current time stamp information;
if not, executing the step of acquiring n historical time differences of n continuous historical periods.
3. The method of claim 1, wherein comparing the first time difference value with n historical time difference values and determining a step trimming parameter according to the comparison result comprises:
comparing the first time difference value and n historical time difference values,
when the first time difference value and the n historical time difference values are positive or negative, arranging the first time difference value and the n historical time difference values according to a periodic sequence to obtain a first sequence, wherein the first time difference value is positioned at the last position of the first sequence;
calculating a first-order difference of the first sequence to obtain a second sequence;
taking absolute values of the numerical values in the second sequence to obtain a third sequence;
calculating the first-order difference of the third sequence to obtain a fourth sequence;
judging whether the values in the fourth sequence are all greater than or equal to 0,
if yes, outputting positive fine tuning action parameters when the first time difference value and the n historical time difference values are positive, or outputting negative fine tuning action parameters when the first time difference value and the n historical time difference values are negative;
if not, maintaining the current step fine tuning parameters;
when the first time difference value is positive and the historical time difference value corresponding to the previous period of the current period is negative, the current stepping fine adjustment parameter is maintained;
and when the first time difference value is negative and the historical time difference value corresponding to the previous period of the current period is positive, maintaining the current stepping fine adjustment parameter.
4. The method of claim 1, wherein adjusting the local daemon accumulation logic based on the step trimming parameter and outputting current timestamp information comprises:
and modifying the offset parameter of the time keeping timer according to the stepping fine tuning parameter, and outputting the current time stamp information.
5. The method of claim 4, wherein the watch dog timer is comprised of an integer portion and a fractional floating point portion, and wherein modifying the offset parameter of the watch dog timer based on the step trimming parameter comprises:
accumulating the step fine tuning parameter in the fraction floating point portion of the watch dog timer.
6. The method of claim 4 or 5, wherein the time keeping timer is a 96-bit counter.
7. The method of claim 1, wherein the step-wise trimming parameter uses 0.1PPM of the current crystal oscillator as a trimming step, wherein PPM represents parts per million.
8. A time stamp synchronization system, wherein the system is applied to a field programmable gate array FPGA high-speed serial computer expansion bus standard PCIE network card, the system comprising:
the first acquisition module is used for acquiring Network Time Protocol (NTP) time information and local time keeping time information of the current period;
the difference value calculation module is used for calculating the time difference between the NTP time information and the local time keeping time information to obtain a first time difference value of the current period;
the second acquisition module is used for acquiring n historical time differences of n continuous historical periods, wherein each historical time difference is obtained by pre-calculating the time difference between the NTP time information and the local time keeping time information of the historical period corresponding to each historical time difference, the n continuous historical periods comprise the previous period of the current period, and n is a positive integer greater than 1;
the step fine adjustment module is used for comparing the first time difference value with n historical time difference values and confirming step fine adjustment parameters according to comparison results, wherein the step fine adjustment parameters comprise positive fine adjustment action parameters and negative fine adjustment action parameters;
and the local timekeeping module is used for adjusting the local timekeeping accumulation logic according to the stepping fine adjustment parameter and outputting the current timestamp information.
9. A time stamp synchronizing terminal, comprising: a storage medium and a processor;
computer-executable instructions are stored in the storage medium;
the processor executes computer-executable instructions stored on the storage medium to implement the method of any one of claims 1 to 7.
10. A computer readable storage medium having stored therein computer executable instructions which when executed by a processor are adapted to carry out the method of any one of claims 1 to 7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310265986.4A CN116032411A (en) | 2023-03-17 | 2023-03-17 | Time stamp synchronization method, system, terminal and storage medium |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310265986.4A CN116032411A (en) | 2023-03-17 | 2023-03-17 | Time stamp synchronization method, system, terminal and storage medium |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116032411A true CN116032411A (en) | 2023-04-28 |
Family
ID=86074274
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310265986.4A Pending CN116032411A (en) | 2023-03-17 | 2023-03-17 | Time stamp synchronization method, system, terminal and storage medium |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116032411A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117009146A (en) * | 2023-09-28 | 2023-11-07 | 金篆信科有限责任公司 | Data synchronization method, device, computer equipment and storage medium |
| CN117081960A (en) * | 2023-10-16 | 2023-11-17 | 深圳华云信息系统科技股份有限公司 | Data transmission performance testing method and device, electronic equipment and storage medium |
-
2023
- 2023-03-17 CN CN202310265986.4A patent/CN116032411A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117009146A (en) * | 2023-09-28 | 2023-11-07 | 金篆信科有限责任公司 | Data synchronization method, device, computer equipment and storage medium |
| CN117009146B (en) * | 2023-09-28 | 2024-03-08 | 金篆信科有限责任公司 | Data synchronization method, device, computer equipment and storage medium |
| CN117081960A (en) * | 2023-10-16 | 2023-11-17 | 深圳华云信息系统科技股份有限公司 | Data transmission performance testing method and device, electronic equipment and storage medium |
| CN117081960B (en) * | 2023-10-16 | 2023-12-22 | 深圳华云信息系统科技股份有限公司 | Data transmission performance testing method and device, electronic equipment and storage medium |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN116032411A (en) | Time stamp synchronization method, system, terminal and storage medium | |
| CN109600186B (en) | Clock synchronization method and device | |
| CN103368676B (en) | A kind of strange land based on cyclic pulse signal synchronous data sampling method and system | |
| CN115987477B (en) | Multi-reference source time synchronization method, system, module and medium | |
| CN111831056A (en) | Real-time clock calibration module and method and real-time clock chip | |
| CN113392063B (en) | Time synchronization method, device and system | |
| CN105306159A (en) | Clock timestamp compensation method and clock timestamp compensation device | |
| US11303376B2 (en) | Information processing apparatus and time synchronization method | |
| JP5972450B2 (en) | Signal processing device | |
| CN100595716C (en) | Method and apparatus for synchronizing clock of distributed processing system | |
| US11853116B2 (en) | Clock error-bound tracker | |
| CN202759413U (en) | An on-line time error correcting system based on a satellite and a constant temperature crystal oscillator | |
| CN116015523A (en) | Time synchronization method and device and electronic equipment | |
| CN114489239A (en) | Method and device for dynamically calibrating real-time clock | |
| CN110618604B (en) | Method and device for improving time keeping precision by using NTP auxiliary source | |
| CN114296511A (en) | Real-time clock calibration circuit, method and chip structure | |
| CN114070762B (en) | Network monitoring probe assembly, synchronization method and data acquisition and analysis device | |
| CN112019288B (en) | Time synchronization method, service single board and network equipment | |
| CN109359067B (en) | Method and system for acquiring delay step time in storage module | |
| CN110442186A (en) | Deviation correction method, intelligent terminal and storage medium when a kind of clock is walked | |
| CN114172607B (en) | Synchronization device and synchronization method between main clock and standby clock | |
| CN116886080B (en) | Control device for timing device and control method thereof | |
| CN117826560B (en) | Method and device for calibrating B code time service system based on satellite navigation | |
| CN116208289B (en) | Time synchronization method and device based on white box switch and electronic equipment | |
| WO2021253339A1 (en) | Method and apparatus for synchronization source selection |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |