JP5972450B2 - Signal processing device - Google Patents

Description

  The present invention relates to a time synchronization control technique, and more particularly to a time synchronization control technique in an apparatus that collects the amount of electricity of a power transmission line or a bus.

There is a protection control system that collects the amount of electricity (voltage value, current value) of power transmission lines and buses at a plurality of locations, immediately shuts down the system when an abnormality is detected from those amounts of electricity, and suppresses the spread of accidents.
In this protection control system, in order to reduce the phase shift of collected electricity, a signal synchronized between collection points is required as a reference for collecting electricity.
In recent protection relay devices, a plurality of data collection devices (hereinafter also referred to as MU: Merging Unit) via a local area network (process bus) for a single arithmetic device (hereinafter also referred to as IED: Intelligent Electronic Device). ) Is connected.
Each MU matches the data sampling timing and time stamp value between the MUs by synchronizing the timing based on the synchronization signal (1PPS signal: 1 Pulse Per Second signal).

JP 2001-305177 A

The reception period of the 1PPS signal is 1 second.
Therefore, each MU is equipped with a high-accuracy crystal oscillator (frequency deviation: ± several ppm) in the clock generation circuit to generate a high-precision clock with a small frequency deviation, and the sampling timing deviation between MUs is ± several times per second. Must be kept below microseconds.
Therefore, an inexpensive general-purpose oscillation circuit (frequency deviation accuracy of about ± 50 ppm) generally used in digital circuits cannot be used, and there is a problem that costs increase.

  The present invention has been made to solve the above-described problems, and has as its main object to enable highly accurate synchronous control even when a general-purpose oscillation circuit having a frequency deviation of about ± 50 ppm is used. To do.

The signal processing apparatus according to the present invention is
A 1PPS signal receiving unit that receives a 1PPS (1 Pulse Per Second) signal;
A clock generation unit that generates a clock signal having a clock period smaller than that of one second;
Each time the 1PPS signal is input from the 1PPS signal receiving unit, the clock signal is input from the clock generation unit, and the 1PPS signal is input, a clock deviation that is a frequency deviation of the clock signal with respect to the 1PPS signal is measured. A clock deviation measuring unit to
A deviation measurement value holding unit for holding a plurality of clock deviation measurement values obtained by a plurality of measurements in the clock deviation measurement unit;
The latest clock deviation measurement value of a plurality of clock deviation measurement values held in the deviation measurement value holding unit is compared with another clock deviation measurement value, and the latest clock deviation measurement value is compared with another clock deviation. The latest clock deviation measurement value is output to the output destination when the measurement value matches within a predetermined allowable range, and the latest clock deviation measurement value does not match the other clock deviation measurement value within the allowable range. And a deviation measurement value selector for outputting any one of the other clock deviation measurement values to the output destination.

According to the present invention, since a clock deviation between a clock signal having a minute clock period compared to 1 second and a 1PPS signal is used, even if a general-purpose oscillation circuit having a frequency deviation of about ± 50 ppm is used, high accuracy is achieved. Synchronous control can be performed.
Further, since the plurality keeps the clock deviation measuring values, when the latest clock deviation measuring value does not match the other clock deviation measuring values, select other clock deviation measurement values rather than the latest clock deviation measuring value, Even when an abnormality occurs in the reception of the 1PPS signal, the abnormality does not affect the generation of the sampling signal.

FIG. 3 is a diagram illustrating a configuration example of a data collection device according to the first embodiment. FIG. 3 is a diagram illustrating an operation example of the data collection device according to the first embodiment. FIG. 4 is a diagram illustrating a configuration example of a data collection device according to a second embodiment. FIG. 10 is a diagram illustrating an operation example of the data collection device according to the second embodiment. The figure which shows the structure used as the premise of the data collection device which concerns on Embodiment 1,2. The figure explaining the operation principle of the data collection device which concerns on Embodiment 1,2. The figure explaining the operation principle of the data collection device which concerns on Embodiment 1,2. The figure explaining the operation principle of the data collection device which concerns on Embodiment 1,2. FIG. 3 is a diagram illustrating a hardware configuration example of the data collection device according to the first and second embodiments.

Embodiment 1 FIG.
In this embodiment, a data collection device (MU) that calculates a correction value of a counter (sampling signal generation counter) that determines a cycle for sampling an electric quantity according to a clock deviation measurement value will be described.
Thereby, even if a general-purpose oscillation circuit having a frequency deviation of about ± 50 ppm is used, high-precision synchronization can be achieved.
Further, the data collection device of the present embodiment holds a plurality of clock deviation measurement values, and if the latest clock deviation measurement value matches the previous clock deviation measurement value, the latest clock deviation measurement value is selected and does not match. If selects the clock deviation measuring value just before not the latest clock deviation measuring values.
For this reason, even when an abnormality such as the interruption of the 1PPS signal occurs, the abnormality does not affect the generation of the sampling signal.

FIG. 1 shows a configuration example of a data collection device 100 according to the present embodiment.
The data collection device 100 corresponds to an example of a signal processing device.
The data collection apparatus 100 according to the present embodiment includes a deviation measurement value holding unit 301 that holds a plurality of clock deviation measurement values, and a subsequent stage among the plurality of clock deviation measurement values held in the deviation measurement value holding unit 301. The main feature is that it includes a clock deviation value generation unit 302 that selects a clock deviation measurement value to be output to the sampling period counting unit 105.

  In consideration of ease of understanding, first, the operation of the data collection device 100 according to the present embodiment is performed using a data collection device that does not include the deviation measurement value holding unit 301 and the clock deviation value generation unit 302. The principle will be explained.

  FIG. 5 shows a configuration of the data collection device 150 in which the deviation measurement value holding unit 301 and the clock deviation value generation unit 302 are excluded from the data collection device 100 according to the present embodiment.

The data collection device 150 receives the 1PPS signal and transmits data indicating the measured amount of electricity to the arithmetic device 200.
The arithmetic device 200 that is an IED detects an abnormality in the power system and suppresses the spread of the accident by shutting off the system.
The transmission source of the 1PPS signal may be the arithmetic device 200 or another device having a GPS (Global Positioning System) receiver.

  In the data collection device 150, the 1PPS signal receiving unit 101 receives the 1PPS signal.

The clock generation unit 102 generates an operation clock signal (hereinafter simply referred to as a clock signal) of the data collection device 150.
The clock cycle of the clock signal is very small compared to 1 second.

  The clock deviation measuring unit 103 measures a clock deviation which is a frequency deviation with respect to the clock signal of the data collection device 150 with respect to the period of the 1PPS signal.

The deviation measurement value holding unit 104 holds the clock deviation measurement value measured by the clock deviation measurement unit 103.
Unlike the deviation measurement value holding unit 301 in FIG. 1, the deviation measurement value holding unit 104 holds only one clock deviation measurement value.

The sampling period count unit 105 counts the time interval of the timing for sampling the amount of electricity.
The sampling cycle counting unit 105 receives the 1PPS signal from the 1PPS signal receiving unit 101, receives the clock signal from the clock generation unit 102, starts counting according to the clock cycle of the clock signal when the 1PPS signal is input, and completes the counting. When the count up to the value is completed, the count from the count start value is started.
The sampling period counting unit 105 corresponds to an example of a counter.

  The sampling signal generation unit 106 generates a sampling timing signal (also referred to as a sampling signal) that is a pulse indicating the sampling timing from the count value of the sampling period counting unit 105.

  The electric quantity measurement unit 107 measures the electric quantity of the power system at the timing of the pulse (sampling signal) generated by the sampling signal generation unit 106.

  The data generation unit 108 converts the electrical quantity measured by the electrical quantity measurement unit 107 into digital data in a communication frame format that can be transmitted to a local area network (process bus).

  The communication unit 109 transmits the digital data generated by the data generation unit 108 to the arithmetic device 200 via a local area network (process bus).

  Next, an operation example of the data collection device 150 will be described.

The data collection device 150 receives a 1 PPS signal from the arithmetic device 200 using transmission means such as an optical fiber cable or an electric signal cable.
The 1PPS signal is a pulse signal indicating a period of 1 second of absolute time, and the period error is as small as several ppm or less.
The 1PPS signal is received by the 1PPS signal receiving unit 101 and distributed to the clock deviation measuring unit 103 and the sampling period counting unit 105.

In the clock generation unit 102, a clock signal of the data collection device 150 is generated and distributed to the clock deviation measurement unit 103 and the sampling period counting unit 105.
The clock deviation measuring unit 103 measures a clock deviation that is a difference between the reception timing of the 1PPS signal and one second counted by the clock signal of the data collecting device 150, and the measurement result is held in the deviation measured value holding unit 104. .

  The sampling period count unit 105 is a counter that counts up or down with the clock signal generated by the clock generation unit 102.

Here, the upper limit value (count completion value) of the count value for generating the sampling period is determined based on the clock deviation measurement value held in the deviation measurement value holding unit 104 so as to match the accuracy of the 1PPS signal. The
For example, when the AC frequency of the power system is 50 Hz and the number of samplings per AC cycle is 80, the sampling cycle is 250 microseconds.
If the accuracy of the 1PPS signal is 0 ppm, 250 microseconds corresponds to 20000 counts with an 80 MHz counter.
Here, when the frequency deviation of the clock signal is −50 ppm, the count of 20000 times is 250.0125 microseconds, and the sampling period is increased by 12.5 nanoseconds.
Therefore, when the clock deviation measurement value held in the deviation measurement value holding unit 104 is −50 ppm, the time limit of the sampling period is set to 250 microseconds (at 0 ppm by setting the count upper limit value of the 80 MHz counter to 19999 times. Time width).

The sampling signal generation unit 106 generates a sampling timing signal to be given to the electric quantity measurement unit 107 using the count value generated by the sampling period counting unit 105.
The electric quantity measuring unit 107 measures the electric quantity (current, voltage) of the power system by receiving the sampling timing signal generated by the sampling signal generating unit 106.
Data generator 108 for transmitting the electrical quantity measured at the sampling signal generator 106 to the arithmetic unit 200, configured in the form of a possible communication frames transmitted by the communication unit 109.
The communication unit 109 transmits the communication frame is data generating unit 108 to generate the arithmetic unit 200.

  Next, operations of the clock deviation measuring unit 103, the deviation measured value holding unit 104, and the sampling period counting unit 105 will be described with reference to FIG.

The clock deviation measuring unit 103 starts generating a 10-millisecond periodic pulse starting from the time when the 1PPS signal is received and using the clock signal as a count source.
When the value of the 10-millisecond pulse count counted up by the 10-millisecond periodic pulse reaches 99, the clock deviation measurement unit 103 starts counting by the clock deviation measurement counter using the clock signal as a count source.
When the 1PPS signal is received after the count starts, the clock deviation measuring unit 103 stops counting the clock deviation measuring counter.

By subtracting the ideal count value of 10 milliseconds (count value when the clock deviation is 0 ppm) from the count value of the clock deviation measurement counter, the clock frequency deviation accumulation amount of the clock signal during the reception of the 1 PPS signal (for example, reference numeral 500 in FIG. 6). The time corresponding to the rectangle) can be obtained.
The deviation accumulation amount (clock deviation measurement value) obtained by the clock deviation measurement unit 103 is held in the deviation measurement value holding unit 104.

  The operation of the clock deviation measuring unit 103 will be described in more detail with reference to FIG.

When the 1PPS signal is input to the clock deviation measuring unit 103, a 10-millisecond counter that counts according to the clock period of the clock signal operates.
For example, when the clock signal is 80 MHz, the count is in units of 12.5 nanoseconds, so 800000 counts to 10 milliseconds.
When the count of 10 milliseconds is the 99th time, if the counter reaches 800,000, the measurement of the clock signal of the data collection device 150 takes 1 second.
A difference in reception timing of 1 second and 1 PPS signal counted by this clock signal is a measured value of the clock deviation.
In FIG. 7 , since the 1 PPS signal is received when the counter of 10 milliseconds is 798400 counts, the clock signal counts late by 20 microseconds ((800000-798400) × 12.5 nanoseconds) in 1 second. This value is a measured value of the clock deviation.
With such an operation, the clock deviation measuring unit 103 measures a clock deviation that is a divergence time per second of the clock signal with respect to the 1PPS signal, and stores the clock deviation measured value in the deviation measured value holding unit 104.
When the count for 1 second by the clock signal is 20 microseconds slower than the 1PPS signal, the sampling signal is output only 3999 times per second as shown in FIG. 8, and the sampling signal is output at a cycle of 250 microseconds. It will not be done.
For this reason, in order to perform correction for 20 microseconds, it is necessary to change the upper limit value (count completion value) of the sampling period counter.

As shown in FIG. 6, the sampling period count unit 105 includes a sampling signal generation counter.
The sampling cycle count unit 105 calculates the deviation accumulation amount (clock deviation measurement value) per sampling cycle from the deviation accumulation amount (clock deviation measurement value) for one second held in the deviation measurement value holding unit 104.
For example, if the sampling cycle is 250 microseconds as described above, the sampling signal generation counter samples 4000 times per second, so that the deviation accumulation for 1 second held in the deviation measurement value holding unit 104 is performed. The amount (clock deviation measurement value) is divided by 4000 to obtain a deviation accumulation amount (clock deviation measurement value) per sampling period.
The sampling cycle count unit 105 adds or subtracts the calculated accumulated deviation amount from the ideal value of the sampling cycle count (count value when the clock deviation is 0 ppm), and uses this value as the upper limit value (count completion value) of the sampling signal generation counter. Set.
In FIG. 6, reference numeral 600 indicates the upper limit value of the sampling signal generation counter.
The sampling signal generation unit 106 monitors the count value of the sampling signal generation counter, and makes the sampling timing signal for the electric quantity measurement unit 107 significant at the timing when the count value becomes 0 (count start value).
The reference numeral 600 may be a different value for each sampling. When the accumulated amount of deviation (clock deviation measurement value) for one second is not divisible by the number of samplings or smaller than 1, fine adjustment can be performed by changing the upper limit value of the sampling signal generation counter for each sampling. For example, in three samplings, the value of the symbol 600 is set to the ideal value (count value when the clock deviation is 0 ppm) once, and the value 2 less than the ideal value is set to twice. In this case, adjustment for four clocks is performed during three samplings, and adjustment for 1.33 clocks per sampling can be performed.

In this way, the data collection device 150 shown in FIG. 5 measures the deviation amount of the clock signal with respect to the 1PPS signal, and determines the upper limit value of the sampling period counting unit 105 using the measurement result, thereby determining the sampling period. Match the time width to the ideal time width (time width at 0 ppm).

  Next, it is possible to avoid the generation of an incorrect sampling period due to an erroneous clock deviation measurement value when a reception abnormality occurs such that the 1PPS signal input is temporarily interrupted by the data collection device 100 of FIG. Explain that.

The difference between the configuration of FIG. 1 and the configuration of FIG. 5 is that, in FIG. 1, a deviation measurement value holding unit 301 is arranged instead of the deviation measurement value holding unit 104, and a clock deviation value generation unit 302 is added. It is.
Except for the deviation measurement value holding unit 301 and the clock deviation value generation unit 302, the configuration is the same as that shown in FIG.

The deviation measurement value holding unit 301 holds a plurality of clock deviation measurement values measured by the clock deviation measurement unit 103.
That is, the deviation measurement value holding unit 301 holds a plurality of clock deviation measurement values obtained by a plurality of measurements in the clock deviation measurement unit 103.

The clock deviation value generation unit 302 compares the plurality of clock deviation measurement values of the deviation measurement value holding unit 301 and outputs the clock deviation measurement value output to the sampling period counting unit 105, which is the output destination, to the plurality of clock deviation measurement values. Choose from.
The clock deviation value generation unit 302 corresponds to an example of a deviation measurement value selection unit.

  Next, an operation example of the data collection device 100 will be described with reference to FIG.

The deviation measurement value holding unit 301 has a plurality of holding units (storage areas), and the latest clock deviation measurement value is held in the holding unit 1, the previous clock deviation measurement value is held in the holding unit 2, and the previous clock deviation is two. The measured value is stored in the holding unit 3.
The amount of deviation of the clock signal from the 1PPS signal varies depending on environmental factors such as a temperature difference between day and night, but does not change within a short time such as several seconds.
For this reason, the three clock deviation measurement values in the deviation measurement value holding unit 301 should match.

The clock deviation value generation unit 302 compares the plurality of clock deviation measurement values of the deviation measurement value holding unit 301, and if the latest clock deviation measurement value matches another clock deviation measurement value, the latest clock deviation measurement value. It is determined that the measurement value is normal, and the latest clock deviation measurement value is selected as a value to be output to the sampling period count unit 105.
If the latest clock deviation measurement value does not coincide with other clock deviation measurement values, the clock deviation value generation unit 302 determines that an abnormality has occurred, for example, the 1PPS signal is interrupted, and does not update the clock deviation measurement value. Maintain the current value.
That is, the clock deviation value generation unit 302 selects the clock deviation measurement value held in the holding unit 2 as a value to be output to the sampling period counting unit 105.
Then, the clock deviation value generation unit 302 outputs the selected clock deviation measurement value to the sampling period counting unit 105.

As a result, even when an abnormality occurs in the reception of the 1PPS signal, it is possible to prevent the abnormality from affecting the sampling signal generation.
1 and 2, the number of holding units in the deviation measurement value holding unit 301 has been described as three, but two or more arbitrary values may be used.
In the above description, the latest clock deviation measurement value is output to the sampling period counting unit 105 only when the latest clock deviation measurement value in the deviation measurement value holding unit 301 completely matches the other clock deviation measurement value. It was decided to.
On the other hand, when a predetermined allowable range is provided and the latest clock deviation measured value matches another clock deviation measured value within the allowable range, the latest clock deviation measured value is input to the sampling period count unit 105. You may make it output.

Embodiment 2. FIG.
In the first embodiment described above, the deviation amount of the clock signal with respect to the 1PPS signal is measured, and the count upper limit value of the sampling period count unit is determined using the measurement result, whereby the time width of the sampling period is set to the ideal time width (0 ppm). It was explained that it matches the time width in (1).
In the first embodiment, an example is shown in which generation of a sampling signal due to an erroneous clock deviation measurement value is prevented when there is an abnormality in reception of a 1PPS signal.
In this embodiment, when the interruption of the 1PPS signal takes a long time or when the 1PPS signal is received for the first time after the data collector is turned on, the generation start position of the sampling timing signal is matched with the reception timing of the 1PPS signal. Indicates the method.

In FIG. 3, the sampling position adjustment unit 501 generates a timing correction amount for adjusting the generation start position of the sampling timing signal generated by the sampling signal generation unit 106 to the 1PPS signal reception timing.
More specifically, the sampling position alignment unit 501 monitors the input timing of the 1PPS signal to the sampling cycle counting unit 105 and the timing of the count start value in the sampling cycle counting unit 105.
When the timing of the count start value does not coincide with the input timing of the 1PPS signal, the sampling alignment unit 501 calculates a timing correction value for making the timing of the count start value coincide with the input timing of the 1PPS signal. .
Then, the sampling period counting unit 105 changes the count upper limit value (count completion value) using the timing correction value calculated by the sampling position alignment unit 501, and matches the timing of the count start value with the input timing of the 1PPS signal. .
Note that the sampling position alignment unit 501 corresponds to an example of a timing correction value calculation unit.
The elements other than the sampling position alignment unit 501 are the same as those shown in FIG.

  Next, an operation example of the data collection device 100 according to the present embodiment will be described with reference to FIG.

In order for sampling timings to match among a plurality of data collection devices, it is necessary that the sampling timing signal start position matches the reception timing of the 1PPS signal in addition to the matching of the sampling period time widths. .
For this reason, in the calculation formula for determining the upper limit value of the sampling signal generation counter, in addition to setting the time width of the sampling period in accordance with the clock deviation measurement value (2), (3) for shifting the generation timing of the sampling timing signal )is necessary.
<Sampling signal generation counter upper limit value determination formula>
Counter upper limit value = (1) Counter base value (cycle count value at 0 ppm)
± (2) Clock deviation value ± (3) Timing correction amount

  When the interruption of the 1PPS signal lasts for a long time or when the 1PPS signal is received for the first time after the data collector is turned on, the amount of synchronization deviation (the difference between the sampling timing signal position and the 1PPS signal reception position) in FIG. ) And the amount of synchronization deviation is different for each data collection device.

The sampling alignment unit 501 calculates the amount of synchronization deviation from the count value of the sampling signal generation counter at the time of 1PPS reception.
Then, the sampling position alignment unit 501 outputs the calculated amount of synchronization deviation to the sampling period counting unit 105 as a timing correction amount.
The sampling period counting unit 105 can adjust the amount of synchronization deviation to 0 by changing the counter upper limit value based on the determination formula of the sampling signal generation counter upper limit value.

The sampling alignment unit 501 determines the direction of adjusting the sampling timing signal, that is, whether to add or subtract the (3) timing correction amount, according to the count value of the sampling signal generation counter when receiving the 1PPS signal.
4, when the reception timing of the 1PPS signal is earlier than the counter upper limit value even after the intermediate value of the sampling signal generating counter (of FIG. 4 (1)), the sampling aligning unit 501, the counter upper limit value By subtracting the timing correction amount from the sampling timing signal, the sampling timing signal coincides with the 1PPS signal reception timing.
In addition, when the reception timing of the 1PPS signal is earlier than the intermediate value of the sampling signal generation counter and later than the counter start value ((2) in FIG. 4), the sampling position alignment unit 501 sets the timing to the counter upper limit value. By adding the correction amount, the sampling timing signal is made coincident with the 1PPS signal reception timing.

Note that (3) the adjustment of the timing correction amount may not be performed once but may be performed in a plurality of times.
For example, if you want to limit the change in the sampling timing signal interval to 75 nanoseconds or less and the synchronization deviation amount is 750 ns, the maximum adjustment amount is 75 ns (4 counts for the 80 MHz counter) and the counter upper limit is adjusted. It may be performed 10 times.
Further, the adjustment amount for each time may not be the same.

  As described above, according to the present embodiment, when the interruption of the 1PPS signal takes a long time or when the 1PPS signal is received for the first time after the data collecting device is turned on, the generation start position of the sampling timing signal is set. It becomes possible to match the 1PPS signal reception timing.

In Embodiments 1 and 2, the example in which sampling period counting section 105 counts by increment has been described, so that the count start value is the lower limit value of sampling period counting section 105 and the count completion value is the upper limit value. .
When the sampling cycle count unit 105 counts by decrement, the count start value becomes the upper limit value of the sampling cycle count unit 105, and the count completion value becomes the lower limit value.

Finally, a hardware configuration example of the data collection device 100 shown in the first and second embodiments will be described with reference to FIG.
The data collection device 100 is a computer, and each element of the data collection device 100 can be realized by a program.
As a hardware configuration of the data collection device 100, a control device 901, an external storage device 902, a main storage device 903, a communication device 904, an input / output device 905, a clock generation circuit 906, and a counter 907 are connected to the bus.

The control device 901 is a CPU that executes a program.
The external storage device 902 is, for example, a ROM (Read Only Memory), a flash memory, or a hard disk device.
The main storage device 903 is a RAM (Random Access Memory).
The deviation measured value holding unit 301 is realized by the main storage device 903, for example.
The communication device 904 corresponds to the physical layer of the 1PPS signal receiving unit 101 and the communication unit 109.
The input / output device 905 is, for example, a mouse, a keyboard, a display device, or the like.
The clock generation circuit 906 includes a crystal oscillator and generates a clock signal for the data collection device 100.
The clock generation unit 102 is realized by a clock generation circuit 906.
The sampling period counting unit 105 is realized by a counter 907.

The program is normally stored in the external storage device 902, and is loaded into the main storage device 903 and sequentially read and executed by the control device 901.
The program is a program that realizes the functions described as “˜units” shown in FIG. 1 and FIG. 3 (however, except for the clock generation unit 102 and the deviation measurement value holding unit 301, the same applies hereinafter).
Further, an operating system (OS) is also stored in the external storage device 902. At least a part of the OS is loaded into the main storage device 903, and the control device 901 executes the OS while the “˜ part” shown in FIG. ”Is executed.
In the description of the first and second embodiments, “measurement of”, “count of”, “change of”, “determination”, “setting of”, “designation of”, “ Results of the processes described as "Calculation of", "Judgment of", "Judgment of", "Selection of", "Generation of", "Input of", "Reception of" Information, data, signal values, and variable values are stored in the main storage device 903 as files.

  The configuration in FIG. 9 is merely an example of the hardware configuration of the data collection device 100, and the hardware configuration of the data collection device 100 is not limited to the configuration illustrated in FIG. Also good.

  DESCRIPTION OF SYMBOLS 100 Data collection device, 101 1PPS signal receiving part, 102 Clock generation part, 103 Clock deviation measurement part, 104 Deviation measurement value holding part, 105 Sampling period count part, 106 Sampling signal generation part, 107 Electric quantity measurement part, 108 Data generation Unit, 109 communication unit, 301 deviation measurement value holding unit, 302 clock deviation value generation unit, and 501 sampling alignment unit.

Claims (7)

A 1PPS signal receiving unit that receives a 1PPS (1 Pulse Per Second) signal;
A clock generation unit that generates a clock signal having a clock period smaller than that of one second;
Each time the 1PPS signal is input from the 1PPS signal receiving unit, the clock signal is input from the clock generation unit, and the 1PPS signal is input, a clock deviation that is a frequency deviation of the clock signal with respect to the 1PPS signal is measured. A clock deviation measuring unit to
A deviation measurement value holding unit for holding a plurality of clock deviation measurement values obtained by a plurality of measurements in the clock deviation measurement unit;
The latest clock deviation measurement value of the plurality of clock deviation measurement values held in the deviation measurement value holding unit is compared with another clock deviation measurement value, and the latest clock deviation measurement value is compared with another clock. Outputs the latest clock deviation measurement value to the output destination when the deviation measurement value matches within a predetermined allowable range, and the latest clock deviation measurement value does not match with other clock deviation measurement values within the allowable range And a deviation measurement value selection unit that outputs any one of the clock deviation measurement values of the other clock deviation measurement values to the output destination. The signal processing device further includes:
The 1PPS signal is input from the 1PPS signal receiving unit, the clock signal is input from the clock generation unit, and the count from the count start value to the count completion value is performed according to the clock cycle of the clock signal, and the count is completed A counter that starts counting from the count start value when the count to the value is finished,
The input timing of the 1PPS signal to the counter and the timing of the count start value in the counter are monitored, and when the timing of the count start value does not coincide with the input timing of the 1PPS signal, the count start value A timing correction value calculation unit for calculating a timing correction value for matching the timing of the above to the input timing of the 1PPS signal,
The counter is
The timing correction value calculated by the timing correction value calculation unit is used to change the count completion value so that the timing of the count start value coincides with the input timing of the 1PPS signal. Signal processing equipment. The timing correction value calculator is
When the input timing of the 1PPS signal to the counter is later than the intermediate value between the count start value and the count completion value and before the count completion value, the counter completes the count completion. The timing correction value is subtracted from the value,
When the input timing of the 1PPS signal to the counter is after the count start value and before the intermediate value, the counter is caused to add a timing correction value to the count completion value. The signal processing apparatus according to claim 2. The timing correction value calculator is
Divide the calculated timing correction value into n (n is an integer of 2 or more),
The counter is
The division value of the timing correction value is used as the n count completion value to change the n count completion value so that the timing of the count start value coincides with the input timing of the 1PPS signal. The signal processing apparatus according to claim 2 or 3. A 1PPS signal receiving unit that receives a 1PPS (1 Pulse Per Second) signal;
A clock generation unit for generating a clock signal having a clock period smaller than 1 second;
The 1PPS signal is input from the 1PPS signal receiving unit, the clock signal is input from the clock generation unit, and the count from the count start value to the count completion value is performed according to the clock cycle of the clock signal, and the count is completed A counter that starts counting from the count start value when the count to the value is finished,
The input timing of the 1PPS signal to the counter and the timing of the count start value in the counter are monitored, and when the timing of the count start value does not coincide with the input timing of the 1PPS signal, the count start value A timing correction value calculation unit for calculating a timing correction value for matching the timing of the above to the input timing of the 1PPS signal,
The counter is
The signal processing apparatus, wherein the count completion value is changed using the timing correction value calculated by the timing correction value calculation unit, and the timing of the count start value is made coincident with the input timing of the 1PPS signal. The timing correction value calculator is
When the input timing of the 1PPS signal to the counter is later than the intermediate value between the count start value and the count completion value and before the count completion value, the counter completes the count completion. The timing correction value is subtracted from the value,
When the input timing of the 1PPS signal to the counter is after the count start value and before the intermediate value, the counter is caused to add a timing correction value to the count completion value. The signal processing apparatus according to claim 5. The timing correction value calculator is
Divide the calculated timing correction value into n (n is an integer of 2 or more),
The counter is
The division value of the timing correction value is used as the n count completion value to change the n count completion value so that the timing of the count start value coincides with the input timing of the 1PPS signal. The signal processing device according to claim 5 or 6.

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