JP4535288B2 - Distributed control system - Google Patents

Description

  The present invention relates to a distributed control system in which a central device and distributed terminal devices are connected by a transmission line in a multi-terminal fault location device and a measuring device of an electric power system.

In a system that collects system information of remote multi-points at each terminal device installed in a distributed manner, and sends these collected data (sampling data) to the central unit to calculate, it is necessary to synchronize the sampling timing of this data collection There is.
Conventionally, when data sampling is performed in the power system, a reference signal is acquired for each electrical angle of 30 degrees (1666.6 ... ms in the 50 Hz system) from the transmission system using a PCM carrier relay or a distributed substation LAN. Sampling timing synchronization control. Here, since a synchronization reference having a relatively short period is obtained, it is not necessary to detect and correct a fluctuation error of the oscillation frequency of the clock.

  As a related prior art, Japanese Patent Application Laid-Open No. 8-056153 applies a temperature compensated oscillator, detects the temperature around the oscillator, and has a temperature compensation level (analog value) corresponding to this to be in the oscillation loop. It describes that the oscillation frequency is controlled by changing the capacitance of a variable capacitance element. Furthermore, the gazette uses a GPS (global positioning system) output signal (expected value F), measures the GPS output signal with a clock (voltage controlled oscillator), detects the deviation from the expected value, A method is described in which the clock oscillation frequency is controlled by converting the correction level into analog and controlling the voltage controlled oscillator.

  In other words, this conventional technology uses a GPS receiver that outputs a reference pulse synchronized with UTC (Coordinated Universal Time), and a frequency error detection that detects an error between the output frequency of the oscillator and a given expected frequency using the reference pulse. Means and a control signal generating means for generating a control signal for reducing the error based on the frequency error. Further, this prior art oscillation circuit includes an averaging means for averaging the frequency error the number of times corresponding to the amount of change in the frequency error.

  With these configurations, a high-precision reference pulse output from the GPS receiving means is used, a deviation is detected from the expected frequency of the output frequency of the oscillator, and the oscillator is controlled so as to reduce the deviation. Further, the fluctuation of the reference pulse caused by the reception state of the GPS receiving means is mitigated by the averaging means. As a result, an oscillation frequency having high accuracy and high stability can be obtained.

By the way, if the surrounding environment where the GPS antenna is installed is bad, the surrounding environment changes, or there is an error in the setting of the GPS receiver, the output of the GPS reference timing will not be stable, and in some cases the timing itself will not be output. It is also possible. Further, when the power is turned on, a certain amount of time is required until the output of the GPS reference timing is stably obtained. Further, there may be a case where the GPS reference signal cannot be temporarily obtained due to a change in the surrounding environment where the GPS antenna is installed. In this case, the above-described synchronization control is impossible .

Accordingly, the present invention is, or can not be received is time GPS reference signal, even when transiently GPS reference signal varies / stop, and an object to enable the synchronous sampling data.

In order to solve the above problems, the present invention provides a distributed control system in which a central device and each terminal device installed in a distributed manner are connected by a transmission line.
Each terminal device detects an internal reference signal generating means for generating an internal reference signal, an external reference signal input means for inputting an external reference signal, and a phase difference between the input external reference signal and the internal reference signal. immediately before a phase difference detecting means, and failure detecting means for detecting a system fault occurs, in which the external reference signal from the sampling timing of the internal reference signal immediately after detecting a system fault occurrence by the front Symbol failure detecting means is first input It said measuring means for measuring a time until the sampling timing, and communication means for transmitting the time ΔT obtained by the sum of the phase difference detected by the measuring data and the phase difference detecting means by said measuring unit to the central unit Prepared,
Based on the time ΔT sent from each terminal device, the central device estimates the relative deviation of the internal reference signal between the terminal devices when a system failure occurs, and performs correction using the deviation. And a failure point locating means for locating the failure point.
The external reference signal is a reference signal obtained from GPS, for example.

As described above, according to the present invention, even if the external reference signal (GPS reference signal) cannot be received for a certain period and the system synchronization is not established, the central device recognizes the deviation of the sampling timing of the data. By correcting, stable sampling data can be synchronized .

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
First, a first reference example of the present invention will be described with reference to FIGS.
FIG. 1 is a block diagram conceptually showing the structure of the first reference example of the present invention. In the figure, an external reference signal 1 is input to a measurement counter 3. As the external reference signal 1, a GPS reference signal is used. The crystal oscillator 2 generates a clock and sends it to the measurement counter 3. The measurement counter 3 starts counting when the pulse of the external reference signal 1 is input, and stops counting when the next pulse is input.

  That is, the clock is counted during one period ΔText of the external reference signal Text. Next, the count value Tcnt of the clock is compared with the theoretical period value ΔText of the known external reference signal Text, and a difference Δε between them is calculated (6). The period theoretical value ΔText is the number of clocks counted during one period ΔText of the external reference signal when the crystal oscillator 2 oscillates according to the theoretical value.

Next, the absolute value of the error Δε is compared with a predetermined reference range α (7). If the error Δε is larger than the reference range α, it is determined that the crystal oscillator 2 is defective and an alarm is output (8). If the error Δε is not larger than the reference range α, a correction value ± t corresponding to the value of the error Δε is calculated and sent to the adder 27 (9).
In the adder 27, the correction value ± t is added to the reference division value Tdiv given in advance to correct it, and it is sent to the internal reference timing generation counter 10. When the corrected reference frequency division value Tdiv is input, the internal reference timing generation counter 10 divides the input clock from the crystal oscillator 2 based on the value and outputs it as an internal reference signal Tint ( 12). The configuration shown in FIG. 1 is provided for each device of the system.

  FIG. 2 is a diagram showing that the configuration shown in FIG. 1 is installed in each device constituting the system. In the figure, a reference signal 13 from a GPS or the like is input to an A device 14 and a B device 19 installed at a distance from each other, and input to the synchronous frequency dividing circuits 15 and 20 as an external reference signal Text. The synchronous frequency dividing circuits 15 and 20 correspond to the measurement counter 3 to the internal reference timing generation counter 10 in FIG.

  The synchronous dividers 15 and 20 determine the clocks of the crystal oscillators 18 and 23 based on the input external reference signal Text, and output alarms 16 and 21 if they are out of the reference range. If so, correct it to create and output a more accurate internal reference signal Tint17,22. The A device 14 and the B device 19 execute their respective operations based on the output internal reference signals Tint17, 22.

  In the case of FIG. 2, the external reference signal 13 can be applied between devices far away by using a signal from GPS. Further, the internal reference signals Tint17 and 22 of each device are used for data sampling timing of the power system, for example. In that case, the timing between the devices needs to be synchronized. However, since there is an error in the crystal oscillators 18 and 23 serving as the respective reference clocks, a synchronization error occurs even if the internal reference timing is generated with the same frequency division value. Thus, by adding the above-described correction function, synchronization between the devices can be maintained.

FIG. 3 is a timing chart showing the relationship between the external reference signal Text in FIG. 2 and the internal reference signals Tint17 and 22 respectively created by the A device 14 and the B device 19 based thereon. In the figure, the theoretical count value for one period of the external reference signal Text is the period theoretical value ΔText5, and the count value of the clock that is actually counted during this period is Tcnt4.
In the illustrated example, the reference frequency division value ΔTdiv is shown as a sufficiently small value compared to the period ΔText of the external reference signal Text.

The internal reference signal Tint17 output from the device A is output after the reference frequency division value ΔTdiv is corrected by the correction value ± t (A).
The internal reference signal Tint22 output from the device B is generated and output based on a predetermined reference division value ΔTdiv without being corrected in the first half, and the reference division value ΔTdiv is corrected to a correction value ± t ( Output based on the value corrected by B). That is, in the first half, since the internal reference signal Tint22 of the device B is not corrected, the internal reference signals Tint17 and 22 are not synchronized with each other (24), but in the second half, both the devices A and B have the internal reference signal Tint17. , 22 are corrected, the internal reference signals Tint17, 22 are synchronized with each other (25).

With this configuration, in the first reference example of the present invention, it is possible to maintain high-precision synchronization of the internal reference timing of the apparatus without considering the accuracy of the crystal oscillator. For example, a short period (early) internal reference timing can be generated even if a long period (slow) reference timing such as a GPS reference signal is used.
Even if the external reference signal such as GPS is interrupted, once the crystal oscillator error is detected, synchronization can be maintained for a certain period.

  FIG. 4 is a timing chart showing a state when the external reference signal Text is interrupted. In the figure, when the external reference signal Text is not input to the devices A and B from a certain point in time, the correction values ± t (A) and ± t (B) based on the immediately preceding count are held as they are. The output of the original internal reference signal Tint17, 22 is held. Normally, the output of the internal reference signals Tint17 and 22 is held until the external reference signal Text is next restored and input.

As a result, even when the system equipment is installed in a place with a poor temperature environment, it is not affected by the frequency fluctuations that occur in the crystal oscillator, and the reference signals of each equipment are kept synchronized with high precision. Will be.
Next, a second reference example and a third reference example of the present invention will be described below with reference to FIGS.

FIG. 5 is a diagram schematically showing an example of the configuration of the entire distributed control system to which the second reference example of the present invention or a third reference example to be described later is applied. In the figure, it is assumed that a central apparatus 31 and terminal apparatuses 32, 33, and 34 are installed in a distributed manner to form a distributed control system.
The central device 31 and the terminal devices 32, 33 and 34 are connected to a communication line 35. The central device 31 and the terminal devices 32, 33, and 34 collect various types of grid information of the power grid. Each terminal device 32, 33, 34 transmits the collected system information to the central device 31 via the communication line 35. The central device 31 performs a fault location calculation and various measurement calculations based on the transmitted system information.

The central device 31 and each of the terminal devices 32, 33, and 34 include GPS receivers 31a, 32a, 33a, and 34a, respectively, and use the GPS reference signal obtained by the GPS receiver as an external reference signal, Control is performed and sampling synchronization of the entire distributed control system is achieved.
This will be described in detail below with reference to FIGS.

FIG. 6 is a diagram for explaining phase control in each device constituting the distributed control system.
In the figure, an internal reference timing signal generated / output from an internal reference timing generation frequency dividing counter 48, which will be described later, and a GPS reference signal obtained by the GPS receiver are input to a phase error measurement counter 42, and a clock oscillator (Crystal oscillator) It operates by the clock signal of 41. In the following description, it is assumed that the clock signal is, for example, 50 (MHz) (= 20 ns period).

The phase error measurement counter 42 starts counting with one pulse of the internal reference timing signal and stops counting with one pulse of the GPS reference signal, thereby counting the phase difference Δε between the internal reference timing signal and the GPS reference signal. For example, the count number corresponding to the phase difference Δε shown in FIG.
Then, the phase control is performed so that the timing error between the internal reference timing signal and the GPS reference signal is eliminated (so that the phase difference Δε is zero (0)). In this reference example, the value of the phase difference Δε is set. Accordingly, the phase control of the fine adjustment width (n1) with high accuracy and the phase control of the coarse adjustment width (n2) for speeding up the convergence time can be used to synchronize with high speed and high accuracy. it can.

Here, as shown in the figure, the period of the internal reference timing signal generated / output by the internal reference timing generation frequency dividing counter 48 is determined by the frequency division setting value and the clock frequency of the clock oscillator 41. its basic division setting value, the electrical angle of 30 degrees (30 degrees 1 cycle as 360 degrees; e.g. ΔT ₃₀ = 1.666 ··· (ms at 50 Hz), 60 Hz at _{ΔT 30 = 1.388 ··· (ms)} ) of It is a value (n ₃₀ ) for generating timing. For example, when the clock CLK of the clock oscillator 41 is 50 (MHz) (= 20 ns period), to generate timing with an electrical angle of 30 degrees,
1666.66 (μs) / 20 (ns) ≈83333
Is the basic frequency division set value n ₃₀ .

The frequency division setting value of the internal reference timing generation frequency dividing counter 48 is, as shown in the figure, a value ± n ′ to n ₃₀ output from the basic frequency division setting value output unit 46 by the adder / subtractor 47, that is, , N ₃₀ ± n ′. If the value of n ′ is small, the highly precise fine adjustment width phase control is performed, and if the value of n ′ is large, the coarse adjustment width phase control is performed.
The value of n ′ is determined by the processing unit 43, the N down counter 44, and the processing unit 45. This will be described in detail below.

  First, in the processing unit 43, when the absolute value of the phase difference Δε detected by the phase error measurement counter 42 as described above is larger than a predetermined value β (rough adjustment width control lock management value) ( | Δε |> β), and the combination of the coarse adjustment width (n2) and the fine adjustment width (n1) is the adjustment width for phase control (n = n2 + n1). On the other hand, when the absolute value of the phase difference Δε is equal to or smaller than a predetermined value β (| Δε | ≦ β), the fine adjustment width (n1) is set as the adjustment width of the phase control (n = n1). . Here, it is assumed that n1 is one cycle (20 ns) of the clock CLK and n2 is 16 cycles (320 ns).

Further, the frequency division setting value N of the N down counter 44 is obtained from “N = | Δε | / n”. Here, in the 50 Hz system (system frequency is 50 Hz), the sampling timing of the electrical angle of 30 degrees is 600 cycles, which is the same as the GPS reference signal cycle of 1 second (in the 60 Hz system, it is 720). Therefore, for example, if it is desired to control the timing by 20 (ns) per second, it is only necessary to enable the control of n1 for one cycle out of 600 cycles (in other periods, the electrical angle 30 as described later). Degree fixed period ΔT ₃₀ ). The effective period is determined by the frequency division setting value N.

That is, when the frequency division set value N is set, the N down counter 44 counts down by one for each pulse of the internal reference timing signal, and the count value> 0 is set to “1” from the “TOUT” terminal. 'Output. The control unit 45 assumes that the valid period is in effect while “1” is output from the N down counter 44, and outputs n ′ = n. At this time, the frequency division setting value of the internal reference timing generation frequency dividing counter 48 is n ₃₀ ± n, and phase control of the fine adjustment width or the coarse adjustment width is performed.

On the other hand, when the valid period expires, the N down counter 44 outputs “0”, and the control unit 45 outputs “n” = 0. Thus, the frequency division setting value of the frequency division counter 48 is n ₃₀ . That is, the internal reference timing signal has a fixed period ΔT ₃₀ with an electrical angle of 30 degrees. An example of the internal reference timing signal when the above-described phase control is performed is shown in FIG. 7B, for example. This is because the synchronization control of this reference example performs synchronization determination every second of the GPS reference pulse period and performs synchronization based on this (control of one second period). When performing phase control that is ± (plus / minus) to the fixed period ΔT ₃₀ of 30 degrees, the resolution of the control cannot be ensured unless the effective period of phase control and the fixed period setting period of 30 electrical degrees are mixed. is there.

  Here, for example, in a 50 Hz system, when n1 is set to one cycle (20 ns) of clock CLK and n2 is set to 16 cycles (320 ns) as described above, phase control with fine adjustment control width n1 is performed for 1 second. The phase control with a maximum of 12 μs (20 ns × 600 (cycle)) and the coarse adjustment control width n 2 can control the phase at a maximum of 192 μs (320 ns × 600 (cycle)) per second. Movement control of a maximum of 204 μs becomes possible.

  As described above, in the second reference example of the present invention, when the phase difference Δε is relatively large (| Δε |> β), the coarse adjustment width (n2) and the fine adjustment width (n1) are relatively large. By performing phase control with the control width, the timing error (phase difference Δε) can be converged to zero (set to a synchronized state) as fast as possible. On the other hand, when the phase difference Δε converges to some extent and becomes equal to or less than the predetermined value β (| Δε | ≦ β), the phase control is performed with a relatively small control width based only on the fine adjustment width (n1), and stable and It can be synchronized with high accuracy. In particular, even when the GPS reference pulse fluctuates or cuts off transiently during the control with the fine adjustment width (n1), the error caused by the phase control is 12 μs (± 12 μs) per second at maximum in the above example. Just do it.

  In this reference example, the adder / subtractor 47 allows the phase control direction to be in both the + (plus) direction and the-(minus) direction. For example, when the phase measurement error Δε is larger than a half value of a period of 30 electrical degrees (0.833... Ms in the 50 Hz system), control in the − (minus) direction is performed. FIGS. 7A and 7B show an example in which control in the + (plus) direction is performed.

In the above description, it is assumed that there is no error of the clock oscillator (crystal oscillator) 41. However, when an error of the crystal oscillator occurs, the error correction function of the first reference example is combined. Just do it.
Next, a method of not performing synchronization control (phase control), which is a third reference example of the present invention, will be described below with reference to FIG.

In this method, the above-described phase control is originally performed in order to prevent a calculation error due to a phase shift between the terminal devices in the central device 31, and the result is obtained even if the timing is not synchronized between the devices. In particular, attention is focused on the point that it is sufficient to prevent calculation errors.
In each terminal device 32, 33, 34, the phase difference measurement counter 42 always measures the phase difference Δε while the internal reference timing signal and the GPS reference signal are not synchronized, and this phase difference Δε is The collected sampling data (the system information) is transmitted to the central apparatus 31 via the communication line 35. When the central unit 31 executes the fault location calculation and various measurement calculations as described above based on the sent sampling data, the central unit 31 uses the data of the phase difference Δε to determine the internal reference timing between the terminal units. An error ΔE is calculated.

For example, as shown in FIG. 8, in the terminal devices 32 and 33, the internal reference timing is generated with a fixed period ΔT ₃₀ of an electrical angle of 30 degrees, and the phase difference Δε with respect to the GPS reference signal is Δε _1. , Δε ₂ , the central device 31 determines the error ΔE of the internal reference timing between the terminal device 32 and the terminal device 33 as
ΔE = Δε ₂ −Δε ₁
Calculated by Note that this is not shown in FIG. 8, and the same applies to the terminal devices 32 and 33 and the terminal device 34.

The central device 31 can correct the sampling data in accordance with the error ΔE to perform the fault location calculation and various measurement calculations without causing a calculation error.
In this way, even if timing synchronization control between the devices is not performed, calculation errors can be prevented from occurring in the fault location calculation and various measurement calculations.

Next, a first embodiment of the present invention will be described.
As described above, it is conceivable that the GPS reference signal cannot be obtained for a certain period of time after the apparatus is turned on, or cannot be temporarily obtained due to the installation environment / environment change of the antenna. In the first embodiment, even in such a case, the calculation error can be prevented from occurring.
For example, it is assumed that the GPS reference signal cannot be received for a certain period, and even if a system failure occurs during that period, the error of the internal reference timing between each terminal device when the system failure occurs is estimated In the point location calculation, it is possible to estimate an accurate failure point by preventing calculation errors. Hereinafter, description will be given by taking failure point location as an example.

For the first embodiment will be described with reference to FIG.
In the distributed control system as the failure point locating device, each of the terminal devices 32 to 34 installed in a distributed manner can simultaneously detect the occurrence of a system failure using a change width overcurrent relay or the like. Depending on the distance from the failure occurrence point to each terminal device, a time lag occurs in the failure detection by each device, so if the internal reference timing between each terminal device is synchronized, by using this time lag data as it is, Accurate failure points can be estimated. On the other hand, in a state that can not normally receive the GPS reference signal by some kind of reason, although the internal reference timing between the terminal devices can not synchronize, in the first embodiment, even impossible synchronization, an accurate fault location Can be estimated.

That is, for example, when an accident occurs at the timing shown in FIG. 9 and the occurrence of a system failure is detected in each of the terminal devices 32 to 34 as described above, each terminal device 32 to 34 recovers from the internal reference timing immediately after the occurrence of the accident. Time ΔT (ΔT ₁ , ΔT _2, etc .; two of the three terminal devices are shown as an example in FIG. 8) is measured until the GPS reference signal is reached. Each terminal device has an internal reference timing signal of a fixed period ΔT ₃₀ with an electrical angle of 30 degrees, and from the time of the occurrence of the system failure detection to the time of GPS restoration (until the GPS reference signal can be normally received), The number of pulses (M) of the internal reference timing signal is counted, and a phase difference Δε between the GPS reference signal at the time of GPS restoration and the internal reference timing signal immediately before is detected. Then, ΔT ₁ and ΔT ₂ are
ΔT ₃₀ × M (cycle) + phase difference Δε
Calculated by For example, in the example shown in FIG.
ΔT ₁ = ΔT ₃₀ × M ₁ + Δε ₃
ΔT ₂ = ΔT ₃₀ × M ₂ + Δε ₄
It becomes.

Then, each terminal device notifies the central device 31 of the calculated ΔT.
The central device 31 calculates an internal reference timing error ΔE between the terminal devices at the time of an accident as shown in FIG. 9, for example, by ΔE = ΔT ₂ −ΔT ₁ . In this way, by calculating the timing error ΔE between the terminal devices, as in the method described with reference to FIG. 8, the sampling data is corrected in accordance with the error ΔE, so that a correct failure point can be obtained without causing an arithmetic error. The orientation calculation result can be obtained.

In the first embodiment described above, it is necessary to wait until the GPS reference signal is restored . In the fourth reference example, which is a modification of the first embodiment described below, wait until the GPS reference signal is restored. It can respond without any problems. In the fourth reference example , in such a case, the central device 31 notifies each terminal device 32 to 34 of a simultaneous broadcast trigger. Hereinafter, a detailed description will be given with reference to FIGS. 10 and 11.
In the fourth reference example , the simultaneous broadcast trigger is notified as described above, but a transmission delay difference occurs depending on the length of the transmission path between the central device 31 and each terminal device. For this reason, the transmission time delay time is obtained by measuring the time until the test data is transmitted from the central device 31 to each terminal device and the response from each terminal device to the test data is received in advance. deep. For example, in the example shown in FIG. 10, the transmission distance between the central device 31 and the terminal device 32 is L ₁ , the transmission distance between the central device 31 and the terminal device 33 is L ₂ , and the transmission distance between the central device 31 and the terminal device 34 is L ₃ is a thing and then, respectively transmit the test data (test frame) to each terminal device from the central unit 31, the time to receive a response (response frame) to be returned immediately from the respective terminal devices with respect to the test data And Δt ₁ , Δt ₂ , and Δt ₃ , respectively. In this case, each transmission path delay _{time, Δt 1/2, Δt 2} /2, obtained as Delta] t _3/2. And the central apparatus 31 notifies each transmission line delay time to each terminal device 32-34.

In this way, when the central device 31 notifies the terminal devices 32 to 34 of the simultaneous broadcast trigger in a state where the GPS reference signal cannot be received, for example, as shown in FIG. The broadcast trigger is received with a delay of Δt _1/2 from the timing at which the device 31 transmits the broadcast trigger (reference trigger transmission timing). Terminal device 33, and from the reference trigger transmission timing by the central unit 31 Δt _2/2 delay, to receive the broadcast trigger.

Each terminal device 32, 33, when the difference between its own internal reference timing at the time of receiving the simultaneous broadcast trigger and its immediately preceding internal reference timing is Δε ₅ , Δε ₆ , respectively, The differences ΔX ₁ and ΔX ₂ are obtained by the following equations.
_{ΔX 1 = Δt 1/2 -Δε} 5 -Y 1
_{ΔX 2 = Δt 2/2 -Δε} 6 -Y 2
(Here, Y ₁ and Y ₂ are obtained by taking Y ₁ as an example.
First, y ₁ = (Δt ₁ / 2−Δε ₅ ) / ΔT ₃₀ (rounded down to the nearest decimal point; integer) is obtained, and then Y ₁ = y ₁ × ΔT ₃₀ is obtained. Y ₂ is obtained in the same manner.

For example, in the example of FIG. 11, assuming that y ₁ is a value of about 2.7 by eye measurement, y ₁ = 2 is obtained by rounding off the decimal point. Similarly, y ₂ = 4. Therefore, in this example, Y ₁ = 2 × ΔT ₃₀ and Y ₂ = 4 × ΔT _30.
Accordingly, the central device 31 can obtain the internal reference timing error ΔE between the terminal devices by sending the data of ΔX together with the collected data (the system information and the like) from each terminal device. For example, the internal reference timing error ΔE between the terminal devices 32-33 can be obtained as ΔE = ΔX ₁ −ΔX ₂ .

Therefore, as in the first embodiment described above, even if the internal reference timing between the terminal devices is not synchronized, the central device 31 corrects the collected data (system information, etc.) using the timing error ΔE. Thus, fault location calculation and the like can be performed without causing a calculation error.
The fourth reference example is basically a so-called “one pair” in which a central device 31 is connected to each of the terminal devices 32 to 34 via a one-to-one transmission path as shown in FIG. N transmission form ". However, the physical configuration may be an N-to-N transmission form such as a LAN. Any communication line dedicated to this system may be used. In other words, it is not necessary to have a configuration in which other systems are mixed and the transmission delay time varies due to transmission of other systems.

In addition, the trigger is not limited to the one transmitted by simultaneous broadcast. For example, even if the central device 31 sequentially transmits triggers to the terminal devices 32 to 34, it is only necessary to detect a difference between the internal reference timing of each terminal device and the reference trigger transmission timing.
Here, if the second method is used, a trigger from the central device 31 can be generated at an arbitrary timing. For example, a trigger can be generated manually. Can be done easily. This is possible even during execution of the synchronous control based on the phase control described above, for example.

This will be described below.
The system configuration is a so-called “1-to-N transmission configuration” system in which a central device 31 is connected to each of the terminal devices 32 to 34 through a one-to-one transmission path as shown in FIG. In this system, for example, as described with reference to FIG. 10, the test data (test frame) is transmitted from the central device 31 to each terminal device, and the response (response frame) from each terminal device to the test data is received. time to _{(Δt 1, Δt 2, Δt} 3) by measuring the respective transmission path delay time _{(Δt 1/2, Δt 2} /2, Δt 3/2) Request. Each terminal device shall immediately return a response frame upon receipt of a test frame (if precision is required, each terminal device may measure in advance the time taken from test frame reception to response frame transmission. This is registered on the central device 31 side and corrected).

For example, the central device 31 transmits a synchronization reference frame to the terminal devices 32 to 34 by simultaneous broadcast communication at regular intervals or according to an operation of an operator or the like. Hereinafter, a description will be given with reference to an example shown in FIG.
In the example shown in FIG. 13, as shown in FIG. 13, the internal reference timing of each of the central device 31 and each of the terminal devices 32 to 34 is synchronized with the GPS reference signal. It is assumed that it is misaligned. As described above, an accurate GPS reference timing can be obtained when the GPS antenna is installed, when the surrounding environment changes, or when there is an error in the GPS receiver settings. This is because it is considered that there is a slight timing shift depending on each device even if it is not.

When the central device 31 transmits the synchronization reference frame by the broadcast communication, the central device 31 measures the time ΔZ ₁ from the internal reference timing synchronized with its own GPS reference signal to the synchronization reference frame. Each of the terminal devices 32 to 34 measures the time ΔZ ₂ , ΔZ ₃ , ΔZ ₄ from the internal reference timing synchronized with its own GPS reference signal to the reception of the synchronization reference frame, and transmits this to the central device 31.

The central unit 31 includes a data of ΔZ ₁ ~ΔZ _4, each transmission path delay time _{(Δt 1/2, Δt 2} /2, Δt 3/2) based on the data, each device 31 to 34 The synchronization management times Tsync1 to Tsync4 are calculated as follows.
Central unit 31; Tsync1 = ΔZ ₁
Terminal _{32; Tsync2 = ΔZ 2 -Δt 1} /2
Terminal _{33; Tsync3 = ΔZ 3 -Δt 2} /2
Terminal _{34; Tsync4 = ΔZ 4 -Δt 3} /2
(Here, if synchronization between all devices is established,
Tsync1 = Tsync2 = Tsync3 = Tsync4
It becomes. )
The central device 31 obtains a timing error ε _nm (brute force) between the devices according to the following equation, and determines that the device is out of synchronization if it is above a certain reference value. Then, for example, an alarm is sounded and the device name / device number of the device with poor synchronization is displayed.

ε _nm = | Tsync n−Tsync m |
(N; 1-4, m; 1-4)
For example, in FIG. 13, as an example, the timing error ε ₁₂ between the central device 31 and the terminal device 32, the timing error ε ₂₃ between the terminal device 32 and the terminal device 33, and the timing error ε between the terminal device 33 and the terminal device 34. ₃₄ are shown.
ε ₁₂ = | Tsync1-Tsync2 |
ε ₂₃ = | Tsync2-Tsync3 |
ε ₃₄ = | Tsync3-Tsync4 |
Is calculated by

  In this way, for example, by performing the above-described timing synchronization test / evaluation process periodically (or at any time), it is possible to automatically detect a device (defective terminal) having a defect in the GPS reference signal. . If a defective terminal can be identified, it is possible to quickly perform a treatment such as repair of the defective terminal. It is also conceivable to perform processing only with the remaining normal terminals.

It is the block diagram which showed notionally the structure of the 1st reference example of this invention. It is a figure which shows the whole system in which the structure shown by FIG. 1 is included. 3 is a timing chart showing the relationship between an external reference signal and an internal reference signal in FIG. It is a timing chart which shows a mode when an external reference signal stops. It is a figure which shows roughly an example of a structure of the whole distributed control system of a 2nd reference example and a 3rd reference example . It is a figure for demonstrating the phase control in each apparatus which comprises the distributed control system of FIG. It is a figure which shows an example of the internal reference timing signal which performed phase control by the structure of FIG. It is a figure for demonstrating the method which does not perform synchronous control (phase control). It is a figure for demonstrating the 1st Example. It is a figure for demonstrating transmission line delay time calculation in the 4th reference example . It is a figure for demonstrating the 4th reference example . It is a figure which shows roughly an example of a structure of the whole distributed control system to which a 4th reference example is applied. It is a figure for demonstrating a timing synchronous test and evaluation method.

Explanation of symbols

1 External reference signal 2 Crystal oscillator 3 Measurement counter
10 Internal reference timing generation counter
13 External reference signal
14 A equipment
15 Synchronous frequency divider
16 Alarm
17 Internal reference signal
18 Crystal oscillator
19 B equipment
20 Synchronous frequency divider
21 Alarm
22 Internal reference signal
23 Crystal oscillator
27 Adder
31 Central unit
32 Terminal equipment
32a GPS receiver
33 Terminal equipment
33a GPS receiver
34 Terminal equipment
34a GPS receiver
35 Communication line
41 clock oscillator
42 Phase error measurement counter
43 Processing section
44 N down counter
45 Processing section
46 Electric angle 30 degree fixed frequency division setting part
47 Addition / subtraction part
48 Dividing counter for generating internal reference timing

Claims (2)

In a distributed control system in which a central device and each terminal device installed in a distributed manner are connected by a transmission line,
Each terminal device detects an internal reference signal generating means for generating an internal reference signal, an external reference signal input means for inputting an external reference signal, and a phase difference between the input external reference signal and the internal reference signal. immediately before a phase difference detecting means, and failure detecting means for detecting a system fault occurs, in which the external reference signal from the sampling timing of the internal reference signal immediately after detecting a system fault occurrence by the front Symbol failure detecting means is first input It said measuring means for measuring a time until the sampling timing, and communication means for transmitting the time ΔT obtained by the sum of the phase difference detected by the measuring data and the phase difference detecting means by said measuring unit to the central unit Prepared,
Based on the time ΔT sent from each terminal device, the central device estimates the relative deviation of the internal reference signal between the terminal devices when a system failure occurs, and performs correction using the deviation. A distributed control system comprising failure point locating means for locating failure points. The distributed control system according to claim 1, wherein a reference signal obtained from GPS is an external reference signal.