CN105102991B

CN105102991B - Signal processing apparatus

Info

Publication number: CN105102991B
Application number: CN201380075156.XA
Authority: CN
Inventors: 伊户靖则
Original assignee: Mitsubishi Electric Corp
Current assignee: Mitsubishi Electric Corp
Priority date: 2013-03-29
Filing date: 2013-03-29
Publication date: 2017-12-08
Anticipated expiration: 2033-03-29
Also published as: GB201517671D0; CN105102991A; KR20150134405A; JPWO2014155706A1; GB2527007B; GB2527007A; HK1212777A1; JP5972450B2; WO2014155706A1; KR101795199B1

Abstract

1PPS signal receiving parts (101) receive 1PPS signals, clock generation unit (102) generates clock signal, clock jitter determination part (103) determines clock jitter, and the clock jitter is frequency departure of the clock signal relative to 1PPS signals.Deviation measuring value maintaining part (301) is kept by the multiple measure of clock jitter determination part multiple clock jitter measured values for obtaining.Newest clock jitter measured value in multiple clock jitter measured values that clock jitter value generating unit (302) is kept to deviation measuring value maintaining part (301) is compared with other clock jitter measured values, in the case where newest clock jitter measured value is consistent with other clock jitter measured values, newest clock jitter measured value is exported to sampling period count section (105), in the case where newest clock jitter measured value and other clock jitter measured values are inconsistent, arbitrary clock jitter measured value in other clock jitter measured values is exported to sampling period count section (105).

Description

Signal processing apparatus

Technical field

The present invention relates to timing synchronization control technology, more particularly to collect in the device of electrical quantity of power transmission line or bus Timing synchronization control technology.

Background technology

With Protection control system as follows, the Protection control system collects power transmission line or bus in multiple opening positions Electrical quantity (magnitude of voltage, current value), when detecting abnormal according to these electrical quantity, cutting system, suppresses accident immediately Involve.

In the Protection control system, in order to reduce the phase deviation for the electrical quantity being collected into, it is necessary to place will collected Between obtain the benchmark that synchronous signal is collected as electrical quantity.

In protective relay device in recent years, for 1 arithmetic unit (hereinafter also referred to as IED：Intelligent Electronic Device：Intelligent electronic device) via LAN (process bus) connect multiple transacters (it is following, Also referred to as MU：Merging Unit：Combining unit).

Each MU is according to synchronizing signal (1PPS signals：1Pulse Per Second signals), Timing Synchronization is obtained, thus Make between MU data sampling timing or timestamp value it is consistent.

Prior art literature

Patent document

Patent document 1：Japanese Unexamined Patent Publication 2001-305177 publications

The content of the invention

The invention problem to be solved

The reception cycle of 1PPS signals is to be spaced for 1 second.

Therefore, each MU needs to carry high-precision quartz oscillator (frequency departure on clock generation circuit：± a few ppm), To generate the small high precision clock of frequency departure, between the suppression of the deviation of the sampling timing between MU is formed in 1 second deviation for ± it is several micro- Below second.

Accordingly, there exist can not use cheap general oscillating circuit (the frequency departure essence that is generally used in digital circuit Degree ± 50ppm or so) and cause the increased problem of cost.

The present invention completes to solve above-mentioned such problem, and its main purpose is to be even with frequency departure ± 50ppm or so general oscillating circuit, it can also carry out high-precision Synchronization Control.

The means used to solve the problem

The signal processing apparatus of the present invention is characterised by possessing：1PPS signal receiving parts, it receives 1PPS signals, its In, 1PPS represents pulse per second (PPS)；Clock generation unit, it generates the clock signal of the clock cycle smaller than 1 second；Clock jitter determines Portion, it inputs above-mentioned 1PPS signals from above-mentioned 1PPS signal receiving parts, inputs above-mentioned clock signal from above-mentioned clock generation unit, often When inputting above-mentioned 1PPS signals, clock jitter is determined, the clock jitter is above-mentioned clock signal relative to above-mentioned 1PPS signals Frequency departure；Deviation measuring value maintaining part, it keeps obtaining by multiple measure in above-mentioned clock jitter determination part Multiple clock jitter measured values；And deviation measuring value selector, it is kept above-mentioned to above-mentioned deviation measuring value maintaining part Newest clock jitter measured value in multiple clock jitter measured values is compared with other clock jitter measured values, above-mentioned , will be above-mentioned newest when newest clock jitter measured value and other clock jitter measured values consistent in defined permissible range Clock jitter measured value is output to output destination, in above-mentioned newest clock jitter measured value and other clock jitter measured values When inconsistent in above-mentioned permissible range, any clock jitter measured value in above-mentioned other clock jitter measured values is output to Above-mentioned output destination.

Invention effect

According to the present invention, because inclined using the clock between the clock signal and 1PPS signals of the clock cycle smaller than 1 second Difference, so even with the general oscillating circuit that frequency departure is ± 50ppm or so, it can also carry out high-precision synchronous control System.

In addition, multiple clock jitter measured values are kept, when newest clock jitter measured value and other clock jitter measured values When inconsistent, other clock jitter measured values rather than newest clock jitter measured value are selected, so even in 1PPS signals When producing abnormal in reception, the exception will not also feed through to the generation of sampled signal.

Brief description of the drawings

Fig. 1 is the figure of the configuration example for the transacter for showing embodiment 1.

Fig. 2 is the figure of the action example for the transacter for showing embodiment 1.

Fig. 3 is the figure of the configuration example for the transacter for showing embodiment 2.

Fig. 4 is the figure of the action example for the transacter for showing embodiment 2.

Fig. 5 is the figure of the structure of the premise for the transacter for being shown as embodiment 1,2.

Fig. 6 is the figure of the operating principle for the transacter for illustrating embodiment 1,2.

Fig. 7 is the figure of the operating principle for the transacter for illustrating embodiment 1,2.

Fig. 8 is the figure of the operating principle for the transacter for illustrating embodiment 1,2.

Fig. 9 is the figure of the hardware configuration example for the transacter for showing embodiment 1 and 2.

Embodiment

Embodiment 1.

In the present embodiment, transacter (MU) is illustrated, it is calculated according to clock jitter measured value Determine the corrected value of the counter (sampled signal generation counter) in the cycle sampled to electrical quantity.

Thus, even with the general oscillating circuit that frequency departure is ± 50ppm or so, can also obtain high-precision same Step.

In addition, the transacter of present embodiment keeps multiple clock jitter measured values, when newest clock jitter When measured value is consistent with previous clock jitter measured value, newest clock jitter measured value is selected, when inconsistent, before selection One clock jitter measured value, rather than newest clock jitter measured value.

Therefore, when generation 1PPS signal interruptions etc. are abnormal, the abnormal generation that will not also feed through to sampled signal.

Fig. 1 shows the configuration example of the transacter 100 of present embodiment.

Example of the transacter 100 equivalent to signal processing apparatus.

Being mainly characterized by for the transacter 100 of present embodiment, possesses：Deviation measuring value maintaining part 301, it is protected Hold multiple clock jitter measured values；And clock jitter value generating unit 302, it is kept from deviation measuring value maintaining part 301 In multiple clock jitter measured values, the clock jitter measured value of the output of sampling period count section 105 to rear class is selected.

In view of readily appreciating, first, using not comprising deviation measuring value maintaining part 301 and clock jitter value generating unit The transacter of 302 structure, to illustrate the operating principle of the transacter 100 of present embodiment.

Fig. 5 is to show to remove deviation measuring value maintaining part 301 from the transacter 100 of present embodiment with timely The structure of transacter 150 after clock deviation generating unit 302.

Transacter 150 receives 1PPS signals, in addition, the data for representing determined electrical quantity are sent into computing Device 200.

Arithmetic unit 200 as IED detects the exception of power system, cutting system, thus, suppresses involving for accident.

The transmission source of 1PPS signals can be arithmetic unit 200 or have GPS (Global Positioning System) other devices of receiver.

In transacter 150,1PPS signal receiving parts 101 receive 1PPS signals.

Clock generation unit 102 generates the Action clock signal (hreinafter referred to as clock signal) of transacter 150.

The clock cycle of clock signal is smaller than 1 second.

Clock jitter determination part 103 determines clock jitter, and the clock jitter is the clock signal phase of transacter 150 For the frequency departure in the cycle of 1PPS signals.

Deviation measuring value maintaining part 104 keeps the clock jitter measured value that clock jitter determination part 103 is determined.

Deviation measuring value maintaining part 104 is different from Fig. 1 deviation measuring value maintaining part 301, only keeps 1 clock jitter to survey Definite value.

Sampling period count section 105 is counted to the time interval of timing, and this is regularly sampled to electrical quantity Regularly.

Sampling period count section 105 inputs 1PPS signals from 1PPS signal receiving parts 101, is inputted from clock generation unit 102 Clock signal, start in the input of 1PPS signals it is corresponding with the clock cycle of clock signal count, when complete by counting During counting untill end value, start the counting from being counted initial value.

In addition, example of the sampling period count section 105 equivalent to counter.

Sampled signal generating unit 106 is according to the count value of sampling period count section 105, the pulse of generation expression sampling timing That is sample clock signal (also referred to as sampled signal).

The timing for the pulse (sampled signal) that electrical quantity determination part 107 is generated in sampled signal generating unit 106, measure electricity The electrical quantity of Force system.

The electrical quantity that electrical quantity determination part 107 is determined is converted to and LAN (process can be transmitted by data generating section 108 Bus (process bus)) communication frame form numerical data.

The numerical data that data generating section 108 is generated is sent to fortune by communication unit 109 via LAN (process bus) Calculate device 200.

Then, the action example of transacter 150 is illustrated.

Delivery unit as fiber optic cables or Electrical signal cable is used in transacter 150 from arithmetic unit 200 input 1PPS signals.

1PPS signals are the pulse signals in the cycle of 1 second for representing the absolute moment, and circular error is several below ppm, very It is small.

1PPS signals are received using 1PPS signal receiving parts 101, are published to clock jitter determination part 103 and sampling period meter Several 105.

In clock generation unit 102, the clock signal of transacter 150 is generated, is published to clock jitter determination part 103 and sampling period count section 105.

In clock jitter determination part 103, timing and the clock letter with transacter 150 are received to 1PPS signals The deviation i.e. clock jitter between 1 second number counted is measured, and measurement knot is kept in deviation measuring value maintaining part 104 Fruit.

Sampling period count section 105 be the clock signal that is generated based on clock generation unit 102 carry out incremental count or The counter of countdown.

Here, the higher limit (counting end value) for generating the count value in sampling period is according to deviation measuring value maintaining part 104 clock jitter measured values kept and determined in a manner of consistent with the precision of 1PPS signals.

For example, power system a-c cycle be 50Hz, every 1 ac cycle sampling number be 80 times when, sampling week Phase is 250 microseconds.

In the case where the precision of 1PPS signals is 0ppm, in 80MHz counters, 250 microseconds and the counting of 20000 times Unanimously.

Here, in the case where the frequency departure of clock signal is -50ppm, the counting of 20000 times is micro- as 250.0125 Second, the sampling period extended for 12.5 nanoseconds.

Therefore, in the case where the clock jitter measured value that deviation measuring value maintaining part 104 is kept is -50ppm, make The count upper-limit value of 80MHz counters turns into 19999 times, thus makes the time width and 250 microseconds (0ppm feelings in sampling period Time width under condition) it is consistent.

The count value that sampled signal generating unit 106 is generated using sampling period count section 105, generate and electrical quantity is determined The sample clock signal that portion 107 provides.

Electrical quantity determination part 107 measures electricity in the reception for the sample clock signal that sampled signal generating unit 106 is generated The electrical quantity (electric current, voltage) of Force system.

The electrical quantity that sampled signal generating unit 106 is determined is sent to arithmetic unit 200 by data generating section 108, therefore Form the form for the communication frame that communication unit 109 can be utilized to be transmitted.

The communication frame that data generating section 108 is generated is sent to arithmetic unit 200 by communication unit 109.

Then, clock jitter determination part 103, deviation measuring value maintaining part 104, sampling period count section are illustrated using Fig. 6 105 action.

As starting point, using clock signal as counting source when clock jitter determination part 103 proceeds by the reception using 1PPS signals 10 millisecond period pulses generation.

Reach 99 stage, clock in the value for 10 milliseconds of step-by-step countings that incremental count is carried out using 10 millisecond period pulses The clock jitter that deviation measuring portion 103 is proceeded by using clock signal as counting source determines the counting of counter.

After counting starts, when receiving 1PPS signals, clock jitter determination part 103 stops clock jitter measure and counted The counting of device.

10 milliseconds of preferable count value (clock jitter is subtracted in count value that can be by determining counter from clock jitter Count value during 0ppm), it is (such as suitable to obtain the frequency deviation of clock accumulation of the clock signal of 1PPS signal reception periods In the time of the rectangle of Fig. 6 label 500).

The deviation accumulation that is obtained by clock jitter determination part 103 is kept in deviation measuring value maintaining part 104, and (clock is inclined Poor measured value).

The action of clock jitter determination part 103 is described in more detail using Fig. 7.

When 1PPS signals are input into clock jitter determination part 103, counted according to the clock cycle of clock signal 10 milliseconds of counter acted.

For example, in the case where clock signal is 80MHz, turn into 12.5 nanosecond unit counting, so, in 800000 meters Turn into 10 milliseconds during number.

When 10 milliseconds of the counting is the 99th time, counted if counter turns into 800000, in transacter Turn into 1 second in the measurement of 150 clock signal.

1 second counted according to the clock signal and the difference for receiving timing of 1PPS signals turn into the measure of clock jitter Value.

In the figure 7, because have received 1PPS signals at the time of 10 milliseconds of counter carries out 798400 counting, Clock signal postponed 20 microseconds (nanosecond of (800000-798400) × 12.5) and counted in 1 second, and this value is clock jitter Measured value.

In such action, it is inclined relative to every 1 second of 1PPS signals that clock jitter determination part 103 determines clock signal It is clock jitter from the time, the store clock deviation measuring value in deviation measuring value maintaining part 104.

When the counting of 1 second based on clock signal postpones 20 microsecond compared with 1PPS signals, as shown in figure 8, sampling letter Number only exported in 1 second 3999 times, sampled signal can not be exported in the cycle of 250 microseconds.

Therefore, in order to carry out 20 microseconds correction, it is necessary to change the higher limit (counting end value) of sample period counter.

Sampling period count section 105 is built-in with sampled signal generation counter as shown in Figure 6.

Deviation accumulation (the clock of 1 second that sampling period count section 105 is kept according to deviation measuring value maintaining part 104 Deviation measuring value) calculate the deviation accumulation (clock jitter measured value) in each sampling period.

For example, when the sampling period is as described above 250 microsecond, sampled signal generation counter carried out 4000 in 1 second Secondary sampling, so, remove the deviation accumulation of 1 second (clock jitter measured value) that deviation measuring value maintaining part 104 is kept With 4000, the deviation accumulation (clock jitter measured value) in each sampling period is obtained.

The ideal value (count value during clock jitter 0ppm) that sampling period count section 105 counts from the sampling period add or Calculated deviation accumulation is subtracted, this value is set as to the higher limit (counting end value) of sampled signal generation counter.

In figure 6, label 600 represents the higher limit of sampled signal generation counter.

Sampled signal generating unit 106 monitors the count value of sampled signal generation counter, and turning into 0 in count value, (counting is opened Initial value) timing, the activation sample clock signal relative with electrical quantity determination part 107.

In addition, label 600 can be different values according to each sampling.In the deviation accumulation of 1 second, (clock jitter was surveyed Definite value) situation of sampling number can not be eliminated or less than 1 in the case of, according to it is each sampling change sampled signal generation counter Higher limit, thus, carry out trickle adjustment.For example, in 1 sampling of 3 samplings, the value of label 600 is set to preferable It is worth (count value during clock jitter 0ppm), in 2 samplings, is set to smaller than ideal value 2 value.In the case, adopted at 3 times The adjustment of 4 clocks can be carried out in sample, every 1 sampling carries out the adjustment of 1.33 clocks.

So, the transacter 150 shown in Fig. 5 determines departure of the clock signal relative to 1PPS signals, uses Measurement result determines the count upper-limit value of sampling period count section 105, thus, make the time width in sampling period with it is preferable when Between width (time width in the case of 0ppm) it is consistent.

Then, illustrate following situation, when producing the reception exception that the input of 1PPS signals is temporarily interrupted, utilize Fig. 1's Transacter 100 can avoid the feelings in generation sampling period wrong caused by the clock jitter measured value of mistake Condition.

The difference of Fig. 1 structure and Fig. 5 structure is to be configured in Fig. 1 instead of deviation measuring value maintaining part 104 inclined Poor measured value maintaining part 301, in addition, having added clock jitter value generating unit 302.

In addition to deviation measuring value maintaining part 301 and clock jitter value generating unit 302, with the content phase shown in Fig. 5 Together.

Deviation measuring value maintaining part 301 keeps multiple clock jitter measured values measured by clock jitter determination part 103.

That is, deviation measuring value maintaining part 301 is kept multiple and what is obtained by the multiple measure of clock jitter determination part 103 Clock jitter measured value.

Clock jitter value generating unit 302 is compared to multiple clock jitter measured values of deviation measuring value maintaining part 301, Selection is surveyed to the clock jitter exported as the sampling period count section 105 of output destination from multiple clock jitter measured values Definite value.

Example of the clock jitter value generating unit 302 equivalent to deviation measuring value selector.

Then, the action example of transacter 100 is illustrated using Fig. 2.

Deviation measuring value maintaining part 301 has multiple maintaining parts (storage region), and newest clock is stored in maintaining part 1 Deviation measuring value, in maintaining part 2 store one before clock jitter measured value, in maintaining part 3 store 2 before when Clock deviation measuring value.

Clock signal will change relative to the departure of 1PPS signals according to the environment such as diurnal temperature difference because, But changed within the short time as several seconds.

Therefore, 3 clock jitter measured values in deviation measuring value maintaining part 301 should be consistent.

Clock jitter value generating unit 302 is compared to multiple clock jitter measured values of deviation measuring value maintaining part 301, In the case where newest clock jitter measured value is consistent with other clock jitter measured values, it is determined as that newest clock jitter is surveyed Definite value is normal, selects value of the newest clock jitter measured value as output to sampling period count section 105.

In the case where newest clock jitter measured value and other clock jitter measured values are inconsistent, the life of clock jitter value It is judged as the exception such as producing 1PPS signal interruptions into portion 302, without the renewal of clock jitter measured value, but maintains to work as Preceding value.

That is, clock jitter value generating unit 302 selects the clock jitter measured value that is kept of maintaining part 2, as output to adopting The value in sample cycle count portion 105.

Then, clock jitter value generating unit 302 exports selected clock jitter measured value to sampling period count section 105。

Thus, in the case of producing exception in the reception of 1PPS signals, it can also prevent exception from being given birth to sampled signal Influenceed into bringing.

In addition, in Fig. 1 and Fig. 2, the situation that the maintaining part in deviation measuring value maintaining part 301 is 3 is illustrated, but It can also be the arbitrary value of more than 2.

More than in addition, the newest clock jitter measured value and other clocks only in deviation measuring value maintaining part 301 are inclined When poor measured value is completely the same, newest clock jitter measured value is exported to sampling period count section 105.

On the other hand, defined permissible range can also be set, in newest clock jitter measured value in permissible range When consistent with other clock jitter measured values, newest clock jitter measured value is exported to sampling period count section 105.

Embodiment 2.

Following such situation is illustrated in embodiment 1 more than, measure clock signal is relative to 1PPS signals Departure, the count upper-limit value of sampling period count section is determined using measurement result, thus, make the time width in sampling period It is consistent with ideal time width (time width in the case of 0ppm).

In addition, embodiment 1 prevents the clock jitter based on mistake when showing and having abnormal in the reception of 1PPS signals The example of the generation of measured value sampled signal.

Present embodiment shows the situation of 1PPS signals long-time interruption or after the power on of transacter In the case of receiving 1PPS signals first, make the generation starting position of sample clock signal and the reception timing of 1PPS signals corresponding Mode.

In figure 3, sampling location adjustment portion 501 generates correction of timing amount, and the correction of timing amount is used to give birth to sampled signal The generation starting position of the sample clock signal generated into portion 106 receives regularly corresponding with 1PPS signals.

More specifically, the monitoring of sampling location adjustment portion 501 is input to the defeated of the 1PPS signals of sampling period count section 105 Enter the timing of the counting initial value in timing and sampling period count section 105.

Then, in the case where the timing of counting initial value and the incoming timing of 1PPS signals are inconsistent, sampling location is adjusted Whole 501 calculate for making the timing of the counting initial value correction of timing value consistent with the incoming timing of 1PPS signals.

Then, sampling period count section 105 changes meter using the correction of timing value calculated by sampling location adjustment portion 501 Number higher limit (counting end value), makes the timing of counting initial value consistent with the incoming timing of 1PPS signals.

In addition, example of the sampling location adjustment portion 501 equivalent to correction of timing value calculating part.

In addition, the key element beyond sampling location adjustment portion 501 is same as shown in Figure 1.

Then, the action example of the transacter 100 of present embodiment is illustrated using Fig. 4.

In order that sampling timing is consistent between multiple transacters, except the time width in sampling period it is consistent it Outside, it is also necessary to which the starting position of sample clock signal is consistent with the reception timing of 1PPS signals.

Therefore, in the formula of higher limit of sampled signal generation counter is determined, except making the time in sampling period wide Outside (2) that degree is accordingly set with clock jitter measured value, it is also necessary to for making the generation timing of sample clock signal (3) of skew.

Counter upper limit value=(1) counter reference value (cycle count value during 0ppm) ± (2) clock jitter value ± (3) Correction of timing amount

Received first after 1PPS the signals for a long time situation of interruption or the power in transacter In the case of 1PPS signals, synchronism deviation amount in Fig. 4 is deposited (between sample clock signal position and 1PPS signal receiving positions Deviation), the synchronism deviation amount turns into the value different according to transacter.

The count value of sampled signal generation counter when sampling location adjustment portion 501 receives according to 1PPS calculates synchronization Departure.

Then, sampling location adjustment portion 501 using the synchronism deviation amount calculated as correction of timing amount to the sampling period count Portion 105 exports.

The decision formula that sampling period count section 105 can generate counter upper limit value according to above-mentioned sampled signal counts to change Device higher limit, thus, synchronism deviation amount is adjusted to 0.

The count value of sampled signal generation counter when sampling location adjustment portion 501 receives according to 1PPS signals, to determine Set the tone whole sample clock signal direction, above-mentioned (3) correction of timing amount is added or subtracted each other.

In Fig. 4,1PPS signals reception timing be sampled signal generation counter median after and counter In the case of before higher limit (Fig. 4 (1)), sampling location adjustment portion 501 from counter upper limit value by subtracting correction of timing Amount, sample clock signal is set to be received with 1PPS signals regularly consistent.

In addition, the reception timing in 1PPS signals is before sampled signal generates the median of counter and counter starts In the case of after value (Fig. 4 (2)), sampling location adjustment portion 501 by making correction of timing amount be added with counter upper limit value, Sample clock signal is set to be received with 1PPS signals regularly consistent.

In addition, the adjustment of above-mentioned (3) correction of timing amount may not be progress 1 time, and it is divided into repeatedly carrying out.

For example, when it is desirable that synchronism deviation in the case that the change at sample clock signal interval was limited to below 75 nanoseconds When amount is 750ns, the adjustment amount of 1 time can be made turn into maximum 75ns (amount of 4 countings in 80MHz counters), carried out 10 times The adjustment of counter upper limit value.

In addition, each adjustment amount can differ.

So, according to present embodiment, situation about being interrupted for a long time in 1PPS signals or the power supply in transacter In the case of receiving 1PPS signals first after connecting, generation starting position and the 1PPS signals of sample clock signal can be made It is corresponding to receive timing.

In addition, illustrate what sampling period count section 105 was incrementally counted in embodiment 1 and 2 Example, therefore, the lower limit that initial value is sampling period count section 105 is counted, it is higher limit to count end value.

In the case where sampling period count section 105 is counted in a manner of successively decreasing, counting initial value turns into sampling week The higher limit of phase count section 105, counting end value turns into lower limit.

Finally, reference picture 9 illustrates the hardware configuration example of the transacter 100 shown in embodiment 1,2.

Transacter 100 is computer, and each key element of transacter 100 can be realized using program.

As the hardware configuration of transacter 100, control device 901, external memory are connected in bus 902nd, main storage means 903, communicator 904, input/output unit 905, clock generation circuit 906, counter 907.

Control device 901 is the CPU of configuration processor.

External memory 902 is, for example, ROM (Read Only Memory：Read-only storage) or flash memory, hard disk unit.

Main storage means 903 are RAM (Random Access Memory：Random access memory).

Deviation measuring value maintaining part 301 can for example be realized by main storage means 903.

Communicator 904 is corresponding with the physical layer of 1PPS signal receiving parts 101 and communication unit 109.

Input/output unit 905 is, for example, mouse, keyboard, display equipment etc..

Clock generation circuit 906 possesses quartz (controlled) oscillator, generates the clock signal of transacter 100.

Clock generation unit 102 is realized by clock generation circuit 906.

In addition, sampling period count section 105 is realized by counter 907.

Program is generally stored inside in external memory 902, in the state of being loaded into main storage means 903, successively Controlled device 901 reads in and performed.

Program is realized as "~the portion " shown in Fig. 1, Fig. 3 (wherein, except clock generation unit 102, deviation measuring value are protected It is hold outside portion 301, below and same) program of function that illustrates.

Moreover, being also stored with operating system (OS) in external memory 902, OS at least a portion is loaded into main memory In storage device 903, control device 901 performs OS, and performs the program for the function of realizing "~portion " shown in Fig. 1.

In addition, in the explanation of embodiment 1,2, by be denoted as "~measure ", "~counting ", "~change More ", "~decision ", "~setting ", "~specify ", "~calculating ", "~judgement ", "~judgement ", "~choosing Select ", "~generation ", "~input ", the information, data, signal value or variable of the result of explanation such as "~reception " It is worth stored as a file arrive in main storage means 903.

In addition, Fig. 9 structure is only one of the hardware configuration for representing transacter 100, transacter 100 Hardware configuration be not limited to structure described in Fig. 9, can be other structures.

Label declaration

100 transacters；1011PPS signal receiving parts；102 clock generation units；103 clock jitter determination parts；104 Deviation measuring value maintaining part；105 sampling period count sections；106 sampled signal generating units, 107 electrical quantity determination parts；108 data Generating unit；109 communication units；301 deviation measuring value maintaining parts；302 clock jitter value generating units；501 sampling location adjustment portions.

Claims

1. a kind of signal processing apparatus, it is characterised in that it possesses：

1PPS signal receiving parts, it receives 1PPS signals, wherein, 1PPS represents pulse per second (PPS)；

Clock generation unit, it generates the clock signal of the clock cycle smaller than 1 second；

Clock jitter determination part, it inputs above-mentioned 1PPS signals from above-mentioned 1PPS signal receiving parts, defeated from above-mentioned clock generation unit Enter above-mentioned clock signal, whenever above-mentioned 1PPS signals are inputted, determine clock jitter, the clock jitter is above-mentioned clock signal phase For the frequency departure of above-mentioned 1PPS signals；

Deviation measuring value maintaining part, it is kept by the multiple measure in above-mentioned clock jitter determination part multiple clocks for obtaining Deviation measuring value；And

Deviation measuring value selector, in its above-mentioned multiple clock jitter measured value kept to above-mentioned deviation measuring value maintaining part Newest clock jitter measured value compared with other clock jitter measured values, in above-mentioned newest clock jitter measured value With other clock jitter measured values it is consistent in defined permissible range when, above-mentioned newest clock jitter measured value is output to Destination is exported, is differed in above-mentioned newest clock jitter measured value with other clock jitter measured values in above-mentioned permissible range During cause, any clock jitter measured value in above-mentioned other clock jitter measured values is output to above-mentioned output destination,

Said signal processing device is also equipped with：

Counter, it inputs above-mentioned 1PPS signals from above-mentioned 1PPS signal receiving parts, when inputting above-mentioned from above-mentioned clock generation unit Clock signal, with the clock cycle of above-mentioned clock signal accordingly carry out from count initial value to count end value counting, when cut At the end of counting untill above-mentioned counting end value, start the counting from above-mentioned counting initial value；And

Correction of timing value calculating part, it monitors the incoming timing for the above-mentioned 1PPS signals for being input to above-mentioned counter and above-mentioned counting The timing of above-mentioned counting initial value in device, differ in the timing and the incoming timing of above-mentioned 1PPS signals of above-mentioned counting initial value In the case of cause, calculate for making the timing of the above-mentioned counting initial value timing school consistent with the incoming timing of above-mentioned 1PPS signals On the occasion of,

Above-mentioned counter changes above-mentioned counting end value using the correction of timing value calculated by above-mentioned correction of timing value calculating part, Make the timing of above-mentioned counting initial value consistent with the incoming timing of above-mentioned 1PPS signals.

2. signal processing apparatus according to claim 1, it is characterised in that

Above-mentioned correction of timing value calculating part is above-mentioned counting in the incoming timing for the above-mentioned 1PPS signals for being input to above-mentioned counter In the case of after median between initial value and above-mentioned counting end value and before above-mentioned counting end value, make above-mentioned counting Device subtracts correction of timing value from above-mentioned counting end value,

After being input to the incoming timing of above-mentioned 1PPS signals of above-mentioned counter and being above-mentioned counting initial value and above-mentioned centre In the case of before value, above-mentioned counter is set to be added correction of timing value with above-mentioned counting end value.

3. signal processing apparatus according to claim 1 or 2, it is characterised in that

Above-mentioned correction of timing value calculating part carries out n segmentations to the correction of timing value calculated, and n is more than 2 integer,

The partition value of above-mentioned correction of timing value is changed above-mentioned n times counting by above-mentioned counter for the counting end value of n times End value, make the timing of above-mentioned counting initial value consistent with the incoming timing of above-mentioned 1PPS signals.

4. a kind of signal processing apparatus, it is characterised in that it possesses：

5. signal processing apparatus according to claim 4, it is characterised in that

6. the signal processing apparatus according to claim 4 or 5, it is characterised in that

Above-mentioned correction of timing value calculating part carries out n segmentations to the correction of timing value calculated, and n is more than 2 integer