CN109450584A - Time measurement device and method - Google Patents
Time measurement device and method Download PDFInfo
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- CN109450584A CN109450584A CN201811435173.0A CN201811435173A CN109450584A CN 109450584 A CN109450584 A CN 109450584A CN 201811435173 A CN201811435173 A CN 201811435173A CN 109450584 A CN109450584 A CN 109450584A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0658—Clock or time synchronisation among packet nodes
- H04J3/0661—Clock or time synchronisation among packet nodes using timestamps
- H04J3/0667—Bidirectional timestamps, e.g. NTP or PTP for compensation of clock drift and for compensation of propagation delays
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0644—External master-clock
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/08—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/50—Testing arrangements
Abstract
The embodiment of the invention discloses a kind of time measurement device and methods, comprising: time measuring circuit, FPGA circuitry and primary processor；Time measuring circuit is connected with FPGA circuitry and at least two Devices to test respectively, for obtaining the time signal of at least two Devices to test simultaneously, and is sent to FPGA circuitry；FPGA circuitry is connected with primary processor, for extracting the temporal information of corresponding Devices to test from the time signal of at least two Devices to test respectively, and is sent to primary processor；Primary processor, for calculating the time value of each Devices to test according to the temporal information of each Devices to test, and calculate deviation time value of the time value relative to reference time value of each Devices to test, the technical solution of the embodiment of the present invention, the time deviation that each Devices to test can be calculated based on same time datum mark improves the accuracy of the time deviation of Devices to test and the property of can refer to.
Description
Technical field
The present embodiments relate to signal measurement field more particularly to a kind of time measurement device and methods.
Background technique
As the automatization level of the industries such as electric power, communication is higher and higher, time synchronization problem is automatic as these industries
The operation basis of change system, has obtained more and more attention, and unified and accurate runing time is to guarantee system safety operation
And an important factor for improving operation level.
Currently, when each voltage class substation and Dispatch authorities generally use the deviation of time tester detection device
Between, method are as follows: the time deviation of one equipment of single measurement obtains the time deviation letter of all devices by repeatedly measuring
Breath, to achieve the purpose that the runing time of all devices is monitored, alerts and is adjusted.
In the prior art, due to external time source or time tester itself the problem of, when the benchmark of time tester
Between there may be jitter error, this may cause the datum mark measured every time inaccurate, can not carry out to all Devices to test
High-precision time management.
Summary of the invention
The embodiment of the present invention provides a kind of time measurement device and method, to realize unified time datum mark and height
Precision measure time data.
In a first aspect, the embodiment of the invention provides a kind of time measurement devices, comprising: time measuring circuit, FPGA
(Field-Programmable Gate Array, field programmable gate array) circuit and primary processor；
The time measuring circuit is connected with the FPGA circuitry and at least two Devices to test respectively, for obtaining simultaneously
The time signal of at least two Devices to test, and be sent to the FPGA circuitry, wherein the time measuring circuit includes
At least two-way time measuring unit, time measuring unit described in every road are connected with the FPGA circuitry, and respectively with an institute
It states Devices to test to be connected, to obtain the time signal of corresponding Devices to test；
The FPGA circuitry is connected with the primary processor, for believing respectively from the time of at least two Devices to test
The temporal information of corresponding Devices to test is extracted in number, and is sent to the primary processor；
The primary processor, for calculating the time of each Devices to test according to the temporal information of each Devices to test
Value, and calculate deviation time value of the time value relative to reference time value of each Devices to test.
Second aspect, the embodiment of the invention also provides a kind of Method Of Time Measurements, including；
Time measuring circuit obtains the time signal of at least two Devices to test simultaneously, and is sent to FPGA circuitry, wherein
The time measuring circuit includes at least two-way time measuring unit, and time measuring unit described in every road is from connected to it described
Corresponding time signal is obtained in Devices to test；
The FPGA circuitry extracts corresponding Devices to test from the time signal of at least two Devices to test respectively
Temporal information, and it is sent to the primary processor；
The primary processor calculates the time value of each Devices to test according to the temporal information of each Devices to test, and
Calculate deviation time value of the time value relative to reference time value of each Devices to test.
The embodiment of the present invention is used by the way that time measuring circuit is connected with FPGA circuitry and at least two Devices to test respectively
In the time signal of at least two Devices to test of acquisition simultaneously, and it is sent to FPGA circuitry；By FPGA circuitry and main process task
Device is connected, for extracting the temporal information of corresponding Devices to test from the time signal of at least two Devices to test respectively, concurrently
It send to primary processor；Primary processor is used to calculate the time value of each Devices to test according to the temporal information of each Devices to test, and counts
Deviation time value of the time value relative to reference time value of each Devices to test is calculated, to form a kind of time measurement device, is solved
The prior art of having determined cannot measure the time deviation of multiple equipment, the skimble-scamble problem of time datum mark, Neng Gouji simultaneously
Calculate the time deviation of each Devices to test in same time datum mark, improve the time deviation of Devices to test accuracy and
The property of can refer to.
Detailed description of the invention
Fig. 1 is a kind of structural schematic diagram for time measurement device that the embodiment of the present invention one provides；
Fig. 2 is a kind of external connection structure schematic diagram of time measurement device provided by Embodiment 2 of the present invention；
Fig. 3 is a kind of flow chart for Method Of Time Measurement that the embodiment of the present invention three provides；
Fig. 4 is a kind of flow chart for Method Of Time Measurement that the embodiment of the present invention four provides；
Fig. 5 is a kind of flow chart for Method Of Time Measurement that the embodiment of the present invention five provides；
Fig. 6 is a kind of flow chart for Method Of Time Measurement that the embodiment of the present invention six provides.
Specific embodiment
The present invention is described in further detail with reference to the accompanying drawings and examples.It is understood that this place is retouched
The specific embodiment stated is used only for explaining the present invention rather than limiting the invention.It also should be noted that in order to just
Only the parts related to the present invention are shown in description, attached drawing rather than entire infrastructure.
Embodiment one
Fig. 1 is a kind of structural schematic diagram for time measurement device that the embodiment of the present invention one provides, and the present embodiment is applicable
In time deviation of the detection device runing time relative to fiducial time the case where, it should be noted that the embodiment of the present invention mentions
The time measurement device of confession can operate in the automated system for needing the multiple equipment retention time synchronous, such as voltage class becomes
Power station, petroleum and mineral resources acquisition station and large ship staging system etc..
As shown in Figure 1, time measurement device includes: time measuring circuit 11, FPGA circuitry 12 and primary processor 13.
Time measuring circuit 11 is connected with FPGA circuitry 12 and at least two Devices to test respectively, is used for while obtaining at least
The time signal of two Devices to test, and it is sent to FPGA circuitry 12, wherein time measuring circuit 11 includes at least two-way time
Measuring unit, every road time measuring unit are connected with FPGA circuitry 12, and are connected respectively with a Devices to test, to obtain phase
Answer the time signal of Devices to test.
Wherein, at least two Devices to test being connected with time measuring circuit 11 belong to an automated system, to be measured to set
Between standby, time synchronization is required between Devices to test and automated system, just can guarantee that automated system operates normally, each
Devices to test is provided with respective local time signal, and the operation of Devices to test is based on the local time signal, different to be measured
The local time signal of equipment is likely to be out of synchronization, but the time signal type of each Devices to test is consistent, the type packet of time signal
Contain but is not limited to IRIG-B (Inter Range Instrumentation Group, U.S. target range instrument group) signal, 1PPS
(Pulse per Second, pulse per second (PPS)) and TOD (Time of Day, Time of Day information) combines signal, PTP (Precision
Time Protocol, Precision Time Protocol) signal and NTP (Network Time Protocol, Network Time Protocol) letter
Number.Time measuring circuit 11 includes multi-channel Time measuring unit, and every road time measuring unit is connected with a Devices to test, to obtain
Take the time signal of corresponding Devices to test.
In a specific example, time measuring circuit 11 includes 12 road time measuring units, and every road time measurement is single
Member is connected with a Devices to test, and in a certain preset time point, time measuring circuit 11 is obtained from each Devices to test simultaneously
Type is the time signal of IRIG-B, and the time signal that will acquire is sent to FPGA circuitry 12.
FPGA circuitry 12 is connected with primary processor 13, for extracting from the time signal of at least two Devices to test respectively
The temporal information of corresponding Devices to test, and it is sent to primary processor 13.
Wherein, temporal information is obtained from time signal, and time signal is decoded into the information of digital form, time
Information can reflect the time value of Devices to test.
Primary processor 13 for calculating the time value of each Devices to test according to the temporal information of each Devices to test, and calculates
Deviation time value of the time value of each Devices to test relative to reference time value.
In general, primary processor 13 is showed in the form of universal computing device, wherein comprising one or more processing units,
It is connected between primary processor 13 and FPGA circuitry 12 with bus form.
Wherein, the time value of Devices to test is obtained according to the data reduction in temporal information, the expression-form of time value
Including but not limited to the form that seconds value and nanosecond value combine, reference time value is the time value determined by reference time signal, base
Quasi- time signal is that primary processor 13 is obtained from alternative reference time signal according to selection rule, and reference time value can be
The internal time benchmark of time measurement device is also possible to the internal time benchmark of one of equipment in all Devices to test.
The technical solution of the present embodiment by by time measuring circuit respectively with FPGA circuitry and at least two Devices to test
It is connected, for obtaining the time signal of at least two Devices to test simultaneously, and is sent to FPGA circuitry；By FPGA circuitry and main place
Device is managed to be connected, for the temporal information of corresponding Devices to test to be extracted from the time signal of at least two Devices to test respectively, and
It is sent to primary processor；Primary processor is used to calculate the time value of each Devices to test according to the temporal information of each Devices to test, and
Deviation time value of the time value relative to reference time value of each Devices to test is calculated, so that a kind of time measurement device is formed,
The time signal for obtaining corresponding Devices to test simultaneously using at least two-way time measuring unit in time measuring circuit, based on same
When the time signal that obtains calculate the deviation time value of each Devices to test, multiple set cannot be measured simultaneously by solving the prior art
Standby time deviation, the skimble-scamble problem of time datum mark can be calculated each to be measured based on same time datum mark
The time deviation of equipment improves the accuracy of the time deviation of Devices to test and the property of can refer to.
Optionally, device further include: crystal oscillating circuit 14 is connected with FPGA circuitry 12, for providing base to FPGA circuitry 12
Quasi- frequency signal；
FPGA circuitry 12 specifically includes: Devices to test time signal decoder module 121 and TDC (Time to Digital
Converter, time-to-digit converter) digital quantization module 122, in which:
Devices to test time signal decoder module 121 respectively with 11 road Zhong Ge of crystal oscillating circuit 14 and time measuring circuit when
Between measuring unit be connected, for being decoded according to time signal of the reference frequency signal to each Devices to test, obtain each to be measured
The seconds value of equipment and second are along count value；
TDC digital quantization module 122 is single with crystal oscillating circuit 14 and the measurement of 11 road Zhong Ge time of time measuring circuit respectively
Member is connected, the TDC digital quantization value of the time signal for calculating each Devices to test according to reference frequency signal.
Wherein, temporal information includes: seconds value, second along count value and TDC digital quantization value, and seconds value is table in time signal
Show the part of number of seconds value, which be calculated by Devices to test time signal decoder module 121.
Second along count value generated by nanosecond counter, for record be less than in time signal minimum time of day when
Between in length, the number of reference frequency signal corresponding clock cycle, for example, in IRIG-B IRIG-B format time code, minimum timing
Unit is 1s, then what the second recorded along count value is exactly the reference frequency signal corresponding clock week in the time span less than 1s
The number of phase, second are also to be calculated by Devices to test time signal decoder module 121 along count value.
TDC digital quantization value is used to record the time span less than the reference frequency signal corresponding clock cycle, TDC number
Quantized value is calculated by TDC digital quantization module 122, after TDC digital quantization module 122 is based on multichannel phase offset
Reference frequency signal calculated in the last one reference frequency signal corresponding clock cycle that above-mentioned nanosecond counter calculates,
More than the time span of datum mark, for example, the second is 5 along count value, the reference frequency signal corresponding clock cycle is 10ns, then says
It is bright, in the 5th 10ns clock cycle that nanosecond counter calculates, it should the detection reference including time measuring circuit 11,
So accurate nanosecond value in order to obtain, it is also necessary to the time span more than datum mark is subtracted in the 5th 10ns clock cycle,
I.e. corresponding TDC digital quantization value.
Reference frequency signal is provided by crystal oscillating circuit 14, the reference signal as decoding and TDC digital quantization.Its
In, the crystal oscillator type used is including but not limited to common crystals, temperature compensating crystal oscillator, voltage controlled crystal oscillator and temperature control crystal oscillator.Reference frequency
The frequency of signal can be arranged according to actual measurement demand.
In this optional technical solution, the decoding of Devices to test time signal decoder module 121 in FPGA circuitry respectively to
The time signal of measurement equipment obtains the TDC digital quantization module 122 of corresponding seconds value and second in count value, FPGA circuitry
The TDC digital quantization value of corresponding time signal is calculated, to obtain time letter corresponding with the time signal of each Devices to test
Breath.
The benefit being arranged in this way is: being believed using TDC digital quantization module 122 in FPGA circuitry 12 and Devices to test time
Number decoder module 121, is divided into multiple phase process for the time signal of each Devices to test, ensure that the precision of data processing, with
Improve crystal oscillating circuit 14 in reference frequency signal frequency, can be further accurate by the time value of time signal, enhance
The accuracy of the time value got in time measurement device.
The TDC digital quantization module and Devices to test time signal in FPGA circuitry are used in this optional technical solution
Seconds value, second in decoder module acquisition time information ensure that the number in temporal information along count value and TDC digital quantization value
According to precision, the accuracy of the time value of acquisition is enhanced.
Optionally, reference time value is obtained according to outside reference time signal or is obtained according to local reference time signal；
Device further include: time source circuit 15 is connect with FPGA circuitry 12, for providing outside reference to FPGA circuitry 12
Time signal；
Correspondingly, FPGA circuitry 12 further include:
Outside reference time signal decoder module 123, is connected with crystal oscillating circuit 14 and time source circuit 15 respectively, is used for root
External reference time signal is decoded according to reference frequency signal, the seconds value for obtaining outside reference time signal and second are along counting
Value；
TDC digital quantization module 122, is also connected with time source circuit 15, external for being calculated according to reference frequency signal
The TDC digital quantization value of reference time signal.
Wherein, reference time value is the reduced time value for calculating each Devices to test time deviation, and reference time value can
To be obtained from outside reference time signal, can also be obtained from local reference time signal.Local reference time signal refers to
In the time signal of the local clock generation of FPGA circuitry 12 itself or all Devices to test when the inside of one of equipment
Between signal.
The signal source of optional reference time value is provided for time measurement device in this optional technical solution, is guaranteed
The stability of reference time value, so that the time deviation for accurately calculating each Devices to test for time measurement device provides guarantor
Barrier.
Optionally, time source circuit 15 specifically includes: satellite-signal time source module and non-satellite signal time source module,
Wherein:
Satellite-signal time source module, for receiving GPS satellite signal and generating corresponding outside reference time signal；
Non-satellite signal time source module, for generating based on the outer of other signal sources acquisition in addition to GPS satellite signal
Portion's reference time signal.
Wherein, specific for receiving including but not limited to receiving antenna and receiver in satellite-signal time source module
GPS (Global Positioning System, global positioning system) satellite-signal of frequency, when as outside reference
Between signal, the outside reference time signal that non-satellite signal time source module generates is including but not limited to IRIG-B signal, 1PPS
Signal, PTP signal and NTP signal are combined with TOD, non-satellite signal time source module is not based on GPS satellite letter for generating
Number other outside reference time signals, for example, using decoding photosignal obtain IRIG-B signal.
Time source circuit is specifically divided into satellite-signal time source module and non-satellite letter in this optional technical solution
Number time source module, has achieved the purpose that a plurality of types of outside reference time signals can be provided for time measurement device, protects
The stability and accuracy of reference time value are demonstrate,proved.
Optionally, primary processor 13 includes:
Time value computing module 131 for calculating the nanosecond value of Devices to test according to the temporal information of Devices to test, and is counted
Calculate Devices to test nanosecond value relative to reference time signal nanosecond value nanosecond deviation, in conjunction with Devices to test relative to base
The second deviation and nanosecond deviation of quasi- time signal, obtain deviation time value:
Wherein, the formula of nanosecond deviation is calculated are as follows: tns=C × T-TDC-t0,
tnsIndicate the nanosecond deviation of Devices to test, C indicates the second of Devices to test along count value, and T indicates reference frequency letter
Number the corresponding clock cycle, TDC indicate Devices to test time signal TDC digital quantization value, C × T-TDC indicate it is to be measured
The nanosecond value of equipment, t0Indicate the nanosecond value of reference time signal, t0=C0×T-TDC0, C0Indicate the second edge of reference time signal
Count value, TDC0Indicate the TDC digital quantization value of reference time signal.
Wherein, time value includes seconds value and nanosecond value, and seconds value is the seconds value in the calculated temporal information of FPGA circuitry 12
Part, nanosecond value are needed according to the second in temporal information along count value C, TDC digital quantization value TDC and reference frequency signal pair
The clock cycle T answered is calculated, and deviation time value includes second deviation and nanosecond deviation, when second deviation is Devices to test
Between seconds value in seconds value and reference time value in value subtract each other as a result, nanosecond deviation is the nanosecond in Devices to test time value
The result that nanosecond value in value and reference time value is subtracted each other.
When in this optional technical solution by calculating each Devices to test using the time value computing module in primary processor
Between signal time value and reporting, reached based on same datum mark, obtained the time data of multiple Devices to test
Purpose, to judge whether time synchronization provides accurate data basis to each Devices to test.
Optionally, FPGA circuitry 12 further include:
Frequency signal processing module is connected with crystal oscillating circuit 14, the reference frequency signal for providing crystal oscillating circuit 14
It is converted into setpoint frequency signal；
Correspondingly, Devices to test time signal decoder module 121, is connected with frequency signal processing module, set for basis
Determine frequency signal to be decoded the time signal of each Devices to test, the seconds value for obtaining each Devices to test and second are along count value；
Outside reference time signal decoder module 123, is connected with frequency signal processing module, for being believed according to setpoint frequency
Number external reference time signal is decoded, the seconds value for obtaining outside reference time signal and second are along count value；
TDC digital quantization module 122, is connected with frequency signal processing module, each for being calculated according to setpoint frequency signal
The TDC digital quantization value of the time signal of Devices to test and the TDC digital quantization value of reference time signal, wherein fiducial time
Signal is outside reference time signal or local reference time signal.
Wherein, frequency signal processing module is used to convert the reference frequency signal that crystal oscillating circuit 14 provides to high-precision frequency
Rate signal, using process of frequency multiplication, can be turned to 125M high-precision for example, the reference frequency that crystal oscillating circuit 14 provides is 10M
Frequency signal.
The benefit being arranged in this way is: improving the frequency of oscillation of reference frequency signal using frequency signal processing module, obtains
High-precision setpoint frequency signal can be improved FPGA circuitry 12 and fall into a trap the data precision of evaluation time information, for example, when based on crystalline substance
When the 10M reference frequency signal that circuit 14 provides that shakes calculates temporal information, the reference frequency signal corresponding clock cycle is
100ns, and after converting high-precision setpoint frequency signal for reference frequency signal, oscillation frequency 125M, setpoint frequency letter
Number corresponding clock cycle is 8ns, then the precision of calculated time value significantly improves, and help to obtain accurately time data.
Turned in this optional technical solution using the reference frequency signal that frequency signal processing module provides crystal oscillating circuit
Setpoint frequency signal is turned to, and the setpoint frequency signal is used for acquisition time information, the precision of time data can be improved, is protected
It is more accurate to demonstrate,prove calculated time deviation data.
Embodiment two
Fig. 2 is a kind of external connection structure schematic diagram of time measurement device provided by Embodiment 2 of the present invention, this implementation
Example further illustrates on the basis of a upper embodiment, the specific effect of primary processor is provided, below with reference to Fig. 2 to this implementation
A kind of time measurement device that example two provides is illustrated, and in the present embodiment, primary processor is used for:
The comparison channel at least two-way time measuring unit is determined according to instruction information.
Wherein, instruction information can be handed down to time measurement device by operator workstation 22, include operator in information
The comparison channel position of member's instruction, is also possible to preset instruction information in time measurement device, for example, surveying between upon this detection
, it is specified that preset time measuring unit is comparison channel when measuring in device without effective outside reference time signal.
In the present embodiment, operator workstation 22 is connected with time measurement device 21, as shown in Fig. 2, be for pair
Time measurement device 21 and all Devices to test 23 play the role of the working end of monitoring.Typically, in operator workstation 22
Comprising time management system, time measurement device is connect by the network interface of primary processor with time management system, will be calculated
The time deviation data of obtained each Devices to test 23 are reported to time management system by network protocol processing unit in time, with
It realizes and continuous long term monitoring is carried out to the time of each Devices to test 23, so that it is managed collectively each Devices to test, meanwhile, operator
Time measurement device 21 can also be indicated according to the letter issued by time management system to the lower photos and sending messages of time measurement device 21
Breath executes corresponding operation.
In the present embodiment, the time value computing module of primary processor determines that at least the two-way time measures from instruction information
Comparison channel in unit, using the time signal in the comparison channel as reference time signal.In general, multiple in needs
In the automated system of 23 time synchronization of Devices to test, master clock and standby clock can be set in the automated system, facilitate basis
The runing time of master clock and/or standby clock adjusts the runing time of each Devices to test 23 in automated system, so, in this implementation
In example, it is preferred that using master clock and standby clock as Devices to test 23, be connected with time measuring unit, use master clock and/or standby clock
The time measuring unit at place channel as a comparison.Certainly, non-master clock can also be chosen and in the present embodiment for the to be measured of clock
Time measuring unit where equipment 23 channel as a comparison.
Calculate the time value for the Devices to test 23 that comparison channel obtains and at least in two-way time measuring unit except comparison is logical
Deviation time value between the time value for the Devices to test 23 that other times measuring unit except road obtains.
The advantages of this arrangement are as follows: in more equipment automatization systems, determine each Devices to test 23 relative to one
The runing time deviation of Devices to test 23, the operation that the more intuitive each Devices to test 23 of judgement of operator can be made current
Situation, to improve the operation level of entire automated system.
By determining comparison channel in this optional technical solution, the time value for the Devices to test that comparison channel obtains is calculated
Deviation time value between the time value of the Devices to test obtained with the other times measuring unit in addition to comparing channel, reaches
Time deviation is calculated in the internal system comprising each Devices to test, is based on internal clocking, the fortune of each Devices to test in adjustment system
The purpose of row time improves the operation level of system.
Embodiment three
Fig. 3 is a kind of flow chart for Method Of Time Measurement that the embodiment of the present invention three provides, and the present embodiment is applicable to examine
The case where time deviation of the measurement equipment runing time relative to fiducial time, this method can be held by above-mentioned time measurement device
Row.
The method of the present embodiment specifically comprises the following steps:
Step 310, time measuring circuit obtain the time signal of at least two Devices to test simultaneously, and are sent to FPGA electricity
Road, wherein time measuring circuit includes at least two-way time measuring unit, and every road time measuring unit is from connected to it to be measured
Corresponding time signal is obtained in equipment.
Wherein, the time signal type of each Devices to test is consistent, and the type of time signal is believed including but not limited to IRIG-B
Number, 1PPS signal, PTP signal and NTP signal are combined with TOD.
In the present embodiment, time measuring circuit is obtained simultaneously in a parallel fashion in a certain preset time point and is measured with the time
The time signal of the connected each Devices to test of multi-channel Time measuring unit, makes the datum mark of each time signal got in circuit
It is identical, achieve the purpose that the parallel detection equipment time.
Step 320, FPGA circuitry extract corresponding Devices to test from the time signal of at least two Devices to test respectively
Temporal information, and it is sent to primary processor.
In the present embodiment, FPGA circuitry decodes the time signal of at least two Devices to test, when therefrom extracting corresponding
Between information, which can be serial process, is also possible to parallel processing, can also be serial and concurrent combined treatment,
When FPGA circuitry decoding cores are monokaryon, the serial time signal for decoding Devices to test therefrom extracts corresponding temporal information；
When FPGA circuitry decoding cores are multicore, according to the quantity of Devices to test and FPGA circuitry decoding cores number, can dispatch
Realize parallel decoding or serial and concurrent combination decoding, it should be noted that in FPGA circuitry, even using serial solution
Code, for decoding the time signal of 12 Devices to test, decoding time is 1 second, and time measurement device may be implemented to be measured
The real time monitoring of equipment.
Step 330, primary processor calculate the time value of each Devices to test according to the temporal information of each Devices to test, and calculate
Deviation time value of the time value of each Devices to test relative to reference time value.
Wherein, the mode that primary processor carries out data calculating can be serial computing, be also possible to parallel computation, can be with
It is that serial and concurrent combination calculates, which is determined by the processing unit number and calculating data volume of primary processor.
In the present embodiment, primary processor is by the time value for calculating each Devices to test and each time value relative to benchmark
The deviation time value of time value can clearly obtain the local time signal of each Devices to test relative to reference time signal
Deviation, to achieve the purpose that the runing time synchronization monitoring to each Devices to test.
In the technical solution of the present embodiment after the time signal of time measuring circuit while at least two Devices to test of acquisition,
The time signal is sent to FPGA circuitry, FPGA circuitry extracts the time letter of corresponding Devices to test from the time signal respectively
Breath, is then forwarded to primary processor, and primary processor calculates the time value of each Devices to test according to the temporal information of each Devices to test,
And deviation time value of the time value relative to reference time value of each Devices to test is calculated, solving the prior art cannot survey simultaneously
The time signal of multiple equipment is measured, the skimble-scamble problem of time datum mark can be based on same time datum mark
The time deviation for calculating each Devices to test improves the accuracy of the time deviation of Devices to test and the property of can refer to.
Example IV
Fig. 4 is a kind of flow chart for Method Of Time Measurement that the embodiment of the present invention four provides, and the present embodiment is implemented upper one
It is further refined on the basis of example, the particular content and FPGA circuitry for providing temporal information to be measured are set from least two respectively
The specific implementation step of the temporal information of corresponding Devices to test is extracted in standby time signal.Below with reference to Fig. 4 to of the invention real
A kind of Method Of Time Measurement for applying the offer of example three is illustrated, comprising the following steps:
Step 410, time measuring circuit obtain the time signal of at least two Devices to test simultaneously, and are sent to FPGA electricity
Road, wherein time measuring circuit includes at least two-way time measuring unit, and every road time measuring unit is from connected to it to be measured
Corresponding time signal is obtained in equipment.
Step 420, FPGA circuitry are decoded according to time signal of the reference frequency signal to each Devices to test, are obtained each
The seconds value of Devices to test and second are along count value.
Step 430, FPGA circuitry calculate the TDC digital quantization of the time signal of each Devices to test according to reference frequency signal
Value.
Wherein, temporal information includes: seconds value, second along count value and TDC digital quantization value；Second is counted along count value by nanosecond
Number device generates；TDC digital quantization value record is less than the time span of reference frequency signal corresponding clock cycle.
In the present embodiment, the calculation of seconds value are as follows:, will be from a certain particular year according to the signal type of time signal
Start accumulative day, when, point and second data be converted to number of seconds value, calculation of the second along count value are as follows: in time signal,
Since the last one second before time measuring circuit obtains the datum mark of the time signal along, it is based on reference frequency signal,
Using the number of nanosecond counter records reference frequency signal corresponding clock cycle, until the datum mark, TDC digital quantization value
It is to be calculated by TDC digital quantization module, TDC digital quantization module is believed based on the reference frequency after multichannel phase offset
Number, it calculates in the last one reference frequency signal corresponding clock cycle that above-mentioned nanosecond counter calculates, is more than datum mark
Time span, reference frequency signal is provided by crystal oscillating circuit, for providing operation clock for decoding process.
In a specific example, the type for 12 Devices to test that FPGA circuitry acquisition time measuring circuit is sent is
The time signal of IRIG-B, the frequency of reference frequency signal is 10M in current crystal oscillating circuit, that is to say, that reference frequency signal pair
The clock cycle T answered isAt the time signal of a certain Devices to test in 12 Devices to test
Reason process include: firstly, Devices to test time signal decoder module 21 is according to the code frame structure of current IRIG-B IRIG-B format time code,
Decode " day " information therein, " when " information, " dividing " information and " second " information, obtain 1970 to datum mark accumulation
Number of seconds value, as the seconds value part in temporal information；Then Devices to test time signal decoder module decodes current IRIG-B lattice
It is less than the part of " second " information in formula timing code, is based on reference frequency 10M, when is less than " second " information using nanosecond counter records
Between in signal, the number of corresponding clock cycle 100ns obtains second in temporal information along counting value part；Finally, TDC number
Word quantization modules are 0,45,90 and 135 reference frequency signal respectively according to 4 tunnel phase offsets, calculate current IRIG-B format
It is more than datum mark and the time span for being less than the corresponding clock cycle 100ns of reference frequency signal in timing code, believes as the time
TDC digital quantization value in breath, the time signal processing mode of other 11 Devices to test is same as described above, needs to illustrate
, aforesaid operations step can be implemented concurrently, concomitantly or simultaneously.
The seconds value of each Devices to test that step 440, FPGA circuitry will acquire, second are along count value and TDC digital quantization value
It is sent to primary processor.
Step 450, primary processor calculate the time value of each Devices to test according to the temporal information of each Devices to test, and calculate
Deviation time value of the time value of each Devices to test relative to reference time value.
The technical solution of the present embodiment has carried out careful explanation on the basis of a upper embodiment, FPGA circuitry has been distinguished
The temporal information that corresponding Devices to test is extracted from the time signal of at least two Devices to test is further refined as specific reality
Step is applied, ensure that the data precision in temporal information, enhances the accuracy of the time value of acquisition.
Optionally, reference time value is obtained according to outside reference time signal or is obtained according to local reference time signal；
Method Of Time Measurement further include:
FPGA circuitry is decoded external reference time signal according to reference frequency signal, obtains outside reference time letter
Number seconds value and the second along count value；
FPGA circuitry calculates the TDC digital quantization value of outside reference time signal according to reference frequency signal.
In general, it is preferable to use outside reference time signal in the external normal situation of reference time signal quality, when
When detecting that outside reference time signal quality is not met using standard, just use local reference time signal as acquisition benchmark
The time source of time value, reason are: outside reference time signal is absolute time signal or close to absolute time signal
Time signal, local reference time signal is the local clock of FPGA circuitry, cannot be accurate for outside reference time signal
The current absolute time of reflection, for example, using the global clock resource of FPGA circuitry as local reference time signal, this is entirely
Office clock resource can only cover the clock demand to region each in FPGA, can not reach the unification with absolute time.
Outside reference time signal decoder module and TDC number in this optional technical solution, in FPGA circuitry
Quantization modules handle outside reference time signal, obtain the mode and FPGA electricity of the corresponding temporal information of outside reference time signal
The mode that the temporal information of each Devices to test is extracted on road is identical, for local reference time signal is generated by FPGA circuitry,
Only need to calculate corresponding TDC digital quantization value using TDC digital quantization module, remaining temporal information can directly in FPGA circuitry
It reads.
The signal source of optional reference time value is provided for time measurement device in this optional technical solution, is guaranteed
The stability of reference time value, so that the time deviation for accurately calculating each Devices to test for time measurement device provides guarantor
Barrier.
Embodiment five
Fig. 5 is a kind of flow chart for Method Of Time Measurement that the embodiment of the present invention five provides, and the present embodiment is in above-mentioned implementation
Example on the basis of further illustrate, provide primary processor according to the temporal information of each Devices to test calculate each Devices to test when
Between be worth, and calculate the specific implementation step of the time value of each Devices to test relative to the deviation time value of reference time value.Below
It is illustrated in conjunction with a kind of Fig. 5 Method Of Time Measurement provided the embodiment of the present invention four, comprising the following steps:
Step 510, time measuring circuit obtain the time signal of at least two Devices to test simultaneously, and are sent to FPGA electricity
Road, wherein time measuring circuit includes at least two-way time measuring unit, and every road time measuring unit is from connected to it to be measured
Corresponding time signal is obtained in equipment.
Step 520, FPGA circuitry extract corresponding Devices to test from the time signal of at least two Devices to test respectively
Temporal information, and it is sent to primary processor.
Step 530, primary processor calculate the nanosecond value of Devices to test according to the temporal information of Devices to test, and calculate to be measured
Equipment nanosecond value relative to reference time signal nanosecond value nanosecond deviation, in conjunction with Devices to test relative to fiducial time
The second deviation and nanosecond deviation of signal, obtain deviation time value；
Wherein, the formula of nanosecond deviation is calculated are as follows: tns=C × T-TDC-t0,
tnsIndicate the nanosecond deviation of Devices to test, C indicates the second of Devices to test along count value, and T indicates reference frequency letter
Number the corresponding clock cycle, TDC indicate Devices to test time signal TDC digital quantization value, C × T-TDC indicate it is to be measured
The nanosecond value of equipment, t0Indicate the nanosecond value of reference time signal, t0=C0×T-TDC0, C0Indicate the second edge of reference time signal
Count value, TDC0Indicate the TDC digital quantization value of reference time signal.
Wherein, time value includes seconds value and nanosecond value, and seconds value is the seconds value in the calculated temporal information of FPGA circuitry 12
Part, nanosecond value are needed according to the second in temporal information along count value C, TDC digital quantization value TDC and reference frequency signal pair
The clock cycle T answered is calculated, and deviation time value includes second deviation and nanosecond deviation, when second deviation is Devices to test
Between seconds value in seconds value and reference time value in value subtract each other as a result, nanosecond deviation is the nanosecond in Devices to test time value
The result that nanosecond value in value and reference time value is subtracted each other.
In a specific example, time measuring circuit includes 12 road time measuring units, every road time measuring unit
It is connected with a Devices to test, the corresponding clock cycle T=8ns of reference frequency signal, FPGA circuitry is according to each to be measured of acquisition
The time signal of equipment, the calculated corresponding second is as shown in table 1 below along count value and TDC digital quantization value, primary processor root
According to FPGA circuitry send data, calculated nanosecond data and nanosecond deviation Value Data it is as shown in table 2 below, wherein the time
Unit ns.
Table 1
Table 2
The technical solution of the present embodiment, when by calculating each Devices to test using the time value computing module in primary processor
Between signal time value and reporting, reached based on same datum mark, obtained the time data of multiple Devices to test
Purpose, to judge whether time synchronization provides accurate data basis to each Devices to test.
Optionally, second deviation and nanosecond deviation of the Devices to test relative to reference time signal are being combined, obtained partially
After poor time value, further includes:
Primary processor determines the comparison channel at least two-way time measuring unit according to instruction information；
Primary processor calculates the time value for comparing the Devices to test that channel obtains and removes at least two-way time measuring unit
Compare the deviation time value between the time value for the Devices to test that the other times measuring unit except channel obtains.
In general, can be set in the automated system in the automated system for needing multiple Devices to test time synchronizations
It sets master clock and standby clock, the purpose being arranged in this way is: when being scheduled management to each Devices to test, not only intentionally getting each
Difference of the runing time of Devices to test relative to reference time value is conducive to external communication, it is also desirable to obtain each Devices to test phase
For the time deviation of master clock in this system and/or standby clock, to facilitate according to the runing time of master clock and/or standby clock automatic
The runing time of each Devices to test of adjustment in change system.
In this optional technical solution, it is preferable that using master clock and standby clock as Devices to test, with time measuring unit
It is connected, using the time measuring unit where master clock and/or standby clock, channel, calculating are obtained from other times measuring unit as a comparison
Deviation time value of the time value of the Devices to test taken relative to the comparison corresponding time value in channel.
By determining comparison channel in this optional technical solution, the time value for the Devices to test that comparison channel obtains is calculated
Deviation time value between the time value of the Devices to test obtained with the other times measuring unit in addition to comparing channel, reaches
Time deviation is calculated in the internal system comprising each Devices to test, internal clocking is based on, adjusts the fortune of each Devices to test in device
The purpose of row time improves the operation level of device.
Embodiment six
Fig. 6 is a kind of flow chart for Method Of Time Measurement that the embodiment of the present invention six provides, and the present embodiment is in above-mentioned implementation
It is further illustrated on the basis of example, provides FPGA circuitry and extracted accordingly from the time signal of at least two Devices to test respectively
The specific implementation step of the temporal information of Devices to test.A kind of time that the embodiment of the present invention five provides is surveyed below with reference to Fig. 6
Amount method is illustrated, comprising the following steps:
Step 610, time measuring circuit obtain the time signal of at least two Devices to test simultaneously, and are sent to FPGA electricity
Road, wherein time measuring circuit includes at least two-way time measuring unit, and every road time measuring unit is from connected to it to be measured
Corresponding time signal is obtained in equipment.
Reference frequency signal is converted setpoint frequency signal by step 620, FPGA circuitry.
Step 630, FPGA circuitry are decoded according to time signal of the setpoint frequency signal to each Devices to test, are obtained each
The seconds value of Devices to test and second are along count value.
Step 640, FPGA circuitry are decoded external reference time signal according to setpoint frequency signal, obtain external base
The seconds value of quasi- time signal and second are along count value.
Step 650, FPGA circuitry calculate the TDC digital quantization of the time signal of each Devices to test according to setpoint frequency signal
The TDC digital quantization value of value and reference time signal, wherein reference time signal is outside reference time signal or this ground
Quasi- time signal.
In the present embodiment, the frequency of oscillation that reference frequency signal is improved using frequency signal processing module, is obtained high-precision
The setpoint frequency signal of degree can be improved FPGA circuitry and fall into a trap the data precision of evaluation time information, for example, when being based on crystal oscillating circuit
When the 10M reference frequency signal of offer calculates temporal information, the reference frequency signal corresponding clock cycle is 100ns, and by base
After quasi- frequency signal is converted into high-precision setpoint frequency signal, oscillation frequency 125M, the corresponding clock of setpoint frequency signal
Period is 8ns, then the precision of calculated time value significantly improves, and help to obtain accurately time data.
Seconds value that step 660, FPGA circuitry will acquire, second are sent to main process task along count value and TDC digital quantization value
Device.
Step 670, primary processor calculate the time value of each Devices to test according to the temporal information of each Devices to test, and calculate
Deviation time value of the time value of each Devices to test relative to reference time value.
The technical solution of the present embodiment is turned using the reference frequency signal that frequency signal processing module provides crystal oscillating circuit
Setpoint frequency signal is turned to, and the setpoint frequency signal is used for acquisition time information, the precision of time data can be improved, is protected
It is more accurate to demonstrate,prove calculated time deviation data.
Optionally, it obtains the time signal of at least two Devices to test simultaneously in time measuring circuit, and is sent to FPGA
Before circuit, further includes:
Primary processor selects the time signal source of reference time value according to selection rule；
Primary processor switches current time signal source to selected time signal source.
Wherein, reference time value is obtained according to outside reference time signal or is obtained according to local reference time signal, outside
Portion's reference time signal combined including but not limited to GPS satellite signal, IRIG-B signal, 1PPS with TOD signal, PTP signal with
And NTP signal, relatively for the local reference time signal of FPGA circuitry, outside reference time signal is more accurate, especially
GPS satellite signal can be used as absolute time signal, so choosing rule when choosing the time signal source of reference time value
Then are as follows: preferred GPS satellite signal, followed by other kinds of outside reference time signal, is finally local reference time signal.
In this optional technical solution, primary processor detects the GPS satellite signal currently obtained according to selection rule
Signal quality, if signal quality is good, using GPS satellite signal as the time signal source of reference time value, if GPS satellite is believed
Number signal quality it is not good, detect other kinds of outside reference time signal, wherein signal quality is good and optimal for selection
Time signal source of the time signal as reference time value, when detecting other kinds of outside reference time signal not
It is up to standard, choose time signal source of the local reference time signal as reference time value, wherein judge the standard of signal quality
The band information and continuity of connection and detection signal including but not limited to detection signal generation apparatus.
This optional technical solution provides the mode for choosing the time signal source of reference time value, primary processor according to
Selection rule chooses the time signal of signal type and the optimal time signal of quality as reference time value, improves base
The accuracy and stability of quasi- time value ensure that the correctness of the calculated time data of time measurement device, for respectively to
Measurement equipment normal operation provides safeguard.
Optionally, the time value of each Devices to test is calculated according to the temporal information of each Devices to test in primary processor, and is counted
After the time value of each Devices to test is calculated relative to the deviation time value of reference time value, further includes:
Deviation time value is stored in shared drive by primary processor；
Primary processor passes through the corresponding relationship of data address mapping table determination deviation time value and Devices to test；
Primary processor sends time management system for deviation time value and corresponding Devices to test information according to corresponding relationship
System.
Wherein, data address mapping table is for matching the storage location in shared drive and corresponding to setting for Devices to test
The relation table of standby serial number, data address mapping table are facilitated the time data that primary processor is calculated and are closed with correct mapping
System is sent to time management system, and time management system is used to show, store and handle the time that current primary processor is sent
Data, to assist staff to manage and dispatch each Devices to test, for example, warning level is arranged in time management system
Value is done when the time value for detecting a certain Devices to test is greater than alarm threshold value relative to the deviation time value of reference time value
Warning note out, warning staff needs to adjust the clock system of the Devices to test, to guarantee that the Devices to test and other wait for
Measurement equipment and entire examining system can be with normal communications.
This optional technical solution, primary processor determine time data and each Devices to test according to data address mapping table
Mapping relations, and send correct data information in time management system, ensure that time management system being capable of basis
Correct data judge the runing time of each Devices to test, assist staff's management to reach and dispatch each Devices to test
Purpose.
Note that the above is only a better embodiment of the present invention and the applied technical principle.It will be appreciated by those skilled in the art that
The invention is not limited to the specific embodiments described herein, be able to carry out for a person skilled in the art it is various it is apparent variation,
It readjusts and substitutes without departing from protection scope of the present invention.Therefore, although being carried out by above embodiments to the present invention
It is described in further detail, but the present invention is not limited to the above embodiments only, without departing from the inventive concept, also
It may include more other equivalent embodiments, and the scope of the invention is determined by the scope of the appended claims.
Claims (10)
1. a kind of time measurement device characterized by comprising time measuring circuit, FPGA circuitry and primary processor；
The time measuring circuit is connected with the FPGA circuitry and at least two Devices to test respectively, is used for while obtaining at least
The time signal of two Devices to test, and it is sent to the FPGA circuitry, wherein the time measuring circuit includes at least
Two-way time measuring unit, time measuring unit described in every road are connected with the FPGA circuitry, and respectively with described in one to
Measurement equipment is connected, to obtain the time signal of corresponding Devices to test；
The FPGA circuitry is connected with the primary processor, for respectively from the time signal of at least two Devices to test
The temporal information of corresponding Devices to test is extracted, and is sent to the primary processor；
The primary processor, for calculating the time value of each Devices to test according to the temporal information of each Devices to test,
And calculate deviation time value of the time value relative to reference time value of each Devices to test.
2. the apparatus according to claim 1, which is characterized in that the temporal information include: seconds value, second along count value and
TDC digital quantization value；The second is generated along count value by nanosecond counter；The TDC digital quantization value record is less than benchmark frequency
The time span of rate signal corresponding clock cycle；
Described device further include: crystal oscillating circuit is connected with the FPGA circuitry, for providing the benchmark to the FPGA circuitry
Frequency signal；
The FPGA circuitry specifically includes: Devices to test time signal decoder module and time-to-digit converter TDC digital quantity
Change module, in which:
The Devices to test time signal decoder module respectively with the crystal oscillating circuit and the road the time measuring circuit Zhong Ge
Time measuring unit is connected, for being decoded according to time signal of the reference frequency signal to each Devices to test,
The seconds value for obtaining each Devices to test and second are along count value；
The TDC digital quantization module measures with the crystal oscillating circuit and time measuring circuit Zhong Ge road time single respectively
Member is connected, the TDC digital quantization value of the time signal for calculating each Devices to test according to the reference frequency signal.
3. the apparatus of claim 2, which is characterized in that the reference time value is obtained according to outside reference time signal
It obtains or is obtained according to local reference time signal；
Described device further include: time source circuit is connect with the FPGA circuitry, described outer for providing to the FPGA circuitry
Portion's reference time signal；
Correspondingly, the FPGA circuitry further include:
Outside reference time signal decoder module is connected with the crystal oscillating circuit and the time source circuit respectively, is used for basis
The reference frequency signal is decoded the outside reference time signal, obtains the seconds value of the outside reference time signal
With the second along count value；
The TDC digital quantization module is also connected with the time source circuit, for calculating institute according to the reference frequency signal
State the TDC digital quantization value of outside reference time signal.
4. the apparatus according to claim 1, which is characterized in that the primary processor is used for:
The comparison channel in time measuring unit described at least two-way is determined according to instruction information；
It calculates described in being removed in the time value and time measuring unit described at least two-way for the Devices to test that the comparison channel obtains
Compare the deviation time value between the time value for the Devices to test that the other times measuring unit except channel obtains.
5. device according to claim 2 or 3, which is characterized in that the FPGA circuitry further include:
Frequency signal processing module is connected with the crystal oscillating circuit, the reference frequency for providing the crystal oscillating circuit
Signal is converted into setpoint frequency signal；
Correspondingly, Devices to test time signal decoder module, is connected, for setting according to the frequency signal processing module
Determine frequency signal to be decoded the time signal of each Devices to test, the seconds value for obtaining each Devices to test and second are along meter
Numerical value；
Outside reference time signal decoder module is connected with the frequency signal processing module, for according to the setpoint frequency
Signal is decoded the outside reference time signal, and the seconds value for obtaining the outside reference time signal and second are along counting
Value；
The TDC digital quantization module is connected with the frequency signal processing module, based on according to the setpoint frequency signal
The TDC digital quantization value of the time signal of each Devices to test and the TDC digital quantization value of reference time signal are calculated,
In, the reference time signal is outside reference time signal or local reference time signal.
6. a kind of Method Of Time Measurement is applied in time measurement device as described in any one in claim 1-5, feature exists
In, comprising:
Time measuring circuit obtains the time signal of at least two Devices to test simultaneously, and is sent to FPGA circuitry, wherein described
Time measuring circuit includes at least two-way time measuring unit, and time measuring unit described in every road is from connected to it described to be measured
Corresponding time signal is obtained in equipment；
The FPGA circuitry extracts the time of corresponding Devices to test from the time signal of at least two Devices to test respectively
Information, and it is sent to the primary processor；
The primary processor calculates the time value of each Devices to test according to the temporal information of each Devices to test, and calculates
Deviation time value of the time value of each Devices to test relative to reference time value.
7. according to the method described in claim 6, it is characterized in that, the temporal information include: seconds value, second along count value and
TDC digital quantization value；The second is generated along count value by nanosecond counter；The TDC digital quantization value record is less than benchmark frequency
The time span of rate signal corresponding clock cycle；
The FPGA circuitry extracts the time of corresponding Devices to test from the time signal of at least two Devices to test respectively
Information, comprising:
The FPGA circuitry is decoded according to time signal of the reference frequency signal to each Devices to test, is obtained each
The seconds value of the Devices to test and second are along count value；
The FPGA circuitry calculates the TDC digital quantization of the time signal of each Devices to test according to the reference frequency signal
Value.
8. the method according to the description of claim 7 is characterized in that the reference time value is obtained according to outside reference time signal
It obtains or is obtained according to local reference time signal；
The Method Of Time Measurement further include:
The FPGA circuitry is decoded the outside reference time signal according to the reference frequency signal, obtains described outer
The seconds value of portion's reference time signal and second are along count value；
The FPGA circuitry calculates the TDC digital quantization value of the outside reference time signal according to the reference frequency signal.
9. according to the method described in claim 6, it is characterized in that, the primary processor is according to time of each Devices to test
Information calculates the time value of each Devices to test, and calculates the time value of each Devices to test relative to reference time value
Deviation time value, comprising:
The primary processor determines the comparison channel in time measuring unit described at least two-way according to instruction information；
The time value that the primary processor calculates the Devices to test that the comparison channel obtains is measured with the time described at least two-way
In unit except it is described comparison channel in addition to other times measuring unit obtain Devices to test time value between deviation when
Between be worth.
10. according to the method described in claim 6, it is characterized in that, the FPGA circuitry is described to be measured from least two respectively
The temporal information of corresponding Devices to test is extracted in the time signal of equipment, comprising:
Reference frequency signal is converted setpoint frequency signal by the FPGA circuitry；
The FPGA circuitry is decoded according to time signal of the setpoint frequency signal to each Devices to test, is obtained each
The seconds value of the Devices to test and second are along count value；
The FPGA circuitry is decoded the outside reference time signal according to the setpoint frequency signal, obtains described outer
The seconds value of portion's reference time signal and second are along count value；
The FPGA circuitry calculates the TDC digital quantization of the time signal of each Devices to test according to the setpoint frequency signal
The TDC digital quantization value of value and reference time signal, wherein the reference time signal is for outside reference time signal or originally
Ground reference time signal.
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| CN110618604A (en) * | 2019-09-20 | 2019-12-27 | 上海东土远景工业科技有限公司 | Method and device for improving time keeping precision by using NTP auxiliary source |
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