WO2021253339A1

WO2021253339A1 - Method and apparatus for synchronization source selection

Info

Publication number: WO2021253339A1
Application number: PCT/CN2020/096864
Authority: WO
Inventors: Yao PENG; Jun Wang; Wenlong Wang; Qiang Fu
Original assignee: Telefonaktiebolaget Lm Ericsson (Publ); Yao PENG
Priority date: 2020-06-18
Filing date: 2020-06-18
Publication date: 2021-12-23

Abstract

The present disclosure provides a method (200) for synchronization source selection. The method (200) includes: detecting (210) a transition of a Quality Level, QL, of a synchronization source candidate from a first level to a second level; starting (220) a timer in response to the transition; and refraining (230) from selecting the synchronization source candidate as a synchronization source before expiry of the timer.

Description

METHOD AND APPARATUS FOR SYNCHRONIZATION SOURCE SELECTION

TECHNICAL FIELD

The present disclosure relates to communication technology, and more particularly, to a method and an apparatus for synchronization source selection.

BACKGROUND

A proper synchronization is fundamental to correct operation of communication networks. Since the emergence of Synchronous Digital Hierarchy (SDH) , synchronization techniques have become more and more important. Especially with the development of the 5 ^th Generation (5G) communication system, the requirements on synchronization become much stricter. Synchronization is considered as a key enabler for the 5G, as well as a fundamental component of new radio access technologies. In addition, synchronization is also of increased importance in machine type communications (industrial automation, smart grids, automotive and other critical applications, etc. ) , data centers, network analytics, and finance.

That is, it is critical to distribute accurate and reliable synchronization information throughout a network. There are typically two types of synchronization that are required in a radio backhaul network, frequency synchronization and timing/phase synchronization.

Frequency synchronization is a process that adjusts a relative frequency of one or more signals based on a frequency reference of another signal. The accuracy required for frequency synchronization in the radio backhaul network air interface is less than 50 pulses per billion (ppb) .

For the frequency synchronization, International Telecommunication Union -Telecommunications Standardization Sector (ITU-T) G. 781, Synchronization Layer Function, September 2008, which is incorporated herein by reference in its entirety, defines atomic functions that are part of two synchronization layers, a Synchronization Distribution (SD) layer and a Network Synchronization (NS) layer. It also defines some atomic functions, part of a transport layer, which are related to synchronization.

Synchronization source (or referred to as clock source in this context) selection is defined in Section 5.6 of ITU-T G. 781. The selection process is based on one or more of the following factors of a synchronization source: a signal failure condition, a Quality Level (QL) , and a priority. Fig. 1 shows an example of synchronization source selection. As shown, Clock 120 has two input sources, Clock 110 and Clock 112. It is assumed here that Clock 110 has a higher priority than Clock 112. In this case, when Clock 110 and Clock 112 have the same QL, Clock 120 will select Clock 110 as its clock source. On the other hand, when Clock 112 has a higher QL than Clock 110, Clock 120 will select Clock 112 as its clock source. Clock 120 may in turn serve as a synchronization source for Clock 130.

SUMMARY

If a QL of a synchronization source (e.g.,

Clock

110 or 112 in Fig. 1) varies frequently (e.g., due to loss and recovery of an upstream synchronization source) , the selected synchronization source for a G. 781 clock (e.g., Clock 120 in Fig. 1) may be changed frequently. In the example shown in Fig. 1, when Clock 110 and Clock 112 have the same QL (e.g., QL-PRC (Primary Reference Clock) ) , Clock 120 will select Clock 110 (having the higher priority) as its clock source. If the QL of Clock 110 changes from QL-PRC to QL-SSU-B (secondary level Synchronization Supply Unit (SSU) ) , e.g., due to loss of synchronization with its upstream clock, Clock 120 will change its clock source to Clock 112. Then if Clock 110's synchronization with its upstream clock recovers and its QL changes from QL-SSU-B to QL-PRC, Clock 120 will change its clock source back to Clock 110. If the QL of Clock 110 changes frequently, the selected synchronization source for Clock 120 may be changed frequently. If Clock 120 is used as a physical layer, or Layer 1 (L1) , assistance for an ITU-T G. 8275.1 Precision Time Protocol (PTP) clock (e.g., Clock 130 in Fig. 1) , such frequent changes may degrade the accuracy of the time/phase synchronization of the PTP clock, which may be disturbing.

ITU-T G. 781 defines a wait to restore timer which applies when a synchronization source signal recovers from a failure condition. The wait to restore timer ensures that a previous failed synchronization source is only again considered as available by the selection process if it is fault-free for a certain time. In a QL-enabled mode, after a QL of a synchronization source changes from QL-FAILED to any other value, the QL value shall be different from QL-FAILED for the wait to restore time before the new QL value is passed to the selection process.

However, if a QL of a synchronization source changes from a value different from QL-FAILED to any other value different from QL-FAILED, the new QL value will be passed to the selection process immediately, which may cause frequent changes in the selected synchronization source, as described above.

It is an object of the present disclosure to provide a method and an apparatus for synchronization source selection, capable of avoiding such frequent changes in the selected synchronization source.

According to a first aspect of the present disclosure, a method for synchronization source selection is provided. The method includes: detecting a transition of a QL of a synchronization source candidate from a first level to a second level; starting a timer in response to the transition; and refraining from selecting the synchronization source candidate as a synchronization source before expiry of the timer.

In an embodiment, each of the first level and the second level may be different from a failed level.

In an embodiment, the operation of refraining may include: removing the synchronization source candidate from a set of synchronization source candidates for synchronization source selection.

In an embodiment, the method may further include: adding the synchronization source candidate to the set after the expiry of the timer.

In an embodiment, the method may further include, before the expiry of the timer: restarting the timer in response to detecting a further transition of the QL of the synchronization source candidate from the second level to a third level. The third level may be different from a failed level.

In an embodiment, the timer may be a wait to restore timer.

In an embodiment, the synchronization source selection may be for frequency synchronization.

In an embodiment, the method may further include: providing a frequency-synchronized signal source for time and/or phase synchronization.

According to a second aspect of the present disclosure, an apparatus for synchronization source selection is provided. The apparatus includes a processor and a memory. The memory contains instructions executable by the processor whereby the apparatus is operative to perform the method according to the above first aspect.

According to a third aspect of the present disclosure, a computer readable storage medium is provided. The computer readable storage medium has computer program instructions stored thereon. The computer program instructions, when executed by a processor in an apparatus, causing the apparatus to perform the method according to the above first aspect.

With the embodiments of the present disclosure, a timer can be started in response to detecting a transition of a QL of a synchronization source candidate from a first level to a second level is detected. As a consequence, the synchronization source candidate will not be selected as a synchronization source before expiry of the timer. That is, once the QL of the synchronization source candidate changes, the QL should be stable (unchanged) for at least a defined time period before the synchronization source candidate can be considered as available for synchronization source selection. In this way, even if the QL of the synchronization source candidate changes frequently, the output of the synchronization source selection process, i.e., the selected synchronization source will not be changed frequently.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects, features and advantages will be more apparent from the following description of embodiments with reference to the figures, in which:

Fig. 1 is a schematic diagram showing an example of synchronization source selection;

Fig. 2 is a flowchart illustrating a method for synchronization source selection according to an embodiment of the present disclosure;

Fig. 3 is a block diagram of an apparatus for synchronization source selection according to an embodiment of the present disclosure; and

Fig. 4 is a block diagram of an apparatus according to another embodiment of the present disclosure.

DETAILED DESCRIPTION

References in the specification to "one embodiment, " "an embodiment, " "an example embodiment, " and the like indicate that the embodiment described may include a particular feature, structure, or characteristic, but it is not necessary that every embodiment includes the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to affect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.

It shall be understood that although the terms "first" and "second" etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and similarly, a second element could be termed a first element, without departing from the scope of example embodiments. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed terms.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be liming of example embodiments. As used herein, the singular forms "a" , "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" , "comprising" , "has" , "having" , "includes" and/or "including" , when used herein, specify the presence of stated features, elements, and/or components etc., but do not preclude the presence or addition of one or more other features, elements, components and/or combinations thereof.

In the following description and claims, unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skills in the art to which this disclosure belongs.

Fig. 2 is a flowchart illustrating a method 200 for synchronization source selection according to an embodiment of the present disclosure. The method 200 can be performed at a Network Equipment (NE) , e.g., Clock 120 of Fig. 1. The synchronization source selection may be used for frequency synchronization source, e.g., in accordance with ITU-T G. 781.

At block 210, a transition of a QL of a synchronization source candidate from a first level to a second level is detected. For example, the QL can be indicated in an Ethernet Synchronization Messaging Channel (ESMC) message from the synchronization source candidate.

As used herein, a “synchronization source candidate” is an input source that is considered to be available and has not been selected in the synchronization source selection. In other words, a set of synchronization source candidates constitute a “pool” from which a synchronization source can be selected.

In an example, each of the first level and the second level is different from a failed level (e.g., QL-FAILED) . When the first level is QL-FAILED, the wait to restore timer defined in ITU-T G. 781 applies. When the second level is QL-FAILED, the synchronization source candidate becomes unavailable and is no longer a candidate.

At block 220, a timer is started in response to the transition. In particular, the timer can be the wait to restore timer defined in ITU-T G. 781 (i.e., the wait to restore timer can be reused in the present disclosure) , or can be a newly defined timer.

At block 230, the NE refrains from selecting the synchronization source candidate as a synchronization source before expiry of the timer.

In particular, in the block 230, the synchronization source candidate can be removed from a set of synchronization source candidates for synchronization source selection, i.e., from the “pool” as described above. After the expiry of the timer, the synchronization source candidate can be added to the set (pool) again.

In an example, before the expiry of the timer, the timer may be restarted in response to detecting a further transition of the QL of the synchronization source candidate from the second level to a third level. The third level may be different from the failed level (e.g., QL-FAILED) . For example, each time when the QL changes to a level different from QL-FAILED while the timer is running, the timer can be restarted. When the third level is QL-FAILED, the synchronization source candidate becomes unavailable and is no longer a candidate.

In an example, the NE may provide a frequency-synchronized signal source for time and/or phase synchronization, e.g., for a PTP clock.

Correspondingly to the method 200 as described above, an apparatus for synchronization source selection is provided. Fig. 3 is a block diagram of an apparatus 300 for synchronization source selection according to an embodiment of the present disclosure. The apparatus 300 can be, or can be implemented in, an NE, e.g., Clock 120 in Fig. 1.

The apparatus 300 can be configured to perform the method 200 as described above in connection with Fig. 2. As shown in Fig. 3, the apparatus 300 includes a detection unit 310 configured to detect a transition of a QL of a synchronization source candidate from a first level to a second level. The apparatus 300 further includes a control unit 320 configured to start a timer in response to the transition. The apparatus 300 further includes a selection unit 330 configured to refrain from selecting the synchronization source candidate as a synchronization source before expiry of the timer.

In an embodiment, the selection unit 330 may be configured to refrain from selecting the synchronization source candidate by: removing the synchronization source candidate from a set of synchronization source candidates for synchronization source selection.

In an embodiment, the selection unit 330 may be further configured to add the synchronization source candidate to the set after the expiry of the timer.

In an embodiment, the control unit 320 may be further configured to, before the expiry of the timer: restart the timer in response to detecting (by the detection unit 310) a further transition of the QL of the synchronization source candidate from the second level to a third level. The third level may be different from a failed level.

In an embodiment, the timer may be a wait to restore timer.

In an embodiment, the apparatus may provide a frequency-synchronized signal source for time and/or phase synchronization.

The

above units

310, 320 and 330 can be implemented as a pure hardware solution or as a combination of software and hardware, e.g., by one or more of: a processor or a micro-processor and adequate software and memory for storing of the software, a Programmable Logic Device (PLD) or other electronic component (s) or processing circuitry configured to perform the actions described above, and illustrated, e.g., in Fig. 2.

Fig. 4 is a block diagram of an apparatus 400 for synchronization source selection according to another embodiment of the present disclosure. The apparatus 400 can be, or can be implemented in, an NE, e.g., Clock 120 in Fig. 1.

The apparatus 400 includes a processor 410 and a memory 420. The memory 420 can contain instructions executable by the processor 410 whereby the apparatus 400 is operative to perform the actions, e.g., of the procedure described earlier in conjunction with Fig. 2. Particularly, the memory 420 can contain instructions executable by the processor 410 whereby the apparatus 400 is operative to: detect a transition of a QL of a synchronization source candidate from a first level to a second level; start a timer in response to the transition; and refrain from selecting the synchronization source candidate as a synchronization source before expiry of the timer.

In an embodiment, the memory 420 may further contain instructions executable by the processor 410 whereby the apparatus 400 is operative to: add the synchronization source candidate to the set after the expiry of the timer.

In an embodiment, the memory 420 may further contain instructions executable by the processor 410 whereby the apparatus 400 is operative to, before the expiry of the timer: restart the timer in response to detecting a further transition of the QL of the synchronization source candidate from the second level to a third level. The third level may be different from a failed level.

In an embodiment the timer may be a wait to restore timer.

In an embodiment the synchronization source selection may be for frequency synchronization.

In an embodiment the memory 420 may further contain instructions executable by the processor 410 whereby the apparatus 400 is operative to: provide a frequency-synchronized signal source for time and/or phase synchronization.

The present disclosure also provides at least one computer program product in the form of a non-volatile or volatile memory, e.g., a non-transitory computer readable storage medium, an Electrically Erasable Programmable Read-Only Memory (EEPROM) , a flash memory and a hard drive. The computer program product includes a computer program. The computer program includes: code/computer readable instructions, which when executed by the processor 410 causes the apparatus 400 to perform the actions, e.g., of the procedure described earlier in conjunction with Fig. 2.

The computer program product may be configured as a computer program code structured in computer program modules. The computer program modules could essentially perform the actions of the flow illustrated in Fig. 2.

The processor may be a single CPU (Central Processing Unit) , but could also comprise two or more processing units. For example, the processor may include general purpose microprocessors; instruction set processors and/or related chips sets and/or special purpose microprocessors such as Application Specific Integrated Circuits (ASICs) . The processor may also comprise board memory for caching purposes. The computer program may be carried by a computer program product connected to the processor. The computer program product may comprise a non-transitory computer readable storage medium on which the computer program is stored. For example, the computer program product may be a flash memory, a Random Access Memory (RAM) , a Read-Only Memory (ROM) , or an EEPROM, and the computer program modules described above could in alternative embodiments be distributed on different computer program products in the form of memories.

The disclosure has been described above with reference to embodiments thereof. It should be understood that various modifications, alternations and additions can be made by those skilled in the art without departing from the spirits and scope of the disclosure. Therefore, the scope of the disclosure is not limited to the above particular embodiments but only defined by the claims as attached.

Claims

A method (200) for synchronization source selection, comprising:

detecting (210) a transition of a Quality Level, QL, of a synchronization source candidate from a first level to a second level;

starting (220) a timer in response to the transition; and

refraining (230) from selecting the synchronization source candidate as a synchronization source before expiry of the timer.
The method (200) of claim 1, wherein each of the first level and the second level is different from a failed level.
The method (200) of claim 1 or 2, wherein said refraining (230) comprises: removing the synchronization source candidate from a set of synchronization source candidates for synchronization source selection.
The method (200) of claim 3, further comprising:

adding the synchronization source candidate to the set after the expiry of the timer.
The method (200) of any of claims 1-4, further comprising, before the expiry of the timer:

restarting the timer in response to detecting a further transition of the QL of the synchronization source candidate from the second level to a third level,

wherein the third level is different from a failed level.
The method (200) of any of claims 1-5, wherein the timer is a wait to restore timer.
The method (200) of any of claims 1-6, wherein the synchronization source selection is for frequency synchronization.
The method (200) of claim 7, further comprising:

providing a frequency-synchronized signal source for time and/or phase synchronization.
An apparatus (400) for synchronization source selection, comprising a processor (410) and a memory (420) , the memory (420) comprising instructions executable by the processor (410) whereby the apparatus (400) is operative to perform the method according to any of claims 1-8.
A computer readable storage medium having computer program instructions stored thereon, the computer program instructions, when executed by a processor in an apparatus, causing the apparatus to perform the method according to any of claims 1-8.