CN114172607B - Synchronization device and synchronization method between main clock and standby clock - Google Patents
Synchronization device and synchronization method between main clock and standby clock Download PDFInfo
- Publication number
- CN114172607B CN114172607B CN202111471797.XA CN202111471797A CN114172607B CN 114172607 B CN114172607 B CN 114172607B CN 202111471797 A CN202111471797 A CN 202111471797A CN 114172607 B CN114172607 B CN 114172607B
- Authority
- CN
- China
- Prior art keywords
- clock
- frequency
- data
- phase
- backup
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
The invention discloses a synchronization device and a synchronization method between a main clock and a standby clock, wherein the device comprises a working clock, a time interval counter, a data processing and control unit, a phase fine tuning instrument and a backup clock which are sequentially connected, wherein the time interval counter is also connected with the phase fine tuning instrument, the method is that 1PPS output by a signal of the backup clock after passing through the phase fine tuning instrument and 1PPS of the working clock are subjected to clock difference measurement through the time interval counter, the phase deviation delta T of the backup clock relative to the working clock is obtained, the frequency compensation delta P added to the backup clock is calculated, and the compensation is fed back to the phase fine tuning instrument to carry out frequency control on the backup clock, so that high-precision frequency and phase synchronization between the working clock and the backup clock are realized. The synchronization device has low cost and high synchronization precision, the method has strong practicability, can realize high-precision frequency and phase synchronization between the main clock and the standby clock, and can ensure the phase synchronization precision between the main clock and the standby clock and improve the long-term frequency stability of the standby clock.
Description
Technical Field
The invention relates to a time frequency synchronization technology, in particular to a synchronization device and a synchronization method between a main clock and a standby clock.
Background
The time is one of 7 basic units in the current international unit system, and the definition and measurement of the time are one basic unit with the longest history, the most complex condition and the highest measurement precision. Time measurement permeates various fields of human activities, scientific experiments and national construction, and various timers, computers, data transmission, telephone faxes and the like are all independent of stable clock frequencies. Communication, telecommunications, positioning, navigation, mapping, energy, etc., the efficiency and quality of which depend largely on high precision time-frequency services. Along with the development of national economy, national defense construction and space technology in China, higher and higher requirements are put forward on the accuracy, stability and reliability of high-precision time-frequency service.
The time-frequency reference station has higher requirement on time synchronization reliability, and is provided with a backup clock besides a working clock, the working clock and the backup clock need to keep high-precision frequency and phase synchronization, and at present, the common practice is that the working clock and the backup clock both adopt a hydrogen atomic clock with smaller noise or a cesium atomic clock with better long-term stability, but the hydrogen atomic clock and the cesium atomic clock are large in volume and high in price.
Disclosure of Invention
The invention aims at overcoming the defects of the prior art and provides a synchronization device and a synchronization method between a main clock and a standby clock. The synchronization device has low cost and high synchronization precision, the method has strong practicability, can realize high-precision frequency and phase synchronization between the main clock and the standby clock, and can ensure the phase synchronization precision between the main clock and the standby clock and improve the long-term frequency stability of the standby clock.
The technical scheme for realizing the aim of the invention is as follows:
the synchronization device between the main clock and the standby clock comprises a working clock, a time interval counter, a data processing and control unit, a phase fine tuning instrument and a standby clock which are sequentially connected, wherein the time interval counter is also connected with the phase fine tuning instrument, and the working clock adopts a Cesiclock OSA3235B and has good long-term stability; the backup clock adopts a commodity rubidium clock FS725, the noise is small, the 1PPS output by the 10MHz signal of the backup clock after passing through a phase fine tuning instrument HROG-10 and the 1PPS of the working clock are subjected to clock difference measurement through a time interval counter SR620, and after the measurement result is analyzed by a data processing and control module, the frequency and phase control is carried out on the backup clock, so that the real-time phase synchronization between the working clock and the backup clock is realized.
The operating clock is cesium clock OSA3235B, the frequency stability of the cesium clock OSA3235B when tau=1s is less than 1.2X10-11 and the frequency stability of the cesium clock OSA3235B when tau=100 s is less than 2.7X10-12, wherein tau represents that when the frequency stability is calculated by using the Allan variance, the frequency deviation is calculated every τsecond.
The backup clock is a rubidium clock FS725, the frequency stability of the rubidium clock FS725 is smaller than 2 x 10 (-11), and the frequency stability of the rubidium clock FS725 is smaller than 2 x 10 (-12).
The time interval counter is SR620, SR620 is a special time interval measuring instrument, the resolution of measurement reaches 25ps, and the time interval between two 1PPS signals is the typical application scene of SR 620.
The phase fine tuning instrument is HROG-10, the HROG-10 is a high-resolution phase frequency compensator, the step of phase compensation is 0.3fs, the step of frequency compensation is 5 x 10 (-19), the frequency and phase compensation of an input frequency signal are realized, the input of a 10MHz sinusoidal signal and the 1PPS signal output of TTL level are supported, and a fixed phase deviation is kept between the input signal and the output signal.
The data processing and controlling unit adopts a computer terminal and a Windows system, the computer terminal collects clock difference data of the working clock and the backup clock from SR620 through a 232 serial port, filters, predicts and calculates the compensation quantity of the collected clock difference data, and finally feeds the compensation quantity back to the phase fine tuning instrument HROG-10 through the 232 serial port.
The method is that 1PPS output by a 10MHZ signal of a backup clock after passing through a phase fine tuning instrument HROG-10 and 1PPS of a working clock are subjected to clock difference measurement through a time interval counter SR620, the phase deviation delta T of the backup clock relative to the working clock is obtained after the measurement result is processed by a data processing and control unit, the frequency compensation delta P added to the backup clock is calculated, and the compensation is fed back to the phase fine tuning instrument HROG-10 to carry out frequency control on the backup clock, so that high-precision frequency and phase synchronization between the working clock and the backup clock is realized, wherein the processing of the data processing and control unit comprises the following steps: preprocessing data, predicting clock error, calculating frequency offset and calculating frequency compensation quantity, and specifically comprises the following steps:
1) Data preprocessing: the preprocessing is to reject coarse data, the coarse data is rejected by adopting a3 sigma criterion, and let y1, y2, y3, … and yn represent N clock difference data acquired at the moments x1, x2, x3 … and xn, wherein the change of the clock difference is a linear process, and the linear relation among the clock difference data is recorded as follows: y=ax+b, the pretreatment flow is: every time 150 clock difference data are collected by the system, fitting the 150 clock difference data by using a least square method, traversing whether the 150 data are in a reasonable deviation range of a3 sigma criterion, replacing the 150 data by a predicted value which is not in the range, and re-fitting the 150 data until the 150 data are processed, and solving a slope a and an intercept b in a clock difference curve y=ax+b;
2) And (3) predicting clock difference and calculating frequency deviation: the method is characterized in that the clock error prediction is carried out by adopting a model of a first-order polynomial, essentially, a power function is used as a fitting function to fit clock error time series data with equal time intervals, the identification parameters are a0 (b in pretreatment) and a1 (a in pretreatment), the values of a0 and a1 are obtained according to a least square estimation principle, and the relation between time difference data delta T and system time T is represented by the first-order polynomial, namely:
ΔT＝a 0 +a 1 (t-t 0 ) (1)，
set relative to time t 1 ,t 2 ,…,t n The clock differences of (2) are respectively: x is x 1 ,x 2 ,…,x n Measurement error v i The equation (1) establishes the clock difference equation:
x i +v i ＝a 0 +a 1 (t i -t 0 ) (2)，
is provided with
A is respectively 0 And a 1 The estimated values of (2) are:
recording according to least square estimation principle
Let->
Then estimate the value
Wherein n is the number of clock difference data, delta t i ＝t i -t 0 The current predicted frequency offset value
Current predictive clock difference +.>
When the first-order polynomial fitting method is used for predicting the clock error, the difference between the predicted value and the measured data is within 0.3ns, and the difference is mainly caused by random walk noise and phase white noise;
3) Calculating a frequency compensation amount: the frequency compensation quantity is calculated and is determined together according to the values of the predicted clock difference delta T and the frequency offset delta f, and the clock difference predicted value of the next control moment under the current clock difference and frequency offset state is calculated:
nextΔT＝ΔT+T×Δf
next Δt is a calculated value, which indicates a predicted value of a clock difference between the backup clock and the main clock after 150s under the current frequency offset,
dividing the next delta T into intervals, adding different frequency and phase compensation amounts to the backup clock in different intervals, wherein the compensation method is as follows:
the synchronization device has low cost and high synchronization precision, the method has strong practicability, can realize high-precision frequency and phase synchronization between the main clock and the standby clock, and can ensure the phase synchronization precision between the main clock and the standby clock and improve the long-term frequency stability of the standby clock.
Drawings
FIG. 1 is a schematic diagram of an embodiment;
FIG. 2 is a schematic diagram of a data preprocessing flow in an embodiment;
FIG. 3 is a diagram illustrating the partitioning of next ΔT intervals according to an embodiment;
FIG. 4 is a schematic diagram of clock skew between a backup clock and a master clock in free running operation in an embodiment;
FIG. 5 is a schematic diagram of clock skew of a master clock and a slave clock using the apparatus of the present example;
FIG. 6 is a graph showing the comparison of the frequency stability curves before and after the backup clock compensation in the embodiment.
Detailed Description
The present invention will now be further illustrated, but not limited, by the following figures and examples.
Examples:
referring to fig. 1, a synchronization device between a main clock and a standby clock comprises a working clock, a time interval counter, a data processing and control unit, a phase fine tuning instrument and a standby clock which are sequentially connected, wherein the time interval counter is also connected with the phase fine tuning instrument, and the working clock adopts an OSA3235B clock, so that the working clock has better long-term stability; the backup clock adopts a commodity rubidium clock FS725, the noise is small, the 1PPS output by the 10MHz signal of the backup clock after passing through a phase fine tuning instrument HROG-10 and the 1PPS of the working clock are subjected to clock difference measurement through a time interval counter SR620, and after the measurement result is analyzed by a data processing and control module, the frequency and phase control is carried out on the backup clock, so that the real-time phase synchronization between the working clock and the backup clock is realized.
The operating clock is cesium clock OSA3235B, the frequency stability of the cesium clock OSA3235B when tau=1s is less than 1.2X10-11 and the frequency stability of the cesium clock OSA3235B when tau=100 s is less than 2.7X10-12, wherein tau represents that when the frequency stability is calculated by using the Allan variance, the frequency deviation is calculated every τsecond.
The backup clock is a rubidium clock FS725, the frequency stability of the rubidium clock FS725 is smaller than 2 x 10 (-11), and the frequency stability of the rubidium clock FS725 is smaller than 2 x 10 (-12).
The time interval counter is SR620, SR620 is a special time interval measuring instrument, the resolution of measurement reaches 25ps, and the time interval between two 1PPS signals is the typical application scene of SR 620.
The phase fine tuning instrument is HROG-10, the HROG-10 is a high-resolution phase frequency compensator, the step of phase compensation is 0.3fs, the step of frequency compensation is 5 x 10 (-19), the frequency and phase compensation of an input frequency signal are realized, the input of a 10MHz sinusoidal signal and the 1PPS signal output of TTL level are supported, and a fixed phase deviation is kept between the input signal and the output signal.
The data processing and controlling unit adopts a computer terminal and a Windows system, the computer terminal collects clock difference data of the working clock and the backup clock from SR620 through a 232 serial port, filters, predicts and calculates the compensation quantity of the collected clock difference data, and finally feeds the compensation quantity back to the phase fine tuning instrument HROG-10 through the 232 serial port.
The method is that 1PPS output by a 10MHZ signal of a backup clock after passing through a phase fine tuning instrument HROG-10 and 1PPS of a working clock are subjected to clock difference measurement through a time interval counter SR620, the phase deviation delta T of the backup clock relative to the working clock is obtained after the measurement result is processed by a data processing and control unit, the frequency compensation delta P added to the backup clock is calculated, and the compensation is fed back to the phase fine tuning instrument HROG-10 to carry out frequency control on the backup clock, so that high-precision frequency and phase synchronization between the working clock and the backup clock is realized, wherein the processing of the data processing and control unit comprises the following steps: preprocessing data, predicting clock error, calculating frequency offset and calculating frequency compensation quantity, and specifically comprises the following steps:
1) Data preprocessing: the preprocessing is to reject coarse data, the coarse data is rejected by adopting a3 sigma criterion, and let y1, y2, y3, … and yn represent N clock difference data acquired at the moments x1, x2, x3 … and xn, wherein the change of the clock difference is a linear process, and the linear relation among the clock difference data is recorded as follows: y=ax+b, the pretreatment flow is as shown in fig. 2: every time 150 clock difference data are collected by the system, fitting the 150 clock difference data by using a least square method, traversing whether the 150 data are in a reasonable deviation range of a3 sigma criterion, replacing the 150 data by a predicted value which is not in the range, and re-fitting the 150 data until the 150 data are processed, and solving a slope a and an intercept b in a clock difference curve y=ax+b;
2) And (3) predicting clock difference and calculating frequency deviation: the method is characterized in that the clock error prediction is carried out by adopting a model of a first-order polynomial, essentially, a power function is used as a fitting function to fit clock error time series data with equal time intervals, the identification parameters are a0 (b in pretreatment) and a1 (a in pretreatment), the values of a0 and a1 are obtained according to a least square estimation principle, and the relation between time difference data delta T and system time T is represented by the first-order polynomial, namely:
ΔT＝a 0 +a 1 (t-t 0 ) (1)，
set relative to time t 1 ,t 2 ,…,t n The clock differences of (2) are respectively: x is x 1 ,x 2 ,…,x n Measurement error v i The equation (1) establishes the clock difference equation:
x i +v i ＝a 0 +a 1 (t i -t 0 ) (2)，
is provided with
A is respectively 0 And a 1 The estimated values of (2) are:
recording according to least square estimation principle
Let->
Then estimate the value
Wherein n is the number of clock difference data, delta t i ＝t i -t 0 The current predicted frequency offset value
Current predictive clock difference +.>
When the first-order polynomial fitting method is used for predicting the clock error, the difference between the predicted value and the measured data is within 0.3ns, and the difference is mainly caused by random walk noise and phase white noise;
3) Calculating a frequency compensation amount: the frequency compensation quantity is calculated and is determined together according to the values of the predicted clock difference delta T and the frequency offset delta f, and the clock difference predicted value of the next control moment under the current clock difference and frequency offset state is calculated:
nextΔT＝ΔT+T×Δf
next Δt is a calculated value, which indicates a predicted value of a clock difference between the backup clock and the main clock after 150s under the current frequency offset,
as shown in fig. 3, the next Δt is divided into intervals, and different frequency and phase compensation amounts are added to the backup clock in different intervals, and the compensation method is as follows:
before the frequency of the backup clock is controlled, a real-time clock difference curve between the backup clock and the main clock is shown in fig. 4, and the clock difference of 8 hours can reach 60ns; after the frequency control is carried out on the backup clock, a real-time clock difference curve between the backup clock and the working clock is shown in fig. 5, after the frequency and the phase control are carried out for 8 hours, the real-time phase synchronization precision between the backup clock and the working clock is +/-0.8 ns, and the fact that the synchronization system can effectively keep the consistency of the phase between the main clock and the backup clock when the frequency control of the backup clock is carried out is proved, in the embodiment, theta=1ns is taken, the real-time phase synchronization precision between the main clock and the backup clock can reach +/-0.8 ns, and after the phase and the frequency compensation is carried out on the backup clock, the long-term frequency stability of the backup clock is effectively improved.
Claims (5)
1. The method is characterized in that the method is applied to a synchronization device between a main clock and a standby clock, wherein the synchronization device between the main clock and the standby clock comprises a working clock, a time interval counter, a data processing and control unit, a phase trimming instrument and a backup clock which are sequentially connected, the time interval counter is also connected with the phase trimming instrument, 1PPS output by a 10MHz signal of the backup clock after passing through the phase trimming instrument HROG-10 and 1PPS of the working clock are subjected to clock difference measurement through the time interval counter SR620, the phase deviation delta T of the backup clock relative to the working clock is obtained after the measurement result is processed by the data processing and control unit, the frequency compensation quantity delta P added to the backup clock is calculated, and the compensation quantity is fed back to the phase trimming instrument HROG-10 to carry out frequency control on the backup clock, so that high-precision frequency and phase synchronization between the working clock and the backup clock are realized, and the processing of the data processing and control unit comprises the steps of: preprocessing data, predicting clock error, calculating frequency offset and calculating frequency compensation quantity, and specifically comprises the following steps:
1) Data preprocessing: the preprocessing is to reject coarse data, the coarse data is rejected by adopting a3 sigma criterion, and let y1, y2, y3, … and yn represent N clock difference data acquired at the moments x1, x2, x3 … and xn, wherein the change of the clock difference is a linear process, and the linear relation among the clock difference data is recorded as follows: y=ax+b, the pretreatment flow is: every time 150 clock difference data are collected by the system, fitting the 150 clock difference data by using a least square method, traversing whether the 150 data are in a reasonable deviation range of a3 sigma criterion, replacing the 150 data by a predicted value which is not in the range, and re-fitting the 150 data until the 150 data are processed, and solving a slope a and an intercept b in a clock difference curve y=ax+b;
2) And (3) predicting clock difference and calculating frequency deviation: the method is characterized in that the clock error prediction is carried out by adopting a model of a first-order polynomial, a power function is used as a fitting function to fit clock error time series data with equal time intervals, the identification parameters are a0 (b in pretreatment) and a1 (a in pretreatment), the values of a0 and a1 are obtained according to a least square estimation principle, and the relation between time difference data delta T and system time T is represented by the first-order polynomial, namely:
ΔT＝a 0 +a 1 (t-t 0 )(1)，
set relative to time t 1 ,t 2 ,…,t n The clock differences of (2) are respectively: x is x 1 ,x 2 ,…,x n The measurement error is v i The equation (1) establishes the clock difference equation:
x i +v i ＝a 0 +a 1 (t i -t 0 )(2)，
is provided with
A is respectively 0 And a 1 The estimated values of (2) are:
recording according to least square estimation principle
Let->
Wherein n is the number of clock difference data, delta t i ＝t i -t 0 The current predicted frequency offset value
Current predictive clock difference +.>
3) Calculating a frequency compensation amount: the frequency compensation quantity is calculated and is determined together according to the values of the predicted clock difference delta T and the frequency offset delta f, and the clock difference predicted value of the next control moment under the current clock difference and frequency offset state is calculated:
nextΔT＝ΔT+T×Δf
next Δt is a calculated value, which indicates a predicted value of a clock difference between the backup clock and the main clock after 150s under the current frequency offset,
dividing the next delta T into intervals, adding different frequency and phase compensation amounts to the backup clock in different intervals, wherein the compensation method is as follows:
2. the method according to claim 1, wherein the operating clock in the synchronization device between the main clock and the standby clock is a bells OSA3235B, the frequency stability of the bells OSA3235B is less than 1.2x10 (-11), and the frequency stability of the bells osa=100 s is less than 2.7x10 (-12), wherein τ represents that when the frequency stability is calculated using the alan variance, the frequency deviation is calculated every τ seconds.
3. The synchronization method between primary and secondary clocks according to claim 1, wherein the backup clock in the synchronization device is a rubidium clock FS725, and the frequency stability of the rubidium clock FS725 is less than 2 x 10 (-11) when τ=1s, and less than 2 x 10 (-12) when τ=100deg.s.
4. The method according to claim 1, wherein the time interval counter in the synchronization device is SR620, and the resolution of SR620 measurement reaches 25ps.
5. The method of claim 1, wherein the phase fine tuning device in the synchronization device is HROG-10, the step of phase compensation of HROG-10 is 0.3fs, the step of frequency compensation is 5 x 10 (-19), the input of 10MHz sinusoidal signal is supported, and the output of 1PPS signal at TTL level is supported, and a fixed phase deviation is maintained between the input and output signals.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111471797.XA CN114172607B (en) | 2021-12-06 | 2021-12-06 | Synchronization device and synchronization method between main clock and standby clock |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111471797.XA CN114172607B (en) | 2021-12-06 | 2021-12-06 | Synchronization device and synchronization method between main clock and standby clock |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114172607A CN114172607A (en) | 2022-03-11 |
| CN114172607B true CN114172607B (en) | 2023-05-02 |
Family
ID=80483051
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111471797.XA Active CN114172607B (en) | 2021-12-06 | 2021-12-06 | Synchronization device and synchronization method between main clock and standby clock |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114172607B (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7860205B1 (en) * | 2001-09-18 | 2010-12-28 | Ciena Corporation | Clock synchronization using a weighted least squares error filtering technique |
| EP3422580A1 (en) * | 2017-06-28 | 2019-01-02 | Analog Devices, Inc. | Apparatus and methods for clock synchronization and frequency translation |
| WO2019177503A1 (en) * | 2018-03-14 | 2019-09-19 | Telefonaktiebolaget Lm Ericsson (Publ) | A method and a first device for clock synchronization |
| CN111416617A (en) * | 2020-03-18 | 2020-07-14 | 广州土圭垚信息科技有限公司 | Clock synchronization method and device and electronic equipment |
| CN111447032A (en) * | 2020-04-10 | 2020-07-24 | 中国科学院精密测量科学与技术创新研究院 | Dynamic high-precision time synchronization device and synchronization method thereof |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8514098B2 (en) * | 2009-04-28 | 2013-08-20 | Schlumberger Technology Corporation | Synchronization between devices |
| KR102013617B1 (en) * | 2015-11-18 | 2019-08-23 | 한국전자통신연구원 | Method and apparatus for synchronizing time |
-
2021
- 2021-12-06 CN CN202111471797.XA patent/CN114172607B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7860205B1 (en) * | 2001-09-18 | 2010-12-28 | Ciena Corporation | Clock synchronization using a weighted least squares error filtering technique |
| EP3422580A1 (en) * | 2017-06-28 | 2019-01-02 | Analog Devices, Inc. | Apparatus and methods for clock synchronization and frequency translation |
| WO2019177503A1 (en) * | 2018-03-14 | 2019-09-19 | Telefonaktiebolaget Lm Ericsson (Publ) | A method and a first device for clock synchronization |
| CN111416617A (en) * | 2020-03-18 | 2020-07-14 | 广州土圭垚信息科技有限公司 | Clock synchronization method and device and electronic equipment |
| CN111447032A (en) * | 2020-04-10 | 2020-07-24 | 中国科学院精密测量科学与技术创新研究院 | Dynamic high-precision time synchronization device and synchronization method thereof |
Non-Patent Citations (3)
| Title |
|---|
| Eui-Jik KIM ; Jeongsik IN ; Sungkwan YOUM ; Chul-Hee KANG.Delay Attack-Resilient Clock Synchronization for Wireless Sensor Networks.IEICE Transactions on Information and Systems.2012,第D卷(第1期),全文. * |
| 张先富 ; 冯冬芹 ; .基于加权最小二乘法的精确时钟同步算法研究与实现.传感技术学报.2008,(第09期),全文. * |
| 鲜鸿宇 ; 邓蕾 ; 汤宝平 ; 肖鑫.基于晶振偏移补偿的机械振动WSN同步累积误差抑制方法.振动与冲击.2019,(第006期),全文. * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114172607A (en) | 2022-03-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7548600B2 (en) | Apparatus and method for compensating the drift of a local clock used as sampling frequency | |
| CN101068128B (en) | Method for time synchronization in distributed control system | |
| CN109581856B (en) | Time synchronization and time keeping method based on high-performance crystal oscillator frequency calibration | |
| US10533882B2 (en) | Efficient battery-powered modular meter | |
| CN112540388B (en) | Satellite communication module and uplink signal Doppler compensation method thereof | |
| CN109085616B (en) | Satellite time service method, device and storage medium | |
| CN102004441B (en) | Adaptive crystal oscillator frequency timekeeping method | |
| CN108803300B (en) | Time synchronization device timekeeping method and time synchronization device based on constant-temperature crystal oscillator | |
| CN100395682C (en) | 'Beidou No.1' satellite navigation system and GPS mutually preparing time service method and apparatus | |
| CN112433235B (en) | Method, system and medium for determining time reference | |
| CN106527113A (en) | High-precision clock online frequency calibration and timing method based on GPS | |
| CN112636857A (en) | High-precision time-frequency signal dynamic driving method based on residual error correction | |
| CN116032411A (en) | Time stamp synchronization method, system, terminal and storage medium | |
| CN114205045B (en) | TTE network clock calibration method and system | |
| CN116125512A (en) | PPP self-adaptive clock difference model estimation method considering clock frequency time-varying characteristics | |
| CN114172607B (en) | Synchronization device and synchronization method between main clock and standby clock | |
| CN110618604B (en) | Method and device for improving time keeping precision by using NTP auxiliary source | |
| WO2019176660A1 (en) | Time synchronization system, management device, time synchronization method, and program | |
| CN109274366A (en) | The clock test instrument and clock test methodology of distribution terminal | |
| CN116133107A (en) | Synchronization method of accurate synchronous acquisition system of multiple acquisition stations based on 5G | |
| EP3732806B1 (en) | Method, device and system for estimating offset skew and drift | |
| CN115580922A (en) | Time keeping method and system based on base station time service | |
| CN118174718A (en) | Crystal oscillator taming system and method based on satellite time service | |
| CN118092120A (en) | Automatic switching time keeping device and method for multiple master clocks | |
| CN116614129A (en) | Rubidium atomic clock time domain signal stability optimization method and device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |