CN202759413U - An on-line time error correcting system based on a satellite and a constant temperature crystal oscillator - Google Patents
An on-line time error correcting system based on a satellite and a constant temperature crystal oscillator Download PDFInfo
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- CN202759413U CN202759413U CN 201220474718 CN201220474718U CN202759413U CN 202759413 U CN202759413 U CN 202759413U CN 201220474718 CN201220474718 CN 201220474718 CN 201220474718 U CN201220474718 U CN 201220474718U CN 202759413 U CN202759413 U CN 202759413U
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Abstract
The utility model provides an on-line time error correcting system based on a satellite and a constant temperature crystal oscillator. The on-line time error correcting system comprises a constant temperature crystal oscillator, a GPS receiver, a clock module, and a real-time time counting circuit. The clock module comprises a correcting pulse generating circuit, a phase comparison circuit, a frequency dividing coefficient control circuit, a frequency dividing circuit, and a restarting circuit. The GPS receiver outputs an external time reference signal to the correcting pulse generating circuit which outputs a correcting pulse according to the external time reference signal. The phase comparison circuit compares the correcting pulse with a time signal in the system. The frequency dividing coefficient control circuit adjusts the frequency dividing coefficient of the frequency dividing circuit according to the compared result of the phase. The frequency dividing circuit divides the frequency of the crystal oscillator clock signal according to the frequency dividing coefficient in order to acquire the time signal in the system. The restarting circuit restarts a frequency dividing counter in the frequency dividing circuit according to the phase difference between the time signal in the system and the correcting pulse. The frequency dividing circuit is connected with the real-time time counting circuit. The on-line time error correcting system has characteristics of low fluctuation and good long-term stability.
Description
Technical field
The utility model relates to the line duration error and tames system, and particularly tames system relevant for a kind of line duration error based on satellite and constant-temperature crystal oscillator.
Background technology
For the power industry automaticity is more and more higher, the equipment such as protection, communication, telemechanical, monitoring, recording, direct current all need the time high unity, are convenient to the unification of data message, the unification of event time, the unification of accident investigation.During the current power accident analysis requires, travelling wave ranging and traveling-wave protection to the requirement of clock accuracy up to 1us.Be exactly a kind of specially for a kind of algorithm of the time accuracy of power industry based on the taming algorithm of satellite and the online error of constant-temperature crystal oscillator, utilize the long-time stability of satellite time and the short-term stability correction local clock of constant-temperature crystal oscillator, thereby guarantee that the output time accuracy is up to 100ns pulse per second (PPS) (1pps).
Traditional method is by a long-term measurement data being added up, set up a data model, using the synthetic combined control system of multi-disc singlechip group, the time delay of compensation synchro system.But the error that this introduces not having compensation and revising from transmitting terminal to the receiving terminal transmission course.The speed of service of single-chip microcomputer is slow simultaneously, and it is larger to introduce time delay in processing procedure.
The utility model content
For overcoming the defective of above-mentioned prior art, the utility model proposes a kind of taming system of fluctuation line duration error little and good long term stability that has.
For reaching above-mentioned purpose, the utility model proposes a kind of line duration error based on satellite and constant-temperature crystal oscillator and tame system, comprise constant-temperature crystal oscillator, gps receiver, clock module and real-time time counting circuit, clock module comprises correction pulse circuit for generating, phase-comparison circuit, divide ratio control circuit, frequency dividing circuit, restarts circuit, and gps receiver output external time reference signal is to the correction pulse circuit for generating; The correction pulse circuit for generating according to the pulse of external time reference signal output calibration to phase-comparison circuit; The phase place of time signal in the system of the more above-mentioned correction pulse of phase-comparison circuit and constant-temperature crystal oscillator output; The divide ratio control circuit connects above-mentioned phase-comparison circuit and frequency dividing circuit, and the divide ratio control circuit is adjusted the divide ratio of frequency dividing circuit according to the phase place comparative result; Frequency dividing circuit carries out frequency division according to divide ratio to crystal oscillator clock signal, thereby obtains time signal in the system; Restart circuit and connect above-mentioned frequency dividing circuit and restart frequency counter in the frequency dividing circuit according to the phase place comparative result of time signal in the system and correction pulse, the output of frequency dividing circuit connects the real-time time counting circuit.
Further, in the utility model, the system of taming also comprises memory module based on the line duration error of satellite and constant-temperature crystal oscillator, connect above-mentioned divide ratio control circuit, the value of the divide ratio when storing normal operation, when the external time reference signal was all lost, the divide ratio value of output preservation was kept time successively.
The beneficial effects of the utility model are: utilize the long-time stability of satellite and the short-term stability correction local clock of constant-temperature crystal oscillator, thereby guaranteed the accuracy of output time, accuracy height 100ns.
Description of drawings
Fig. 1 be the utility model embodiment tame the theory diagram of system based on the line duration error of satellite and constant-temperature crystal oscillator.
Embodiment
In order more to understand technology contents of the present utility model, especially exemplified by specific embodiment and cooperate appended graphic being described as follows.
Fig. 1 be the utility model embodiment tame the theory diagram of system based on the line duration error of satellite and constant-temperature crystal oscillator.
As shown in Figure 1, based on satellite and the constant-temperature crystal oscillator line duration error system of taming comprise clock module and with the real-time time counting circuit, clock module comprises that correction pulse produces circuit, phase-comparison circuit, divide ratio control circuit, frequency dividing circuit, restarts circuit and storage module.Correction pulse produces circuit, produces a correction pulse ub, and ub is identical with satellite input signal PPS_IN phase place.The phase place of time signal PPS_A is determined divide ratio σ in the correction pulse ub that phase-comparison circuit produces by correcting algorithm relatively and the system.The divide ratio control circuit is the nucleus module of whole logical design, and its Main Function is: eliminate standard deviation and the average of input signal PPS_IN by following the tracks of divide ratio σ, obtain more high-precision pulse per second (PPS).The value of divide ratio σ when storage module (SDRAM) is preserved normal operation, when the external time reference signal was all lost, the divide ratio value of output preservation was kept time successively.Restart circuit and be when crystal oscillator is unsettled and wait for, until crystal oscillator stable after, restart circuit guarantees Systems balanth and reliability.
The below is introduced one by one to foregoing circuit
1) correction pulse circuit for generating
Satellite time signal PPS_IN is the input signal of correction pulse circuit for generating as the external time reference signal, and when the rising edge of external time reference signal arrived, the correction pulse circuit for generating produced a correction pulse ub.The pulse duration of correction pulse ub is much smaller than the cycle of input pulse per second (PPS) PPS_IN, and it is a narrow pulse signal.Correction pulse ub only appears at the initial time of satellite time signal PPS_IN, so can represent the phase place of satellite time signal PPS_IN.
2) phase-comparison circuit
For making the not larger time error of reason crystal oscillator cumulative errors appearance of output time, the phase relation of time signal PPS_A and satellite time signal PPS_IN in the system of necessary constantly detection constant-temperature crystal oscillator output, and according to the phase place of time signal PPS_A in the detection case corrective system, it is too large to make its error be unlikely to accumulation.
Phase-comparison circuit will be finished the phase bit comparison of time signal PPS_A in correction pulse ub and the system.If correction pulse ub appears at the front half period of time signal PPS_A in the system, it is the high level part of time signal PPS_A in the system, the phase place of time signal PPS_A is ahead of the phase place of input pulse per second (PPS) in the illustrative system, if correction pulse ub appears at the later half cycle of time signal PPS_A in the system, namely export the low level part of pulse per second (PPS), the phase place of time signal PPS_A lags behind the phase place of input pulse per second (PPS) in the illustrative system.
3) divide ratio control circuit
The effect of divide ratio control circuit is: according to the phase place comparative result of phase-comparison circuit, adjust the divide ratio σ of frequency dividing circuit.
If the phase place comparative result is the phase place that the phase place of time signal PPS_A in the system is ahead of satellite time signal PPS_IN, then the divide ratio by divide ratio control circuit adjustment frequency dividing circuit is σ+1, at this moment the time signal PPS_A cycle lengthens in the system of frequency dividing circuit, frequency reduces, 1 the high-frequency signal cycle appearance of can delaying time of the rising edge of time signal PPS_A has realized correction or lag in the next system.
Otherwise, if the phase place of time signal PPS_A lags behind the phase place of satellite time signal PPS_IN in the system, the divide ratio of then adjusting frequency dividing circuit is σ-1, in the system of at this moment frequency dividing circuit output the time signal PPS_A cycle shorten, the frequency increase, the rising edge of time signal PPS_A can shift to an earlier date 1 high-frequency signal cycle appearance in the next system, has realized anticipatory control.
4) frequency dividing circuit
The effect of frequency dividing circuit be according to divide ratio σ to the crystal oscillator clock signal frequency division, time signal PPS_A and output time signal PPS_OUT in the generation system.PPS_OUT is the output pulse per second (PPS), and time signal PPS_A is used for internal circuit in the system, and PPS_OUT is the output after PPS_A removes constant offset.
The pulsewidth of time signal PPS_A and output time signal PPS_OUT can be by to pulseWidth[25:0 in the system] setting adjust.
The operation principle of time signal PPS_A pulsewidth setting is in the system: the high-frequency signal of the counter that utilizes frequency dividing circuit after to High Accuracy Constant Temperature crystal oscillator frequency multiplication counted (initial value of counter is 1), (high level lasting time that guarantees crystal oscillator clock second with definite value is about the requirement settings when count value is less than or equal to definite value, when being 100MHz such as crystal oscillator frequency, definite value is set to 20000000, then pulsewidth is 200ms) time, frequency dividing circuit output high level; When count value during greater than definite value, the frequency dividing circuit output low level.When count value equaled divide ratio, frequency dividing circuit output high level put 1 again with the count value of counter simultaneously, and restarts counting.
5) real-time time counting circuit
The real-time time counting circuit is counted output time signal PPS_OUT, can get real-time time information thus.
6) restart circuit
The effect that restarts circuit is: when the phase place difference of time signal PPS_A in the system and correction pulse ub is very large, restart frequency counter, with next pulse per second (PPS) re-synchronization frequency counter; Judge whether crystal oscillator is stable.
System is in cold start-up, the error ratio of constant-temperature crystal oscillator is larger, by restarting module, can judge rapidly whether constant-temperature crystal oscillator is stable, the method of judging is: if the phase difference (200ns) in the scope of appointment of time signal PPS_A and correction pulse ub system in appears in continuous several times (system is set to 20 times), think that then crystal oscillator stablizes, otherwise, think that crystal oscillator is unstable, system restarts.
In addition, when all lose in four external time reference sources, when namely satellite time signal PPS_IN is without input, get first divide ratio that satellite time signal PPS_IN has last divide ratio when inputting to lose as external source.The like, the divide ratio in a period of time (being generally 1 hour) that is stored among the SDRAM is extracted successively as up-to-date divide ratio.If the active drop-out time of outside institute, then will be stored in divide ratio among the SDRAM greater than 1 hour and again read and get final product.Like this, lose even just can guarantee outside all sources, clock module also can be exported the correct time signal.
In sum, the utility model utilizes the long-time stability of satellite and the short-term stability correction local clock of constant-temperature crystal oscillator, thereby has guaranteed the accuracy of output time, accuracy height 100ns.
Although the utility model discloses as above with preferred embodiment, so it is not to limit the utility model.Have in the technical field under the utility model and usually know the knowledgeable, within not breaking away from spirit and scope of the present utility model, when being used for a variety of modifications and variations.Therefore, protection range of the present utility model is as the criterion when looking claims person of defining.
Claims (2)
1. the line duration error based on satellite and constant-temperature crystal oscillator is tamed system, it is characterized in that, comprise: constant-temperature crystal oscillator, gps receiver, clock module and real-time time counting circuit, clock module comprises correction pulse circuit for generating, phase-comparison circuit, divide ratio control circuit, frequency dividing circuit, restarts circuit, and gps receiver output external time reference signal is to the correction pulse circuit for generating; The correction pulse circuit for generating according to the pulse of external time reference signal output calibration to phase-comparison circuit; The phase place of time signal in the system of the more above-mentioned correction pulse of phase-comparison circuit and constant-temperature crystal oscillator output; The divide ratio control circuit connects above-mentioned phase-comparison circuit and frequency dividing circuit, and the divide ratio control circuit is adjusted the divide ratio of frequency dividing circuit according to the phase place comparative result; Frequency dividing circuit carries out frequency division according to divide ratio to crystal oscillator clock signal, thereby obtains time signal in the system; Restart circuit and connect above-mentioned frequency dividing circuit and restart frequency counter in the frequency dividing circuit according to the phase place comparative result of time signal in the system and correction pulse, the output of frequency dividing circuit connects the real-time time counting circuit.
2. the line duration error based on satellite and constant-temperature crystal oscillator according to claim 1 is tamed system, it is characterized in that, also comprise memory module, connect above-mentioned divide ratio control circuit, the value of the divide ratio when storing normal operation, when the external time reference signal was all lost, the divide ratio value of output preservation was kept time successively.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220474718 CN202759413U (en) | 2012-09-17 | 2012-09-17 | An on-line time error correcting system based on a satellite and a constant temperature crystal oscillator |
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| CN 201220474718 CN202759413U (en) | 2012-09-17 | 2012-09-17 | An on-line time error correcting system based on a satellite and a constant temperature crystal oscillator |
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| CN202759413U true CN202759413U (en) | 2013-02-27 |
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| CN 201220474718 Expired - Fee Related CN202759413U (en) | 2012-09-17 | 2012-09-17 | An on-line time error correcting system based on a satellite and a constant temperature crystal oscillator |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106209092A (en) * | 2016-08-05 | 2016-12-07 | 武汉芯泰科技有限公司 | A kind of precise figures dividing method based on GPS second pulse signal and device |
| CN104300969B (en) * | 2014-05-12 | 2017-12-08 | 长沙理工大学 | A kind of high-precise synchronization clock implementation method based on all-digital phase-locked loop |
| CN110531380A (en) * | 2019-08-30 | 2019-12-03 | 长沙理工大学 | The device and method of satellite clock source low amplitude persistent anomaly for identification |
-
2012
- 2012-09-17 CN CN 201220474718 patent/CN202759413U/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104300969B (en) * | 2014-05-12 | 2017-12-08 | 长沙理工大学 | A kind of high-precise synchronization clock implementation method based on all-digital phase-locked loop |
| CN106209092A (en) * | 2016-08-05 | 2016-12-07 | 武汉芯泰科技有限公司 | A kind of precise figures dividing method based on GPS second pulse signal and device |
| CN110531380A (en) * | 2019-08-30 | 2019-12-03 | 长沙理工大学 | The device and method of satellite clock source low amplitude persistent anomaly for identification |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20130227 Termination date: 20180917 |
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| CF01 | Termination of patent right due to non-payment of annual fee |