CN102981551B - A kind of temperature compensation system for real-time clock and method - Google Patents
A kind of temperature compensation system for real-time clock and method Download PDFInfo
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Abstract
The invention discloses a kind of temperature compensation system for real-time clock, this system comprises and trims register, backoff interval register, low phase error trims mechanism controller, crystal oscillator and frequency trim circuit, trim register, for storing increase and decrease pulse zone bit F and trimming data M, backoff interval register, for preserving backoff interval time value T, trim the low phase error that register is connected trim mechanism controller with described, in make-up time interval T, by judging corresponding clock second compensated under current state, and according to trimming the size of data, what export clock current second trims value m, crystal oscillator, for generation of clock frequency, trim with clock generator and low phase error the frequency that mechanism controller is connected and trim circuit, when this frequency trim circuit receive clock current second trim value m time, according to increase and decrease pulse zone bit F, increase and decrease pulse operation is carried out to crystal oscillator output clock, the 1Hz clock of the accurate low phase error of final output.
Description
Technical field
The invention belongs to electronic circuit technology field, particularly a kind of temperature-compensated system of the real-time clock for electronic circuit and method.
Background technology
Real-time clock (Real Time Clock is called for short RTC) is widely used critical elements in electronic circuit, and it utilizes crystal to perform the function of timing.The hunting of frequency that crystal is being preset, realizes accurate timing by the mode of refresh counter.Because crystal frequency exists the characteristic of drifting about along with temperature variation, so real-time clock is to obtain 1Hz clock accurately, just temperature compensation must be carried out.
Usually adopt compensation scheme as Fig. 1 in current technology.Real-time clock digital temperature compensation system composition shown in figure, comprises temperature sensor, ADC, ROM, compensating circuit, OSC, RTC functional circuit.Preserve in ROM storer that OSC is temperature variant trims data, temperature sensor, by environment temperature switching electrical signals, converts electrical signals to digital signal through ADC; According to the 32.768kHz trimming the output of compensation data crystal oscillator, finally export 1Hz clock accurately.
In order to compensate the error of crystal oscillator output clock, in compensating circuit technology conventional at present, namely the normal compensation scheme adopting burst type is within certain backoff interval cycle, by the increase of burst type within a certain second or the clock number of minimizing some, final frequency division obtains 1Hz clock.This kind of method from the error macroscopically solving crystal oscillator output clock, can finally obtain time 1Hz accurately, but 1Hz clock phase error is now very large.
In order to solve the problem of above-mentioned clock precision, occur a kind ofly adopting the method on average trimmed.As at number of patent application be 200810084325.7 Chinese patent application file in disclose a kind of calibration method of real-time clock, the method is within certain backoff interval cycle, trims value by mean allocation.If in certain backoff interval time T, there is the error of N number of clock period, then by average getting the mode of business Q and remainder R, within front T-1 second, increasing or reducing by Q clock; At T second, increase or minimizing Q+R clock.This kind of mode can reduce the phase error of the 1Hz clock brought because of increase and decrease pulse in a certain sense, but last second increase and decrease pulse number still has more R.The time interval, T was larger, and remainder R variation range also will be larger, and the phase error therefore may brought also will be larger.
Summary of the invention
The object of this invention is to provide a kind of temperature compensation system for real-time clock and method, to solve the problem that compensation method of the prior art cannot solve real-time clock temperature compensation phase error.
Technical scheme of the present invention is, a kind of temperature compensation system for real-time clock, this system comprise trim register, backoff interval register, low phase error trim mechanism controller, crystal oscillator and frequency and trim circuit, wherein
Trim register, for storing increase and decrease pulse zone bit F and trimming data M,
Backoff interval register, for preserving backoff interval time value T,
Trim the low phase error that register is connected trim mechanism controller with described, in make-up time interval T, by corresponding clock second compensated under judging current state, and according to trimming the size of data, what export clock current second trims value m,
Crystal oscillator, for generation of clock frequency,
Trim with clock generator and low phase error the frequency that mechanism controller is connected and trim circuit, when this frequency trim circuit receive clock current second trim value m time, according to increase and decrease pulse zone bit F, increase and decrease pulse operation is carried out to crystal oscillator output clock, the final 1Hz clock exporting accurate low phase error.
Described low phase error trims mechanism controller and comprises, and trims register updating block, divider, timer, two comparers, selector switch, trims value m updating block and increase and decrease pulse zone bit F updating block,
Described divider with trim register updating block and be connected with backoff interval register, it is divisor that the definition of this divider trims register, and backoff interval register is dividend, finally exports business Q and remainder R,
Described timer, is coupled between 1Hz clock and comparer 1, and which obtains current second clock for timing is in backoff interval time T second, when reached during interval T, timer from 1, the timework of repetition from 1 to T,
The first comparer in two described comparers, and trims register updating block and is connected, and whether reaches make-up time interval T, when reached, upgrade and trim register for state more current second,
The second comparer in two described comparers, is connected with timer with divider, and is connected with selector switch again, under comparing present timing state, whether reach remainder R, if reach, coordinate with selector switch, assignment trims value m=Q, if no, then assignment trims value m=Q+1
Described selector switch, is connected with divider with the second comparer, selector switch again with trim value m updating block and be connected.
Described increase and decrease pulse zone bit F updating block, and trims register updating block and is connected with 1Hz clock, for by increase and decrease pulse zone bit F with to trim value synchronous.
Described with trim the low phase error that register is connected and trim mechanism controller, workflow comprises the following steps,
The first step, timer counting cnt, first comparer judges, for make-up time interval T, as cnt=T, upgrade and trim register, now trim register will through divider final business Q and remainder R, if cnt<T, then preserve that to trim register constant, business Q and remainder R also will remain unchanged;
Second step, the second comparer judges, when cnt is less than or equal to R, now selector switch is by a selection Q+1 assignment to trimming register m, if when being greater than R, then assignment is trimmed register m=Q by selector switch;
Described low phase error trims and trims value m in mechanism controller, and what in backoff interval T time, there is R Q+1 trims value, and (T-R) individual Q trims value.
In backoff interval time T, if compared with standard time Ts life period error delta T, i.e. Δ T=T-Ts, in 1 seconds, there is time error Δ t, meet
Trim the N bit that register stores and trim data M, by low phase error trim mechanism controller obtain p.s. in T second corresponding trim value m, m meets relation
A kind of real-time clock temperature compensation, based on temperature compensation system for real-time clock, this system comprise trim register, backoff interval register, low phase error trim mechanism controller, crystal oscillator and frequency and trim circuit, wherein
Trim register, for storing increase and decrease pulse zone bit F and trimming data M,
Backoff interval register, for preserving backoff interval time value T,
Trim the low phase error that register is connected trim mechanism controller with described, in make-up time interval T, by corresponding clock second compensated under judging current state, and according to trimming the size of data, what export clock current second trims value m,
Crystal oscillator, for generation of clock frequency,
Trim with clock generator and low phase error the frequency that mechanism controller is connected and trim circuit, when this frequency trim circuit receive clock current second trim value m time, according to increase and decrease pulse zone bit F, increase and decrease pulse operation is carried out to crystal oscillator output clock, the 1Hz clock of the accurate low phase error of final output
Described low phase error trims mechanism controller and comprises, and trims register updating block, divider, timer, two comparers, selector switch, trims value m updating block and increase and decrease pulse zone bit F updating block,
Described divider with trim register updating block and be connected with backoff interval register, it is divisor that the definition of this divider trims register, and backoff interval register is dividend, finally exports business Q and remainder R,
Described timer, is coupled between 1Hz clock and comparer 1, and which obtains current second clock for timing is in backoff interval time T second, when reached during interval T, timer from 1, the timework of repetition from 1 to T,
The first comparer in two described comparers, and trims register updating block and is connected, and whether reaches make-up time interval T, when reached, upgrade and trim register for state more current second,
The second comparer in two described comparers, is connected with timer with divider, and is connected with selector switch again, under comparing present timing state, whether reach remainder R, if reach, coordinate with selector switch, assignment trims value m=Q, if no, then assignment trims value m=Q+1
Described selector switch, is connected with divider with the second comparer, selector switch again with trim value m updating block and be connected.
Described increase and decrease pulse zone bit F updating block, and trims register updating block and is connected with 1Hz clock, for by increase and decrease pulse zone bit F with to trim value synchronous,
Described with trim the low phase error that register is connected and trim mechanism controller, workflow comprises the following steps,
The first step, timer counting cnt, the first comparer judges, as cnt=T, upgrade trim register, now trim register will through divider final business Q and remainder R, if cnt<T, then preserve that to trim register constant, business Q and remainder R also will remain unchanged;
Second step, the second comparer judges, when cnt is less than or equal to R, now selector switch is by a selection Q+1 assignment to trimming register m, if when being greater than R, then assignment is trimmed register m=Q by selector switch; Described low phase error trims and trims value m in mechanism controller, and what in backoff interval T time, there is R Q+1 trims value, and (T-R) individual Q trims value.
In backoff interval time T, if compared with standard time Ts life period error delta T, i.e. Δ T=T-Ts, in 1 seconds, there is time error Δ t, meet
trim the N bit that register stores and trim data M, by low phase error trim mechanism controller obtain p.s. in T second corresponding trim value m, m meets relation
The present invention in order to reduce the phase difference between adjacent clock to a greater extent, propose a kind of completely newly trim value allocative decision, by a remainder R clock, be assigned in the backoff interval time cycle, within the backoff interval cycle, what be present in R Q+1 trims value, and (T-R) individual Q trims value.This kind of technical scheme, there is the time error of 1 clock in the adjacent 1Hz clock period, greatly reducing the phase error of 1Hz clock at the most.
Accompanying drawing explanation
Fig. 1 real-time clock digital temperature compensation system block diagram
The design real time clock circuit block diagram of Fig. 2 low phase error of the present invention
Fig. 3 low phase error of the present invention trims mechanism controller structural drawing
Fig. 4 low phase error of the present invention trims mechanism controller process flow diagram
Fig. 5 low phase error design real-time clock sequential chart of the present invention
Embodiment
Below with reference to accompanying drawing, the preferred embodiments of the present invention are described, Fig. 2 provides system architecture diagram of the present invention, and structured flowchart comprises: trim register, backoff interval register, and low phase error trims mechanism controller, crystal oscillator, and frequency trims circuit.
Trim register, this trims register and forms by increasing and decreasing pulse zone bit F and trimming data M.
Backoff interval register, this register is for preserving backoff interval time value T.
With trim the low phase error that register is connected and trim mechanism controller, in make-up time interval T, by corresponding clock second compensated under judging current state, and according to trimming the size of data, what export clock current second trims value m.
Crystal oscillator, this preference selects crystal oscillator as clock generator, for generation of clock frequency
Trim with clock generator and low phase error the frequency that mechanism controller is connected and trim circuit, when frequency trim circuit receive clock current second trim value m time, according to increase and decrease pulse zone bit F, increase and decrease pulse operation is carried out to crystal oscillator output clock, the final 1Hz clock exporting accurate low phase error.
Above-mentioned with trim the low phase error that register is connected and trim mechanism controller, this structure is as Fig. 3, and it comprises and trims register updating block, a divider, a timer, two comparers, a selector switch, trims value m updating block, increase and decrease pulse zone bit F updating block.
Above-mentioned low phase error trims the divider in mechanism controller structural drawing 3, with trim register updating block and be connected with backoff interval register, it is divisor that its definition of divider trims register, and backoff interval register is dividend, final output business Q and remainder R.
Above-mentioned low phase error trims the timer in mechanism controller structural drawing 3, be coupled between 1Hz clock and comparer 1, which obtains current second clock for timing is in backoff interval time T second, when reached during interval T, timer is from 1, and the timework of repetition is from 1 to T.
Above-mentioned low phase error trims the comparer 1 in mechanism controller structural drawing 3, and trims register updating block and is connected, and whether reaches make-up time interval T, when reached, upgrade and trim register for state more current second.
Above-mentioned low phase error trims the comparer 2 in mechanism controller structural drawing 3, is connected, and is connected with selector switch again with divider with timer, under comparing present timing state, whether reach remainder R, if reach, coordinate with selector switch, assignment trims value m=Q; If no, then assignment trims value m=Q+1.
Above-mentioned low phase error trims the selector switch in mechanism controller structural drawing 3, is connected with divider with comparer 2, selector switch again with trim value m updating block and be connected.
Above-mentioned increase and decrease pulse zone bit F updating block, its with trim register updating block and be connected with 1Hz clock, its by increase and decrease pulse zone bit F with to trim value synchronous.
Above-mentioned with trim the low phase error that register is connected and trim mechanism controller, workflow is as Fig. 4.Low phase error trims mechanism controller and is divided into two large divisions to perform.
The first, timer counting cnt, comparer 1 judges, as cnt=T, upgrade trim register, now trim register will through divider final business Q and remainder R; If cnt<T, then preserve that to trim register constant, business Q and remainder R also will remain unchanged.
The second, comparer 2 judges, when cnt is less than or equal to R, now selector switch is by a selection Q+1 assignment to trimming register m, if when being greater than R, then assignment is trimmed register m=Q by selector switch.
Above-mentioned low phase error trims and trims value m in mechanism controller, and what in backoff interval T time, there is R Q+1 trims value, and (T-R) individual Q trims value.
This time a kind of computing method of preferred embodiment m value, as sequential chart 5.
In certain backoff interval time T, if compared with standard time Ts life period error delta T, Δ T=T-Ts.In 1 seconds, there is time error Δ t, meet
trim the N bit that register stores and trim data M, by low phase error trim mechanism obtain p.s. in T second corresponding trim value m, m meets relation
1Hz clock and standard 1Hz clock almost homophase after compensating is shown in sequential chart 5.When crystal oscillator output clock CLK frequency f
clkbe less than standard frequency fs, fs=32.768kHz, Δ T>0 now, i.e. Δ t>0, now should reduce the input of CLK pulse; If when crystal oscillator output clock CLK frequency f
clkbe greater than standard frequency fs, Δ T<0 now, i.e. Δ t<0, now should increase the input of CLK pulse.Above two kinds of situations adopt the increase and decrease pulse zone bit F trimmed in register to be distinguished.
The design real-time clock technical scheme of low phase error of the present invention, low phase error is adopted to trim mechanism, foundation trims data M and make-up time interval T obtains average Q and remainder R, and mean allocation trims numerical value m, makes the error of adjacent maximum 1 CLK clock period of existence per second.This compares with the burst compensation way of current cumulative errors, avoids the increase and decrease CLK clock pulses number of clock burst type in certain pulse per second (PPS) cycle, reduces clock phase error, make adjacent per second reach one level and smooth excessive.This time namely scheme improves the precision of clock, again reduces the phase error of 1Hz clock, improves the performance of clock on the whole.
Claims (4)
1. a temperature compensation system for real-time clock, is characterized in that, this system comprise trim register, backoff interval register, low phase error trim mechanism controller, crystal oscillator and frequency and trim circuit, wherein
Trim register, for storing increase and decrease pulse zone bit F and trimming data M,
Backoff interval register, for preserving backoff interval time value T,
Trim the low phase error that register is connected trim mechanism controller with described, in make-up time interval T, by corresponding clock second compensated under judging current state, and according to trimming the size of data, what export clock current second trims value m,
Crystal oscillator, for generation of clock frequency,
Trim with clock generator and low phase error the frequency that mechanism controller is connected and trim circuit, when this frequency trim circuit receive clock current second trim value m time, according to increase and decrease pulse zone bit F, increase and decrease pulse operation is carried out to crystal oscillator output clock, the 1Hz clock of the accurate low phase error of final output
Described low phase error trims mechanism controller and comprises, and trims register updating block, divider, timer, two comparers, selector switch, trims value m updating block and increase and decrease pulse zone bit F updating block,
Described divider with trim register updating block and be connected with backoff interval register, it is divisor that the definition of this divider trims register, and backoff interval register is dividend, finally exports business Q and remainder R,
Described timer, is coupled between 1Hz clock and the first comparer, and which obtains current second clock for timing is in backoff interval time T second, when reached during interval T, timer from 1, the timework of repetition from 1 to T,
The first comparer in two described comparers, and trims register updating block and is connected, and whether reaches make-up time interval T, when reached, upgrade and trim register for state more current second,
The second comparer in two described comparers, is connected with timer with divider, and is connected with selector switch again, under comparing present timing state, whether reach remainder R, if reach, coordinate with selector switch, assignment trims value m=Q, if no, then assignment trims value m=Q+1
Described selector switch, is connected with divider with the second comparer, selector switch again with trim value m updating block and be connected,
Described increase and decrease pulse zone bit F updating block, and trims register updating block and is connected with 1Hz clock, for by increase and decrease pulse zone bit F with to trim value synchronous,
Described with trim the low phase error that register is connected and trim mechanism controller, workflow comprises the following steps,
The first step, timer counting cnt, first comparer judges, for make-up time interval T, as cnt=T, upgrade and trim register, now trim register will through divider final business Q and remainder R, if cnt<T, then preserve that to trim register constant, business Q and remainder R also will remain unchanged;
Second step, the second comparer judges, when cnt is less than or equal to R, now selector switch is by a selection Q+1 assignment to trimming register m, if when being greater than R, then assignment is trimmed register m=Q by selector switch;
Described low phase error trims and trims value m in mechanism controller, and what in backoff interval T time, there is R Q+1 trims value, and (T-R) individual Q trims value.
2. temperature compensation system for real-time clock as claimed in claim 1, is characterized in that,
In backoff interval time T, if compared with standard time Ts life period error delta T, i.e. Δ T=T-Ts, in 1 seconds, there is time error Δ t, meet
Trim the N bit that register stores and trim data M, by low phase error trim mechanism controller obtain p.s. in T second corresponding trim value m, m meets relation
3. a real-time clock temperature compensation, based on temperature compensation system for real-time clock, this system comprise trim register, backoff interval register, low phase error trim mechanism controller, crystal oscillator and frequency and trim circuit, wherein
Trim register, for storing increase and decrease pulse zone bit F and trimming data M,
Backoff interval register, for preserving backoff interval time value T,
Crystal oscillator, for generation of clock frequency,
Described low phase error trims mechanism controller and comprises, and trims register updating block, divider, timer, two comparers, selector switch, trims value m updating block and increase and decrease pulse zone bit F updating block,
It is characterized in that, comprise the following steps:
Trim the low phase error that register is connected trim mechanism controller with described, in make-up time interval T, by corresponding clock second compensated under judging current state, and according to trimming the size of data, what export clock current second trims value m;
Trim with clock generator and low phase error the frequency that mechanism controller is connected and trim circuit, when this frequency trim circuit receive clock current second trim value m time, according to increase and decrease pulse zone bit F, increase and decrease pulse operation is carried out to crystal oscillator output clock, the final 1Hz clock exporting accurate low phase error;
Described divider with trim register updating block and be connected with backoff interval register, it is divisor that the definition of this divider trims register, and backoff interval register is dividend, finally exports business Q and remainder R,
Described timer, is coupled between 1Hz clock and the first comparer, and which obtains current second clock for timing is in backoff interval time T second, when reached during interval T, timer from 1, the timework of repetition from 1 to T,
The first comparer in two described comparers, and trims register updating block and is connected, and whether reaches make-up time interval T, when reached, upgrade and trim register for state more current second,
The second comparer in two described comparers, is connected with timer with divider, and is connected with selector switch again, under comparing present timing state, whether reach remainder R, if reach, coordinate with selector switch, assignment trims value m=Q, if no, then assignment trims value m=Q+1
Described selector switch, is connected with divider with the second comparer, selector switch again with trim value m updating block and be connected,
Described increase and decrease pulse zone bit F updating block, and trims register updating block and is connected with 1Hz clock, for by increase and decrease pulse zone bit F with to trim value synchronous,
Described with trim the low phase error that register is connected and trim mechanism controller, workflow comprises the following steps,
The first step, timer counting cnt, the first comparer judges, as cnt=T, upgrade trim register, now trim register will through divider final business Q and remainder R, if cnt<T, then preserve that to trim register constant, business Q and remainder R also will remain unchanged;
Second step, the second comparer judges, when cnt is less than or equal to R, now selector switch is by a selection Q+1 assignment to trimming register m, if when being greater than R, then assignment is trimmed register m=Q by selector switch;
Described low phase error trims and trims value m in mechanism controller, and what in backoff interval T time, there is R Q+1 trims value, and (T-R) individual Q trims value.
4. real-time clock temperature compensation as claimed in claim 3, is characterized in that,
In backoff interval time T, if compared with standard time Ts life period error delta T, i.e. Δ T=T-Ts, in 1 seconds, there is time error Δ t, meet
Trim the N bit that register stores and trim data M, by low phase error trim mechanism controller obtain p.s. in T second corresponding trim value m, m meets relation
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| CN104977978B (en) * | 2015-07-17 | 2018-04-17 | 上海无线电设备研究所 | A kind of collection and processing method for the asynchronous signal of system clock |
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| CN106444966B (en) * | 2016-09-30 | 2019-06-04 | 大唐微电子技术有限公司 | A kind of real-time clock RTC adjustment device and method |
| CN107465393B (en) | 2017-07-05 | 2020-12-01 | 广州昂宝电子有限公司 | System and method for frequency compensation of real time clock system |
| CN108255232A (en) * | 2017-12-06 | 2018-07-06 | 中国航空工业集团公司西安航空计算技术研究所 | A kind of precision improvement method of IEEE1588 time-codes timer |
| CN108599758B (en) * | 2018-02-10 | 2022-11-22 | 国网河南省电力公司郑州供电公司 | Algorithm and device for generating high-precision trigger pulse based on GPS |
| CN109597297B (en) * | 2018-12-11 | 2020-09-08 | 烟台持久钟表有限公司 | Crystal oscillator compensation method and device |
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| US5327404A (en) * | 1990-11-27 | 1994-07-05 | Vlsi Technology, Inc. | On-chip frequency trimming method for real-time clock |
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