CN114785647B - Equalization circuit and equalization method with signal edge phases respectively adjustable - Google Patents
Equalization circuit and equalization method with signal edge phases respectively adjustable Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
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- H04L25/03006—Arrangements for removing intersymbol interference
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03006—Arrangements for removing intersymbol interference
- H04L2025/03433—Arrangements for removing intersymbol interference characterised by equaliser structure
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Abstract
An equalization circuit and an equalization method with signal edge phases respectively adjustable, wherein the circuit comprises: the logic control module is used for outputting a first register value, a second register value, a size flag bit, a weight direction selection bit and a compensation amplitude; the phase compensation module comprises a main channel unit and a compensation unit, wherein the main channel unit is used for transmitting an input signal with preset amplitude; the compensation unit is connected with the main channel unit and the logic control module, and is used for generating a phase compensation signal according to the input signal, the first register value, the second register value and the size flag bit, selecting the phase compensation signal according to the emphasis direction, and weighting the phase compensation signal directly or after inverting the phase compensation signal with the input signal so as to control the phase of the input signal to modulate according to the compensation amplitude. The logic control module is utilized to output the first register value and the second register value, the internal circuit can automatically find the corresponding edge position of the input signal, the corresponding edge phase of the input signal is subjected to differential compensation, the operation is simple, and the practicability is high.
Description
Technical Field
The application relates to the technical field of electronics, in particular to an equalization circuit and an equalization method with signal edge phases respectively adjustable.
Background
Eye compensation techniques have been an important issue related to high-speed signal quality, and typical equalization techniques can improve the high-frequency component of the eye and compensate for the high-frequency attenuation of the transmission path, but for nonlinear phenomena of the load device, typical equalization techniques have not ideal effects on eye compensation, such as when the load device is a different laser, long trailing phenomena exist on the falling edge of the eye of some types of lasers, phenomena such as overshoot and ringing exist on the rising edge of the eye of some types of lasers, and typical pre-emphasis cannot be compensated for specifically.
The signal quality is generally determined by the opening and symmetry of the eye diagram. The high-frequency component of the signal is greatly attenuated in the transmission process of the high-speed signal, the high-frequency component of the signal is mainly reflected in the slew rate of the rising edge and the falling edge of the signal, when the rising edge and the falling edge of the signal are slow, the signal quality is poor, and the corresponding eye opening is poor; when the degree of attenuation of the rising and falling edges of the signal is different, the signal quality may also be degraded and the symmetry of the corresponding eye pattern may be degraded.
In the prior art, a plurality of compensation circuits are generally used for respectively realizing a pre-emphasis function or a de-emphasis function so as to improve the signal quality and solve the problem of poor eye opening or symmetry; however, a plurality of compensation circuits may cause high power consumption and high design complexity of the circuit, resulting in poor final practicality.
Disclosure of Invention
In view of this, the application provides an equalization circuit and an equalization method with signal edges and phases respectively adjustable, so as to solve the problems of high power consumption expense, high design complexity and weak final practicability of the existing compensation circuit caused by the large number of the compensation circuits.
The application provides a signal edge phase place respectively adjustable equalizer circuit, includes: the logic control module is used for outputting a first register value, a second register value, a size flag bit, a weight direction selection bit and a compensation amplitude; the phase compensation module comprises a main channel unit and a compensation unit, wherein the main channel unit is used for transmitting an input signal with preset amplitude; the compensation unit is connected with the main channel unit and the logic control module, and is used for generating a phase compensation signal according to the input signal, the first register value, the second register value and the size flag bit, and weighting the phase compensation signal with the input signal after directly or reversely taking the phase compensation signal according to the emphasis direction selection bit so as to control the phase of the input signal to be adjusted according to the compensation amplitude.
Optionally, the compensation unit includes a delay subunit and a modulation subunit; the delay subunit generates a first delay signal and a second delay signal according to the input signal, the first register value and the second register value; the first delay signal and the second delay signal are subjected to logic operation according to the size flag bit to output the phase compensation signal, and the phase compensation signal is directly or reversely output according to the emphasis direction selection bit; the modulation subunit is connected with the delay subunit and is used for compensating the edge phase of the input signal corresponding to the phase compensation signal according to the compensation amplitude.
Optionally, the delay subunit comprises a delay signal generating circuit, a compensation signal generating circuit and an emphasis direction selecting circuit; the delay signal generating circuit is connected with the logic control module and the main channel unit and is used for generating a first delay signal and a second delay signal according to the input signal, the first register value and the second register value; the compensation signal generation circuit is connected with the delay signal generation circuit and the logic control module and is used for taking the first delay signal, the second delay signal and the calculated signal as the phase compensation signal when the size marker bit is a first numerical value; when the size flag bit is a second numerical value, the first delay signal and the second delay signal or the signal after operation are used as the phase compensation signal; the first numerical value characterizes the first register value being greater than the second register value; the second value characterizes the first register value as smaller than the second register value;
or, the first value characterizes the first register value as smaller than the second register value; the second value characterizes the first register value being greater than the second register value; the emphasis direction selection circuit is connected with the compensation signal generation circuit and the logic control module and is used for outputting the phase compensation signal forward or reversely according to the emphasis direction selection bit.
Optionally, the delay signal generating circuit includes a plurality of buffers, a first channel selector and a second channel selector; the input ends of the first buffer are used for acquiring the input signals, and the output end of each buffer is sequentially connected with the input ends of the first channel selector and the second channel selector so as to carry out different time delays on the input signals; the control end of the first channel selector is used for receiving the first register value and outputting the first delay signal according to the first register value, and the control end of the second channel selector is used for receiving the second register value and outputting the second delay signal according to the second register value.
Optionally, the compensation signal generating circuit includes at least one and gate, or gate, and a third channel selector; the first input end of the AND gate is connected with the output end of the first channel selector, the second input end of the AND gate is connected with the output end of the second channel selector, and the output end of the AND gate is connected with the first input end of the third channel selector; the first input end of the OR gate is connected with the output end of the first channel selector, the second input end of the OR gate is connected with the output end of the second channel selector, and the output end of the OR gate is connected with the second input end of the third channel selector; the control end of the third channel selector is used for receiving the size marker bit, and selecting a signal of the first input end as the phase compensation signal when the size marker bit is a first numerical value; and selecting a signal of a second input end as the phase compensation signal when the size flag bit is a second value.
Optionally, the emphasis direction selection circuit includes at least one fourth channel selector; the first input end of the fourth channel selector is directly connected with the output end of the third channel selector; the second input end of the fourth channel selector is connected with the output end of the third channel selector after being inverted; the control end of the fourth channel selector is used for receiving the emphasis direction selection bit and outputting the phase compensation signal forward when the emphasis direction selection bit is a third numerical value; inverting the phase compensation signal and outputting the inverted phase compensation signal when the emphasis direction selection bit is a fourth numerical value; the third numerical characterization performs pre-emphasis compensation on the input signal, and the fourth numerical characterization performs de-emphasis compensation on the input signal.
Optionally, the modulation subunit includes at least a first multiplier and an adder; the first input end of the first multiplier is connected with the output end of the fourth selector, and the second input end is used for receiving the compensation amplitude and controlling the phase compensation signal to adjust the compensation amplitude; the first input end of the adder is used for receiving the input signal, the second input end of the adder is connected with the output end of the first multiplier, and the first input end of the adder is used for adding the input signal and the adjusted compensation amplitude value to compensate the edge phase of the input signal.
Optionally, the main channel unit further includes a main channel buffer and a second multiplier; the input end of the main channel buffer is used for receiving the input signal, and the output end is used for outputting the buffered input signal;
the first input end of the second multiplier is connected with the output end of the main channel buffer, and the second input end is used for receiving a preset amplitude and adjusting the amplitude of the input signal according to the preset amplitude.
Optionally, the logic control module includes at least one of a controller and a digital logic circuit.
The application also provides an equalization method with the signal edge phases respectively adjustable, which comprises the following steps: acquiring a first register value, a second register value, a size flag bit, a weighting direction selection bit and a compensation amplitude; and obtaining an input signal with a preset amplitude, generating a phase compensation signal according to the input signal, the first register value, the second register value and the size marker bit, and weighting the phase compensation signal with the input signal directly or after inverting according to the emphasis direction selection bit so as to control the phase of the input signal to be adjusted according to the compensation amplitude.
Optionally, the step of weighting the phase compensation signal directly or after inverting the phase compensation signal according to the emphasis direction selection bit to the input signal to control the phase of the input signal to be adjusted according to the compensation amplitude value includes: outputting the phase compensation signal in the forward direction when the emphasis direction selection bit is a first preset value; when the weighting direction selection bit is a second preset value, inverting the phase compensation signal and outputting the inverted phase compensation signal; controlling and adjusting the compensation amplitude according to the phase compensation signal; adding the input signal and the adjusted compensation amplitude to compensate the edge phase of the input signal; the first preset numerical representation performs pre-emphasis compensation on the input signal, and the second preset numerical representation performs de-emphasis compensation on the input signal.
The equalization circuit and the equalization method with the signal edge phases respectively adjustable output a first register value, a second register value, a size flag bit, an emphasis direction selection bit and a compensation amplitude through a logic control module; the compensation unit can generate a phase compensation signal according to the input signal, the first register value, the second register value and the size flag bit, and weight the phase compensation signal with the input signal after directly or reversely taking the phase compensation signal according to the emphasis direction selection bit, and can perform pre-emphasis compensation or de-emphasis compensation so as to control the phase of the input signal to be adjusted according to the compensation amplitude, only one compensation unit is needed, the resources of a circuit are fully utilized, and the power consumption is low; when the logic control module is used, the logic control module is only required to output the first register value and the second register value, the internal circuit can automatically find the corresponding edge position of the input signal, the corresponding edge phase of the input signal is subjected to differential compensation, the operation is simple, and the practicability is high.
Furthermore, the path selection of the phase compensation signal is controlled by carrying out logic operation on the size flag bits, one path is conducted, and the other path is closed at the same time, so that the power consumption of the circuit is further reduced.
Further, the first delay signal and the second delay signal, namely the long delay signal and the short delay signal, are extracted through the delay signal generating circuit respectively; because two delay circuits are not needed, the purpose of saving the power consumption of the circuit can be achieved.
Drawings
As described in the background art, the prior art generally uses a plurality of compensation circuits to implement a pre-emphasis function or a de-emphasis function, respectively, to improve signal quality and solve the problem of poor eye opening or symmetry. However, a plurality of compensation circuits may cause high power consumption and high design complexity of the circuit, resulting in poor final practicality.
Aiming at the defects of large power consumption and large design complexity of a plurality of compensation circuits in the prior art, the invention provides the equalization circuit and the equalization method with low power consumption and respectively adjustable signal edge phases, and the information of the rising edge phases and the falling edge phases in the input signals can be respectively extracted only by one delay circuit, and meanwhile, two phases are compensated by utilizing one tail current modulation circuit, so that the purpose of saving power consumption is achieved.
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly introduced below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of an equalization circuit with adjustable signal edge phases according to an embodiment of the present application;
fig. 2 is a schematic structural diagram of an equalization circuit with adjustable signal edge phases according to an embodiment of the present application;
FIG. 3 is a circuit diagram of a delay signal generating circuit according to an embodiment of the present application;
fig. 4a is a timing chart of the equalizing circuit with respectively adjustable signal edge phases in the present embodiment when the rising edge phase is greater than or equal to the falling edge phase;
FIG. 4b is a timing chart of the equalizing circuit with respectively adjustable signal edge phases in the present embodiment when the rising edge phase is smaller than the falling edge phase;
FIG. 5 is a schematic flow chart of an equalization method with respectively adjustable signal edge phases according to an embodiment of the present application;
fig. 6 is a flow chart of an equalization method with adjustable signal edge phases according to an embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application. The various embodiments described below and their technical features can be combined with each other without conflict.
Referring to fig. 1, a schematic structure diagram of an equalization circuit with adjustable signal edge phases according to an embodiment of the present application is shown.
The equalizing circuit with the signal edge phase respectively adjustable in the embodiment comprises a logic control module 1 and a phase compensation module 1.
The logic control module 1 is used for outputting a first register value, a second register value, a size flag bit, a weight direction selection bit and a compensation amplitude;
the phase compensation module 2 comprises a main channel unit 21 and a compensation unit 22, wherein the main channel unit 21 is used for transmitting an input signal with preset amplitude; the compensation unit 22 is connected to the main channel unit 21 and the logic control module 1, and is configured to generate a phase compensation signal according to the input signal, the first register value, the second register value, and the size flag bit, and weight the phase compensation signal directly or after being inverted according to the emphasis direction selection bit with the input signal to control the phase of the input signal to be adjusted according to the compensation amplitude.
The equalizing circuit with the signal edge phase respectively adjustable in the embodiment outputs a first register value, a second register value, a size flag bit, an emphasis direction selection bit and a compensation amplitude value through the logic control module 1; the compensation unit 22 may generate a phase compensation signal according to the input signal, the first register value, the second register value, and the size flag bit, and weight the phase compensation signal directly or after inverting the phase compensation signal according to the emphasis direction selection bit, and may perform pre-emphasis compensation or de-emphasis compensation, so as to control the phase of the input signal to be adjusted according to the compensation amplitude, only one compensation unit is needed, and the circuit resource is fully utilized, with low power consumption; when the logic control module 1 is used, the logic control module 1 is used for outputting the first register value and the second register value, the internal circuit can automatically find the corresponding edge position of the input signal, and the corresponding edge phase of the input signal is subjected to differential compensation, so that the logic control module is simple to operate and high in practicability.
In an alternative embodiment, the compensation unit includes a delay subunit and a modulation subunit; the delay subunit generates a first delay signal and a second delay signal according to the input signal, the first register value and the second register value; the first delay signal and the second delay signal are subjected to logic operation according to the size flag bit to output the phase compensation signal, and the phase compensation signal is directly or reversely output according to the emphasis direction selection bit; the modulation subunit is connected with the delay subunit and is used for compensating the edge phase of the input signal corresponding to the phase compensation signal according to the compensation amplitude. The path selection of the phase compensation signal is controlled by carrying out logic operation on the large and small flag bits, one path is turned on, and the other path is turned off, so that the circuit power consumption is further reduced.
In an alternative embodiment, the logic control module includes at least one of a controller and digital logic. The controller comprises an upper computer and an MCU, wherein delay registers of rising edges and falling edges are input from the upper computer or the MCU configuration table, corresponding long delay registers and short delay registers, namely a first register and a second register, are extracted through a digital logic circuit, the sizes of the two registers are judged and are respectively used as a first register value and a second register value, namely the long delay register value and the short delay register value, so that the size of a phase compensation signal of the compensation unit is controlled, the circuit of the compensation unit is simplified, the power consumption of the circuit is reduced, and the circuit design is simplified.
In an alternative embodiment, the delay subunit includes a delay signal generating circuit, a compensation signal generating circuit, and an emphasis direction selecting circuit; the delay signal generating circuit is connected with the logic control module and the main channel unit and is used for generating a first delay signal and a second delay signal according to the input signal, the first register value and the second register value; the compensation signal generation circuit is connected with the delay signal generation circuit and the logic control module and is used for taking the first delay signal, the second delay signal and the calculated signal as the phase compensation signal when the size marker bit is a first numerical value; when the size flag bit is a second numerical value, the first delay signal and the second delay signal or the signal after operation are used as the phase compensation signal; the first numerical value characterizes the first register value being greater than the second register value; the second value characterizes the first register value as smaller than the second register value; or, the first value characterizes the first register value as smaller than the second register value; the second value characterizes the first register value being greater than the second register value; the emphasis direction selection circuit is connected with the compensation signal generation circuit and the logic control module and is used for outputting the phase compensation signal forward or reversely according to the emphasis direction selection bit. The first delay signal and the second delay signal, namely a long delay signal and a short delay signal, are extracted respectively through a delay signal generating circuit; because two delay circuits are not needed, the purpose of saving the power consumption of the circuit can be achieved.
Referring to fig. 2, a schematic diagram of an equalization circuit with phase adjustment along the signal edge according to an embodiment of the present application is shown.
The equalization circuit with adjustable signal edge phases in this embodiment, the compensation unit 22 includes a delay subunit 221 and a modulation subunit 222.
The delay subunit 221 includes a delay signal generating circuit 2211, a compensation signal generating circuit 2212, and an emphasis direction selecting circuit 2213.
The delay signal generating circuit 2211 is connected to the logic control module and the main channel unit, and is configured to generate a first delay signal and a second delay signal according to the input signal, the first register value and the second register value; the compensation signal generating circuit 2212 is connected to the delay signal generating circuit 2211 and the logic control module, and is configured to use the first delay signal and the second delay signal and the calculated signal as the phase compensation signal when the size flag bit is a first value; when the size flag bit is a second numerical value, the first delay signal and the second delay signal or the signal after operation are used as the phase compensation signal; the first numerical value characterizes the first register value being greater than the second register value; the second value characterizes the first register value as smaller than the second register value; or, the first value characterizes the first register value as smaller than the second register value; the second value characterizes the first register value being greater than the second register value; the emphasis direction selection circuit 2213 is connected to the compensation signal generation circuit 2212 and the logic control module, and is configured to output the phase compensation signal in a forward direction or in a reverse direction according to the emphasis direction selection bit.
In this embodiment, the delay signal generating circuit 2211 includes a buffer buf_1, a buffer buf_2, a buffer buf_n-1, a buffer buf_n, a first channel selector Mux1 and a second channel selector Mux2; the INPUT end of the buffer BUF_1 is used for acquiring the INPUT signal INPUT, and the output ends of the buffer BUF_1, the buffer BUF_2, the buffer BUF_n-1 and the buffer BUF_n are sequentially connected and connected with the INPUT ends of the first channel selector Mux1 and the second channel selector Mux2 so as to carry out different time delays on the INPUT signal INPUT; the control end of the first channel selector Mux1 is configured to receive the first register value, i.e. long delay extraction, and output the first delay signal according to the first register value, and the control end of the second channel selector Mux2 is configured to receive the second register value, i.e. short delay extraction, and output the second delay signal according to the second register value.
The compensation signal generation circuit 2212 includes an AND gate AND, an OR gate OR, AND a third channel selector Mux3; a first input end of the AND gate is connected with the output end of the first channel selector Mux1 the second input end is connected with the output end of the second channel selector Mux2, AND the output end is connected with the first input end of the third channel selector Mux3; the first input end of the OR gate is connected with the output end of the first channel selector Mux1, the second input end of the OR gate is connected with the output end of the second channel selector Mux2, and the output end of the OR gate is connected with the second input end of the third channel selector Mux3; the control end of the third channel selector Mux3 is configured to receive the size flag bit, and select a signal of the first input end as the phase compensation signal when the size flag bit is a first value; and selecting a signal of a second input end as the phase compensation signal when the size flag bit is a second value. In other alternative embodiments, the compensation signal generation circuit 2212 may further include other numbers of AND gates AND, OR gates OR AND third channel selectors Mux3, such as two OR three AND gates AND, OR gates OR AND third channel selectors Mux3; other elements may also be included.
In an alternative implementation mode, the size flag bit is used as an enabling signal of the AND gate AND the OR gate, the size flag bit is connected with an enabling control end of the AND gate AND the OR gate, AND then is connected with an enabling control end of the OR gate after passing through an inverter, so that path selection of OR operation OR AND operation is controlled, one path is closed when the other path is conducted, AND circuit power consumption is further reduced.
The emphasis direction selection circuit 2213 includes at least one fourth channel selector Mux4; the first input end of the fourth channel selector Mux4 is directly connected with the output end of the third channel selector Mux 3; the second input end of the fourth channel selector Mux4 is connected with the output end of the third channel selector Mux3 after being inverted; the control end of the fourth channel selector Mux4 is configured to receive the emphasis direction selection bit, and forward output the phase compensation signal when the emphasis direction selection bit is a third value; inverting the phase compensation signal and outputting the inverted phase compensation signal when the emphasis direction selection bit is a fourth numerical value; the third numerical characterization performs pre-emphasis compensation on the input signal, and the fourth numerical characterization performs de-emphasis compensation on the input signal.
The main channel unit 21 further comprises a main channel buffer BUF and a second multiplier A2; the INPUT end of the main channel buffer BUF is used for receiving the INPUT signal INPUT, and the output end is used for outputting the buffered INPUT signal; the first INPUT end of the second multiplier A2 is connected to the output end of the main channel buffer BUF, and the second INPUT end is configured to receive a preset amplitude a, and to adjust the amplitude of the INPUT signal INPUT according to the preset amplitude a.
The modulation subunit 222 includes at least a first multiplier A1 and an adder S; the first input end of the first multiplier A1 is connected with the output end of the fourth channel selector Mux4, the second input end is used for receiving the compensation amplitude, the first input end of the adder S is connected with the output end of the second multiplier A2, and the second input end of the adder S is connected with the output end of the first multiplier A1 and is used for adding the amplitude-adjusted input signal and the adjusted compensation amplitude to compensate the phase of the input signal. The modulation subunit 222 in this embodiment includes a tail current modulation circuit.
The working principle of the equalizing circuit with the signal edge phases respectively adjustable in the embodiment is as follows: the equalizing circuit with the signal edge phase respectively adjustable in this embodiment only needs one delay circuit (including n delay units formed by n buffers buf_1, buf_2, buf_n-1 and buf_n) and two path selection circuits (including a first path selector Mux1 and a second path selector Mux 2), and determines the sizes of a rising edge delay register and a falling edge delay register through a logic control module to respectively generate a long delay register value and a short delay register value, namely a first register value and a second register value and a size flag bit; the long delay register controls the first channel selector Mux1 to selectively output a long delay signal, i.e., a first delay signal, and the short delay register controls the second channel selector Mux2 to selectively output a short delay signal, i.e., a second delay signal. The size flag bit (1 or 0) indicates whether the rising edge register value is greater than the falling edge register value; if the rising edge delay register value is larger than the falling edge delay register value, namely the first register value is larger than the second register value, and the size flag bit is a first numerical value, performing AND operation on the first delay signal and the second delay signal, and outputting the first delay signal and the second delay signal by a third channel selector Mux 3; if the rising edge delay register value is smaller than the falling edge delay register value, that is, the first register value is smaller than the second register value, and the size flag bit is a second value, the first delay signal and the second delay signal are ored and output by the third channel selector Mux 3. The first value may be 0 or 1, or other values, and the corresponding second value may be 1 or 0, or other values. The emphasis direction selection bit controls whether the signal output by the fourth channel selector Mux4 is subjected to inversion processing, and if the signal is subjected to inversion processing, the pre-emphasis compensation is performed; if not, de-emphasis compensation is indicated. (the concepts of pre-emphasis and de-emphasis in this application refer specifically to increasing the relatively low frequency content of the high frequency content and de-emphasis to decreasing the relatively low frequency content of the high frequency content). A phase compensation signal of the output of the fourth channel selector Mux4, the phase compensation signal including delay information of each rising edge and falling edge; and controlling the modulating current delta A generated by the tail current modulating circuit to be overlapped to the original input signal, thereby realizing the pre-emphasis function.
The equalization circuit with the signal edge phases respectively adjustable is used for inputting the rising edge delay register and the falling edge delay register from the upper computer or the MCU configuration table, and extracting corresponding first register values and second register values through the digital logic circuit; the delay signal generating circuit is composed of cascaded delay units, and the first delay signal and the second delay signal are respectively extracted through a first channel selector Mux1 and a second channel selector Mux 2; because two paths of delay circuits are not needed, and the first register value and the second register value control the number of stages of the conduction of the buffer in the delay unit, the purpose of saving circuit power consumption can be achieved; the phase compensation signals generated by the first delay signal and the second delay signal through OR operation or AND operation contain delay information of each rising edge and each falling edge; the size flag bit controls the path selection of OR operation or AND operation, and the other path is closed, so that the power consumption is further reduced; pre-emphasis compensation or de-emphasis compensation can be performed by selecting the direction of emphasis by the selector switch.
Referring to fig. 3, a circuit diagram of a delay signal generating circuit according to an embodiment of the present application is shown.
The delay signal generating circuit of the present embodiment includes a buffer buf_n, a buffer selector bufmux_n-1, a buffer selector bufmux_n-2 … …, a buffer selector bufmux_2, a buffer selector bufmux_1, and a channel selector Mux5.
The INPUT signal INPUT is sequentially INPUT to the buffer buf_n, the buffer selector bufmux_n-1, the buffer selector bufmux_n-2 … …, the buffer selector bufmux_2, the buffer selector bufmux_1 and one INPUT of the channel selector Mux5, the output of the buffer selector buf_n is connected with the other INPUT of the buffer selector bufmux_n-1 and one INPUT of the channel selector Mux5, the output of the buffer selector bufmux_n-1 is connected with the other INPUT of the buffer selector bufmux_n-2 and one INPUT of the channel selector Mux5, so that the output of the buffer selector fmux_n-2 is connected with the other INPUT of the buffer selector of the next stage and one INPUT of the channel selector Mux5, the output of the buffer selector fmux_2 is connected with the other INPUT of the buffer selector bufmux_1 and one INPUT of the channel selector Mux5, and the delay value is extracted according to the first delay value of the buffer register, i.e. the delay value is controlled by the first register. The buffer selector BUFMux_1, the buffer selector BUFMux_ … … and the buffer selector BUFMux_n-2 have the same delay function as the buffer except the channel selection function; the control terminals of the buffer selector BUFMux_1, the buffer selector BUFMux_2 … … and the buffer selector BUFMux_n-2 are respectively used for receiving the first register value, namely long delay extraction, controlling the connection or disconnection of each buffer selector and the input path selection (input one-out-of-two) according to the first register value, and controlling the connection or disconnection of the buffer selector BUF_n according to the first register value. In summary, the first register simultaneously controls the buffer selector BUFMux_1, the buffer selector BUFMux_2 … …, the buffer selector BUFMux_n-2, the buffer selector BUFMux_n-1 and the buffer BUF_n to select and output long delay signals, namely first delay signals. The control end of the channel selector Mux5 is configured to receive the second register value, i.e. short delay extraction, and output a short delay signal, i.e. the second delay signal, according to the second register value. In summary, the short delay register controls the channel selector Mux5 to select and output the short delay signal, i.e. the second delay signal.
The delay signal generating circuit of the embodiment provides another flexible circuit structure, fully utilizes the functions of delay buffering and path selection existing in the buffer selector, controls the generation of long delay signals (the generation of short delay signals is the same as that of the embodiment, and is not repeated here), reduces the parasitism of the output path of the long delay signals, and increases the application scene of the circuit.
Referring to fig. 4a, the equalizing circuits with respectively adjustable signal edge phases in the present embodiment are shown in the timing chart when the rising edge phase is greater than or equal to the falling edge phase.
When the equalization circuit with the signal edge phases respectively adjustable in the embodiment compensates, the rising edge phase is greater than or equal to the falling edge phase, namely (DeltaTr is greater than or equal to DeltaTf): the first delay signal is a long delay signal, the delay phase delta Tr, the second delay signal is a short delay signal, the delay phases delta Tf, delta Tr is larger than or equal to delta Tf, and the size flag bit is a first value, so that the first delay signal and the second delay signal are subjected to AND operation to generate a phase compensation signal, namely the first delay signal and the second delay signal, the phase compensation signal is overlapped to an original input signal according to a weighting direction selection bit and a modulation current delta A generated by a tail current modulation circuit, and therefore a pre-emphasis compensation function or a de-emphasis compensation function is realized, the protruding phase of the pre-emphasis compensated signal at the rising edge is larger than or equal to the recessed phase of the pre-emphasis compensated signal at the falling edge, and the recessed phase of the de-emphasis compensated signal at the rising edge is larger than or equal to the protruding phase of the pre-emphasis signal at the falling edge.
Referring to fig. 4b, the equalizing circuit with adjustable signal edge phases in the present embodiment has a timing chart when the rising edge phase is smaller than the falling edge phase.
When the equalization circuit with the signal edge phases respectively adjustable in this embodiment compensates, the rising edge phase is smaller than the falling edge phase, that is, (Δtr < Δtf): the first delay signal is a long delay signal, the delay phase delta Tf, the second delay signal is a short delay signal, the delay phases delta Tr, delta Tr < delta Tf, and the size zone bit is a second value, so that the first delay signal and the second delay signal are subjected to OR operation to generate a phase compensation signal, namely the first delay signal U-shaped second delay signal, and the phase compensation signal is overlapped to an original input signal according to a weighting direction selection bit and a modulation current delta A generated by a tail current modulation circuit, thereby realizing a pre-emphasis compensation function or a de-emphasis compensation function, wherein the raised phase of the pre-emphasis compensated signal at the rising edge is smaller than the recessed phase of the pre-emphasis compensated signal at the falling edge, and the recessed phase of the de-emphasis compensated signal at the rising edge is smaller than the raised phase of the pre-emphasis signal at the falling edge.
In summary, the equalization circuit with the signal edge phase being respectively adjustable in this embodiment only needs to use one delay circuit (instead of two delay circuits) and one tail current modulation circuit (instead of two tail current modulation circuits), adopts a digital logic judgment method, fully utilizes the resources of the delay circuit, closes the paths which do not work, has low power consumption, and can automatically find the corresponding edge position by configuring an upper computer or importing the delay registers of the rising edge and the falling edge by an MCU during use, so that the equalization circuit is simple to operate and has higher practicability.
Referring to fig. 5, a flow chart of an equalization method with phase adjustment along a signal edge according to an embodiment of the present application is shown.
The equalization method with the signal edge phases respectively adjustable in the embodiment comprises the following steps:
and S10, acquiring a first register value, a second register value, a size flag bit, an emphasis direction selection bit and a compensation amplitude.
And S20, acquiring an input signal with a preset amplitude, generating a phase compensation signal according to the input signal, the first register value, the second register value and the size flag bit, and weighting the phase compensation signal directly or after inverting the phase compensation signal according to the emphasis direction selection bit and the input signal so as to control the phase of the input signal to be adjusted according to the compensation amplitude.
In the equalization method with the signal edge phase respectively adjustable, the first register value and the second register value, the size flag bit, the emphasis direction selection bit and the compensation amplitude are output; generating a phase compensation signal according to the input signal, the first register value, the second register value and the size flag bit, and weighting the phase compensation signal with the input signal after directly or reversely taking the phase compensation signal according to the emphasis direction selection bit, so as to perform pre-emphasis compensation or de-emphasis compensation, so that the phase of the input signal is controlled to be adjusted according to the compensation amplitude, only one compensation unit is needed, the resources of a circuit are fully utilized, and the power consumption is low; when the input signal compensation device is used, the internal circuit can automatically find the corresponding edge position of the input signal only by outputting the first register value and the second register value, and the corresponding edge phase of the input signal is subjected to differential compensation, so that the operation is simple and the practicability is high.
In an alternative embodiment, step S20 includes: outputting the phase compensation signal in the forward direction when the emphasis direction selection bit is a first preset value; when the weighting direction selection bit is a second preset value, inverting the phase compensation signal and outputting the inverted phase compensation signal; controlling and adjusting the compensation amplitude according to the phase compensation signal; adding the input signal and the adjusted compensation amplitude to compensate the edge phase of the input signal; the first preset numerical representation performs pre-emphasis compensation on the input signal, and the second preset numerical representation performs de-emphasis compensation on the input signal. Pre-emphasis compensation and de-emphasis compensation functions can be implemented by the emphasis direction select bits.
The equalization method with the signal edge phases respectively adjustable in the embodiment can be realized by the compensation circuit or other circuits.
Referring to fig. 6, a flow chart of an equalization method with phase adjustment along a signal edge according to an embodiment of the present application is shown.
The equalization method with the signal edge phases respectively adjustable in the embodiment comprises the following steps:
step S31, inputting rising edge and falling edge register values.
Step S32, determining whether the rising edge register value is greater than or equal to the falling edge register value, if so, executing step S33, otherwise, executing step S35.
Step S33, a first register=rising edge register value, and a second register=falling edge register value. The rising edge register value is assigned to a first register, wherein the first register is a long delay register, and can control the long delay register to output a long delay signal, and the long delay signal is a first delay signal; the falling edge register value is assigned to a second register, and the second register is a short delay register, so that the short delay register can be controlled to output a short delay signal, and the short delay signal is the second delay signal.
In step S34, the first delay signal and the second delay signal are and-operated, or the operation path is closed. The first delay signal is a long delay signal, the second delay signal is a short delay signal, and the first delay signal and the second delay signal are subjected to AND operation, namely the long delay signal and the short delay signal are subjected to AND operation, or an operation path is closed.
Step S35, a first register=falling edge register value, and a second register=rising edge register value. Assigning the rising edge register value to a second register, and controlling the second register to output a second delay signal, wherein the second delay signal is a short delay signal; the falling edge register value is assigned to the first register, and the first register can be controlled to output a first delay signal, wherein the first delay signal is a long delay signal.
In step S36, the first delay signal and the second delay signal are or-operated, and the operation path is closed. That is, the long delay signal and the short delay signal are OR-operated, and the AND operation path is closed.
Step S37, acquiring the emphasis direction selection bit.
And performing pre-emphasis when the emphasis direction selection bit is a first preset value, performing step S38, performing de-emphasis when the emphasis direction selection bit is a second preset value, and performing step S39.
Step S38, the phase compensation signal is inverted and then output. The signal is the phase compensation signal.
Step S39, outputting the phase compensation signal in the forward direction. The signal is the phase compensation signal.
And S40, emphasizing the delayed signal output, namely controlling and adjusting the compensation amplitude according to the phase compensation signal.
And S41, the delay signals are added to the original signals in a specific proportion to realize the emphasis function, namely the input signals and the adjusted compensation amplitude are added to compensate the edge phase of the input signals, and the emphasis function is realized.
The timing diagrams of the equalization method with the adjustable signal edge phases respectively in the embodiment are shown in fig. 4a and fig. 4b, and are not repeated here.
The equalization method with the signal edge phases respectively adjustable in the embodiment can automatically find the corresponding edge positions only by leading in the delay register values of the rising edge and the falling edge, and performs differential compensation on the corresponding edge phases, so that the operation is simple and the practicability is higher.
The foregoing embodiments are merely examples of the present application, and are not intended to limit the scope of the patent application, so that all equivalent structures or equivalent processes using the descriptions and the drawings of the present application, such as the combination of technical features of the embodiments, or direct or indirect application to other related technical fields, are included in the scope of the patent protection of the present application.
Claims (9)
1. An equalization circuit with signal edge phases respectively adjustable, comprising:
the logic control module is used for outputting a first register value, a second register value, a size flag bit, a weight direction selection bit and a compensation amplitude;
the phase compensation module comprises a main channel unit and a compensation unit, wherein the main channel unit is used for transmitting an input signal with preset amplitude; the compensation unit is connected with the main channel unit and the logic control module and is used for generating a phase compensation signal according to the input signal, the first register value, the second register value and the size flag bit, and weighting the phase compensation signal with the input signal after directly or reversely taking the phase compensation signal according to the emphasis direction selection bit so as to control the phase of the input signal to be adjusted according to the compensation amplitude;
The compensation unit comprises a delay subunit and a modulation subunit;
the delay subunit generates a first delay signal and a second delay signal according to the input signal, the first register value and the second register value; the first delay signal and the second delay signal are subjected to logic operation according to the size flag bit to output the phase compensation signal, and the phase compensation signal is directly or reversely output according to the emphasis direction selection bit;
the modulation subunit is connected with the delay subunit and is used for compensating the edge phase of the input signal corresponding to the phase compensation signal according to the compensation amplitude.
2. The equalization circuit of claim 1 wherein said delay sub-units comprise a delay signal generation circuit, a compensation signal generation circuit and an emphasis direction selection circuit;
the delay signal generating circuit is connected with the logic control module and the main channel unit and is used for generating a first delay signal and a second delay signal according to the input signal, the first register value and the second register value;
The compensation signal generation circuit is connected with the delay signal generation circuit and the logic control module and is used for taking the first delay signal, the second delay signal and the calculated signal as the phase compensation signal when the size marker bit is a first numerical value; when the size flag bit is a second numerical value, the first delay signal and the second delay signal or the signal after operation are used as the phase compensation signal;
the first numerical value characterizes the first register value being greater than the second register value; the second value characterizes the first register value as smaller than the second register value;
or, the first value characterizes the first register value as smaller than the second register value; the second value characterizes the first register value being greater than the second register value;
the emphasis direction selection circuit is connected with the compensation signal generation circuit and the logic control module and is used for outputting the phase compensation signal forward or reversely according to the emphasis direction selection bit.
3. The equalization circuit of claim 2 wherein said delay signal generation circuit comprises a plurality of buffers, a first channel selector and a second channel selector;
The input ends of the first buffer are used for acquiring the input signals, and the output end of each buffer is sequentially connected with the input ends of the first channel selector and the second channel selector so as to carry out different time delays on the input signals;
the control end of the first channel selector is used for receiving the first register value and outputting the first delay signal according to the first register value, and the control end of the second channel selector is used for receiving the second register value and outputting the second delay signal according to the second register value.
4. The equalization circuit of claim 3 wherein said compensation signal generation circuit comprises at least one and gate, or gate and a third channel selector;
the first input end of the AND gate is connected with the output end of the first channel selector, the second input end of the AND gate is connected with the output end of the second channel selector, and the output end of the AND gate is connected with the first input end of the third channel selector;
the first input end of the OR gate is connected with the output end of the first channel selector, the second input end of the OR gate is connected with the output end of the second channel selector, and the output end of the OR gate is connected with the second input end of the third channel selector;
The control end of the third channel selector is used for receiving the size marker bit, and selecting a signal of the first input end as the phase compensation signal when the size marker bit is a first numerical value; and selecting a signal of a second input end as the phase compensation signal when the size flag bit is a second value.
5. The equalization circuit of claim 4 wherein said emphasis direction selection circuit comprises at least a fourth channel selector;
the first input end of the fourth channel selector is directly connected with the output end of the third channel selector; the second input end of the fourth channel selector is connected with the output end of the third channel selector after being inverted; the control end of the fourth channel selector is used for receiving the emphasis direction selection bit and outputting the phase compensation signal forward when the emphasis direction selection bit is a third numerical value; inverting the phase compensation signal and outputting the inverted phase compensation signal when the emphasis direction selection bit is a fourth numerical value;
the third numerical characterization performs pre-emphasis compensation on the input signal, and the fourth numerical characterization performs de-emphasis compensation on the input signal.
6. The equalization circuit of claim 5 wherein said modulation subunit includes at least a first multiplier and adder;
the first input end of the first multiplier is connected with the output end of the fourth selector, and the second input end is used for receiving the compensation amplitude and controlling the phase compensation signal to adjust the compensation amplitude;
the first input end of the adder is used for receiving the input signal, the second input end of the adder is connected with the output end of the first multiplier, and the first input end of the adder is used for adding the input signal and the adjusted compensation amplitude value to compensate the edge phase of the input signal.
7. The separately adjustable signal edge phase equalization circuit of claim 6, wherein said main channel unit further comprises a main channel buffer and a second multiplier;
the input end of the main channel buffer is used for receiving the input signal, and the output end is used for outputting the buffered input signal;
the first input end of the second multiplier is connected with the output end of the main channel buffer, and the second input end is used for receiving a preset amplitude and adjusting the amplitude of the input signal according to the preset amplitude.
8. The equalization method with the signal edge phases respectively adjustable is characterized by comprising the following steps of:
acquiring a first register value, a second register value, a size flag bit, a weighting direction selection bit and a compensation amplitude;
an input signal with preset amplitude is obtained, and a phase compensation signal is generated according to the input signal, the first register value, the second register value and the size marker bit, wherein the method comprises the following steps: generating a first delay signal and a second delay signal according to the input signal, the first register value and the second register value; performing logic operation on the first delay signal and the second delay signal according to the size flag bit to output the phase compensation signal;
and weighting the phase compensation signal with the input signal directly or after inverting according to the emphasis direction selection bit so as to control the phase of the input signal to be adjusted according to the compensation amplitude.
9. The method of equalizing signals with respective phases being adjustable according to claim 8, wherein the step of weighting the phase compensation signal directly or after inverting the phase compensation signal with the input signal according to the emphasis direction selection bit to control the phase of the input signal to be adjusted according to the compensation amplitude value comprises:
Outputting the phase compensation signal in the forward direction when the emphasis direction selection bit is a first preset value; when the weighting direction selection bit is a second preset value, inverting the phase compensation signal and outputting the inverted phase compensation signal;
controlling and adjusting the compensation amplitude according to the phase compensation signal;
adding the input signal and the adjusted compensation amplitude to compensate the edge phase of the input signal;
the first preset numerical representation performs pre-emphasis compensation on the input signal, and the second preset numerical representation performs de-emphasis compensation on the input signal.
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| CN116633314B (en) * | 2023-07-26 | 2023-10-10 | 厦门优迅高速芯片有限公司 | Self-adaptive continuous time linear equalization circuit |
| CN117238330B (en) * | 2023-11-14 | 2024-03-12 | 杭州广立微电子股份有限公司 | Chip time sequence adjusting device and chip |
| CN118100988B (en) * | 2024-04-25 | 2024-07-02 | 成都电科星拓科技有限公司 | Method for reducing forward crosstalk in communication and forward synthesis circuit |
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