CN102981551A - Temperature compensation system for real-time clock and method - Google Patents
Temperature compensation system for real-time clock and method Download PDFInfo
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Abstract
The invention discloses a temperature compensation system for a real-time clock. The temperature compensation system for the real-time clock comprises a repairing regulating register, a compensation interval register, a low-phase error repairing regulating mechanism controller, a crystal oscillator and a frequency repairing regulating circuit, wherein the repairing regulating register is used for storing an increasing and reducing pulse flag bit F and a repairing regulating data M; the compensation interval register is used for storing a compensation interval time value T; the low-phase error repairing regulating mechanism controller connected with the repairing regulating register is used for outputting a repairing regulating value m of a present second clock within the compensation interval time value T by judging the second clock corresponding to the compensation under the present state according to the size of the repairing regulating data; the crystal oscillator is used for generating a clock frequency; and the frequency repairing regulating circuit connected with a clock generator and the low-phase error repairing regulating mechanism controller is used for performing a pulse increasing and reducing operation on the clock outputted by the crystal oscillator according to the increasing and reducing pulse flag bit F and finally outputting an accurate low-phase error 1Hz clock when the repairing regulating value m of the present second clock is received by the frequency repairing regulating circuit.
Description
Technical field
The invention belongs to the electronic circuit technology field, particularly a kind of temperature-compensated system and method for the real-time clock for electronic circuit.
Background technology
Real-time clock (Real Time Clock is called for short RTC) is widely used critical elements in the electronic circuit, and it utilizes crystal to carry out function regularly.Crystal is at default hunting of frequency, and the mode by refresh counter realizes accurate timing.Owing to there is the characteristic of drifting about along with temperature variation in crystal frequency, so if real-time clock will obtain accurately 1Hz clock, just must carry out temperature compensation.
Usually adopt at present compensation scheme such as Fig. 1 in the technology.Real-time clock digital temperature compensation system shown in the figure forms, and comprises temperature sensor, ADC, ROM, compensating circuit, OSC, RTC functional circuit.Preserve the temperature variant data that trim of OSC in the ROM storer, temperature sensor is converted to digital signal through ADC with electric signal with the environment temperature switching electrical signals; 32.768kHz according to trimming the output of compensation data crystal oscillator finally exports accurately 1Hz clock.
In order to compensate the error of crystal oscillator output clock, at present in the compensating circuit technology commonly used, often adopting the compensation scheme of burst type, namely is in certain backoff interval in the cycle, by the increase of burst type in a certain second or the clock number of minimizing some, final frequency division obtains the 1Hz clock.This kind method can solve from macroscopic view the error of crystal oscillator output clock, finally obtain time 1Hz accurately, but the 1Hz clock phase error of this moment is very large.
In order to solve the problem of above-mentioned clock precision, a kind of method that on average trims that adopts has appearred.As being to disclose a kind of real-time clock calibration steps in 200810084325.7 the Chinese patent application file at number of patent application, the method is in certain backoff interval in the cycle, by the mean allocation value of trimming.If in certain backoff interval time T, there is the error of N clock period, then by on average getting the mode of merchant Q and remainder R, in second, increase or reduce Q clock at front T-1; At T second, increase or Q+R clock of minimizing.This kind mode can have been dwindled the phase error of the 1Hz clock that brings because of the increase and decrease pulse in a certain sense, but last second increase and decrease pulse number still has more R.The time interval, T was larger, and the remainder R variation range also will be larger, and the phase error that therefore may bring also will be larger.
Summary of the invention
The purpose of this invention is to provide a kind of real-time clock temperature-compensated system and method, can't solve the problem of real-time clock temperature compensation phase error to solve compensation method of the prior art.
Technical scheme of the present invention is, a kind of real-time clock temperature-compensated system, this system comprise that trimming register, backoff interval register, low phase error trims mechanism controller, crystal oscillator and frequency and trim circuit, wherein
Trim register, be used for storage increase and decrease pulse zone bit F and trim data M,
The backoff interval register is used for preserving backoff interval time value T,
Trim the low phase error that register links to each other and trim mechanism controller with described, in the make-up time interval T, by judging the second clock of corresponding compensation under the current state, and according to the size that trims data, export the value of the trimming m of current second of clock,
Crystal oscillator, for generation of clock frequency,
Trim the frequency that mechanism controller links to each other with clock generator and low phase error and trim circuit, when this frequency trims circuit and receives the value of the trimming m of current second clock, according to increase and decrease pulse zone bit F, the crystal oscillator output clock is increased and decreased pulse operation, the 1Hz clock of the precisely low phase error of final output.
Described low phase error trims mechanism controller and comprises, trims register updating block, a divider, a timer, two comparers, selector switch, the value of trimming m updating block and an increase and decrease pulse zone bit F updating block,
Described divider with trim the register updating block and link to each other with the backoff interval register, it is divisor that this divider definition trims register, the backoff interval register is dividend, final output merchant Q and remainder R,
Described timer is coupled between 1Hz clock and the comparer 1, and being used for timing, which second obtain current second clock be in the backoff interval time T, and when reaching time interval T, timer is since 1, and the timework of repetition is from 1 to T,
The first comparer in described two comparers and trims the register updating block and links to each other, and is used for more current second state and whether reaches the make-up time interval T, when reaching, upgrades trimming register,
The second comparer in described two comparers links to each other with timer with divider, and links to each other with selector switch again, is used for comparing under the present timing state, it is individual whether to reach remainder R,, cooperates the assignment value of trimming m=Q if reach with selector switch, if no, the assignment value of trimming m=Q+1 then
Described selector switch links to each other with divider with the second comparer, and selector switch links to each other with the value of trimming m updating block again.
Described increase and decrease pulse zone bit F updating block and trims the register updating block and links to each other with the 1Hz clock, is used for increase and decrease pulse zone bit F and the value of trimming synchronously.
Describedly trim mechanism controller with trimming the low phase error that register links to each other, workflow may further comprise the steps,
The first step, timer counting cnt, the first comparer is judged, for the make-up time interval T, when cnt=T, upgrade trimming register, trim register and will must discuss Q and remainder R through divider is final this moment, if cnt＜T preserves then that to trim register constant, merchant Q and remainder R also will remain unchanged;
Second step, the second comparer judge, as cnt during less than or equal to R, selector switch will select Q+1 assignment to trimming register m this moment, if during greater than R, then selector switch trims register m=Q with assignment;
Described low phase error trims the value of the trimming m in the mechanism controller, in backoff interval T time memory value of trimming at R Q+1, (T-R) value of trimming of individual Q.
In the backoff interval time T, if compare life period error delta T with standard time Ts, namely there is time error Δ t in Δ T=T-Ts in 1 seconds, satisfies
The N bit that trims register-stored trims data M, by low phase error trim mechanism controller obtain T in second p.s. the corresponding value of trimming m, m satisfies and concerns
A kind of real-time clock temperature compensation, based on the real-time clock temperature-compensated system, this system comprise trim register, backoff interval register, low phase error trims mechanism controller, crystal oscillator and frequency and trims circuit, wherein
Trim register, be used for storage increase and decrease pulse zone bit F and trim data M,
The backoff interval register is used for preserving backoff interval time value T,
Trim the low phase error that register links to each other and trim mechanism controller with described, in the make-up time interval T, by judging the second clock of corresponding compensation under the current state, and according to the size that trims data, export the value of the trimming m of current second of clock,
Crystal oscillator, for generation of clock frequency,
Trim the frequency that mechanism controller links to each other with clock generator and low phase error and trim circuit, when this frequency trims circuit and receives the value of the trimming m of current second clock, according to increase and decrease pulse zone bit F, the crystal oscillator output clock is increased and decreased pulse operation, the 1Hz clock of the precisely low phase error of final output
Described low phase error trims mechanism controller and comprises, trims register updating block, a divider, a timer, two comparers, selector switch, the value of trimming m updating block and an increase and decrease pulse zone bit F updating block,
Described divider with trim the register updating block and link to each other with the backoff interval register, it is divisor that this divider definition trims register, the backoff interval register is dividend, final output merchant Q and remainder R,
Described timer is coupled between 1Hz clock and the comparer 1, and being used for timing, which second obtain current second clock be in the backoff interval time T, and when reaching time interval T, timer is since 1, and the timework of repetition is from 1 to T,
The first comparer in described two comparers and trims the register updating block and links to each other, and is used for more current second state and whether reaches the make-up time interval T, when reaching, upgrades trimming register,
The second comparer in described two comparers links to each other with timer with divider, and links to each other with selector switch again, is used for comparing under the present timing state, it is individual whether to reach remainder R,, cooperates the assignment value of trimming m=Q if reach with selector switch, if no, the assignment value of trimming m=Q+1 then
Described selector switch links to each other with divider with the second comparer, and selector switch links to each other with the value of trimming m updating block again.
Described increase and decrease pulse zone bit F updating block and trims the register updating block and links to each other with the 1Hz clock, is used for increase and decrease pulse zone bit F and the value of trimming synchronously,
Describedly trim mechanism controller with trimming the low phase error that register links to each other, workflow may further comprise the steps,
The first step, timer counting cnt, the first comparer judge, when cnt=T, upgrade trimming register, trim register and will must discuss Q and remainder R through divider is final this moment, if cnt＜T preserves then that to trim register constant, discusss Q and remainder R and also will remain unchanged;
Second step, the second comparer judge, as cnt during less than or equal to R, selector switch will select Q+1 assignment to trimming register m this moment, if during greater than R, then selector switch trims register m=Q with assignment; Described low phase error trims the value of the trimming m in the mechanism controller, in backoff interval T time memory value of trimming at R Q+1, (T-R) value of trimming of individual Q.
In the backoff interval time T, if compare life period error delta T with standard time Ts, namely there is time error Δ t in Δ T=T-Ts in 1 seconds, satisfies
The N bit that trims register-stored trims data M, by low phase error trim mechanism controller obtain T in second p.s. the corresponding value of trimming m, m satisfies and concerns
The present invention has proposed a kind of brand-new value of trimming allocative decision, with a remainder R clock in order to reduce to a greater extent the phase difference between adjacent clock, be assigned to backoff interval in the time cycle, in cycle, there has been the value of trimming of R Q+1, (T-R) value of trimming of individual Q in backoff interval.This kind technical scheme, there is the time error of 1 clock at the most in the adjacent 1Hz clock period, has reduced greatly the phase error of 1Hz clock.
Description of drawings
Fig. 1 real-time clock digital temperature compensation system block diagram
The design real time clock circuit block diagram of Fig. 2 low phase error of the present invention
Fig. 3 low phase error of the present invention trims the mechanism controller structural drawing
Fig. 4 low phase error of the present invention trims the mechanism controller process flow diagram
Fig. 5 low phase error design real-time clock sequential chart of the present invention
Embodiment
Below with reference to description of drawings the preferred embodiments of the present invention, Fig. 2 provides system architecture diagram of the present invention, comprises in the structured flowchart: trim register, and the backoff interval register, low phase error trims mechanism controller, crystal oscillator, frequency trims circuit.
Trim register, this trims register by increase and decrease pulse zone bit F and trims data M and forms.
Backoff interval register, this register are used for preserving backoff interval time value T.
Trim mechanism controller with trimming the low phase error that register links to each other, in the make-up time interval T, by judging the second clock of corresponding compensation under the current state, and according to the size that trims data, export the value of the trimming m of current second of clock.
Crystal oscillator, this preference selects crystal oscillator as clock generator, for generation of clock frequency
Trim the frequency that mechanism controller links to each other with clock generator and low phase error and trim circuit, when frequency trims circuit and receives the value of the trimming m of current second clock, according to increase and decrease pulse zone bit F, the crystal oscillator output clock is increased and decreased pulse operation, the 1Hz clock of the precisely low phase error of final output.
Above-mentioned trim mechanism controller with trimming the low phase error that register links to each other, this structure such as Fig. 3, it comprises and trims the register updating block, a divider, a timer, two comparers, a selector switch, the value of trimming m updating block, increase and decrease pulse zone bit F updating block.
Above-mentioned low phase error trims the divider in the mechanism controller structural drawing 3, with trim the register updating block and link to each other with the backoff interval register, it is divisor that its definition of divider trims register, and the backoff interval register is dividend, final output merchant Q and remainder R.
Above-mentioned low phase error trims the timer in the mechanism controller structural drawing 3, be coupled between 1Hz clock and the comparer 1, which second obtains current second clock for timing is in the backoff interval time T, when reaching time interval T, timer is since 1, and the timework of repetition is from 1 to T.
Above-mentioned low phase error trims the comparer 1 in the mechanism controller structural drawing 3, and trims the register updating block and links to each other, and is used for more current second state and whether reaches the make-up time interval T, when reaching, upgrades trimming register.
Above-mentioned low phase error trims the comparer 2 in the mechanism controller structural drawing 3, links to each other with timer with divider, and links to each other with selector switch again, be used for comparing under the present timing state, it is individual whether to reach remainder R, if reach, cooperate the assignment value of trimming m=Q with selector switch; If no, the assignment value of trimming m=Q+1 then.
Above-mentioned low phase error trims the selector switch in the mechanism controller structural drawing 3, links to each other with divider with comparer 2, and selector switch links to each other with the value of trimming m updating block again.
Above-mentioned increase and decrease pulse zone bit F updating block, its with trim the register updating block and link to each other with the 1Hz clock, it will increase and decrease pulse zone bit F and the value of trimming synchronously.
Above-mentioned with trim the low phase error that register links to each other and trim mechanism controller, workflow such as Fig. 4.Low phase error trims mechanism controller and is divided into two large divisions's execution.
The first, timer counting cnt, comparer 1 judge, when cnt=T, upgrade trimming register, and trim register and will must discuss Q and remainder R through divider is final this moment; If cnt＜T preserves then that to trim register constant, merchant Q and remainder R also will remain unchanged.
The second, comparer 2 judges, as cnt during less than or equal to R, selector switch will select Q+1 assignment to trimming register m this moment, if during greater than R, then selector switch trims register m=Q with assignment.
Above-mentioned low phase error trims the value of the trimming m in the mechanism controller, in backoff interval T time memory value of trimming at R Q+1, (T-R) value of trimming of individual Q.
A kind of computing method of this preferred embodiment m value are such as sequential chart 5.
In certain backoff interval time T, if compare life period error delta T, Δ T=T-Ts with standard time Ts.In 1 seconds, there is time error Δ t, satisfies
The N bit that trims register-stored trims data M, by low phase error trim mechanism obtain T in second p.s. the corresponding value of trimming m, m satisfies and concerns
Shown almost homophase of the rear 1Hz clock of compensation and standard 1Hz clock in the sequential chart 5.When crystal oscillator output clock CLK frequency f
ClkLess than standard frequency fs, fs=32.768kHz, the Δ T of this moment〉0, i.e. Δ t〉0, should reduce the input of CLK pulse this moment; If when crystal oscillator output clock CLK frequency f
ClkGreater than standard frequency fs, the Δ T of this moment＜0, namely Δ t＜0 should increase the input of CLK pulse at this moment.More than two kinds of situations adopt the increase and decrease pulse zone bit F that trims in the register to be distinguished.
The design real-time clock technical scheme of low phase error of the present invention, adopt low phase error to trim mechanism, foundation trims data M and the make-up time interval T obtains average Q and remainder R, and mean allocation trims numerical value m, makes adjacent per second have at most the errors of 1 CLK clock period.The burst compensation way of this and current cumulative errors is compared, and has avoided the increase and decrease CLK clock pulses number of clock burst type in certain pulse per second (PPS) cycle, has reduced clock phase error, make adjacent per second reach one level and smooth excessively.This time scheme has namely improved the precision of clock, has reduced again the phase error of 1Hz clock, has improved on the whole the performance of clock.
Claims (6)
1. a real-time clock temperature-compensated system is characterized in that, this system comprise trim register, backoff interval register, low phase error trims mechanism controller, crystal oscillator and frequency and trims circuit, wherein
Trim register, be used for storage increase and decrease pulse zone bit F and trim data M,
The backoff interval register is used for preserving backoff interval time value T,
Trim the low phase error that register links to each other and trim mechanism controller with described, in the make-up time interval T, by judging the second clock of corresponding compensation under the current state, and according to the size that trims data, export the value of the trimming m of current second of clock,
Crystal oscillator, for generation of clock frequency,
Trim the frequency that mechanism controller links to each other with clock generator and low phase error and trim circuit, when this frequency trims circuit and receives the value of the trimming m of current second clock, according to increase and decrease pulse zone bit F, the crystal oscillator output clock is increased and decreased pulse operation, the 1Hz clock of the precisely low phase error of final output.
2. real-time clock temperature-compensated system as claimed in claim 1, it is characterized in that, described low phase error trims mechanism controller and comprises, trim register updating block, a divider, a timer, two comparers, selector switch, the value of trimming m updating block and an increase and decrease pulse zone bit F updating block
Described divider with trim the register updating block and link to each other with the backoff interval register, it is divisor that this divider definition trims register, the backoff interval register is dividend, final output merchant Q and remainder R,
Described timer is coupled between 1Hz clock and the comparer 1, and being used for timing, which second obtain current second clock be in the backoff interval time T, and when reaching time interval T, timer is since 1, and the timework of repetition is from 1 to T,
The first comparer in described two comparers and trims the register updating block and links to each other, and is used for more current second state and whether reaches the make-up time interval T, when reaching, upgrades trimming register,
The second comparer in described two comparers links to each other with timer with divider, and links to each other with selector switch again, is used for comparing under the present timing state, it is individual whether to reach remainder R,, cooperates the assignment value of trimming m=Q if reach with selector switch, if no, the assignment value of trimming m=Q+1 then
Described selector switch links to each other with divider with the second comparer, and selector switch links to each other with the value of trimming m updating block again.
Described increase and decrease pulse zone bit F updating block and trims the register updating block and links to each other with the 1Hz clock, is used for increase and decrease pulse zone bit F and the value of trimming synchronously.
3. real-time clock temperature-compensated system as claimed in claim 2 is characterized in that, describedly trims mechanism controller with trimming the low phase error that register links to each other, and workflow may further comprise the steps,
The first step, timer counting cnt, the first comparer is judged, for the make-up time interval T, when cnt=T, upgrade trimming register, trim register and will must discuss Q and remainder R through divider is final this moment, if cnt＜T preserves then that to trim register constant, merchant Q and remainder R also will remain unchanged;
Second step, the second comparer judge, as cnt during less than or equal to R, selector switch will select Q+1 assignment to trimming register m this moment, if during greater than R, then selector switch trims register m=Q with assignment;
Described low phase error trims the value of the trimming m in the mechanism controller, in backoff interval T time memory value of trimming at R Q+1, (T-R) value of trimming of individual Q.
4. real-time clock temperature-compensated system as claimed in claim 3 is characterized in that,
In the backoff interval time T, if compare life period error delta T with standard time Ts, namely there is time error Δ t in Δ T=T-Ts in 1 seconds, satisfies
The N bit that trims register-stored trims data M, by low phase error trim mechanism controller obtain T in second p.s. the corresponding value of trimming m, m satisfies and concerns
5. a real-time clock temperature compensation is characterized in that, based on the real-time clock temperature-compensated system, this system comprise trim register, backoff interval register, low phase error trims mechanism controller, crystal oscillator and frequency and trims circuit, wherein
Trim register, be used for storage increase and decrease pulse zone bit F and trim data M,
The backoff interval register is used for preserving backoff interval time value T,
Trim the low phase error that register links to each other and trim mechanism controller with described, in the make-up time interval T, by judging the second clock of corresponding compensation under the current state, and according to the size that trims data, export the value of the trimming m of current second of clock,
Crystal oscillator, for generation of clock frequency,
Trim the frequency that mechanism controller links to each other with clock generator and low phase error and trim circuit, when this frequency trims circuit and receives the value of the trimming m of current second clock, according to increase and decrease pulse zone bit F, the crystal oscillator output clock is increased and decreased pulse operation, the 1Hz clock of the precisely low phase error of final output
Described low phase error trims mechanism controller and comprises, trims register updating block, a divider, a timer, two comparers, selector switch, the value of trimming m updating block and an increase and decrease pulse zone bit F updating block,
Described divider with trim the register updating block and link to each other with the backoff interval register, it is divisor that this divider definition trims register, the backoff interval register is dividend, final output merchant Q and remainder R,
Described timer is coupled between 1Hz clock and the comparer 1, and being used for timing, which second obtain current second clock be in the backoff interval time T, and when reaching time interval T, timer is since 1, and the timework of repetition is from 1 to T,
The first comparer in described two comparers and trims the register updating block and links to each other, and is used for more current second state and whether reaches the make-up time interval T, when reaching, upgrades trimming register,
The second comparer in described two comparers links to each other with timer with divider, and links to each other with selector switch again, is used for comparing under the present timing state, it is individual whether to reach remainder R,, cooperates the assignment value of trimming m=Q if reach with selector switch, if no, the assignment value of trimming m=Q+1 then
Described selector switch links to each other with divider with the second comparer, and selector switch links to each other with the value of trimming m updating block again.
Described increase and decrease pulse zone bit F updating block and trims the register updating block and links to each other with the 1Hz clock, is used for increase and decrease pulse zone bit F and the value of trimming synchronously,
Describedly trim mechanism controller with trimming the low phase error that register links to each other, workflow may further comprise the steps,
The first step, timer counting cnt, the first comparer judge, when cnt=T, upgrade trimming register, trim register and will must discuss Q and remainder R through divider is final this moment, if cnt＜T preserves then that to trim register constant, discusss Q and remainder R and also will remain unchanged;
Second step, the second comparer judge, as cnt during less than or equal to R, selector switch will select Q+1 assignment to trimming register m this moment, if during greater than R, then selector switch trims register m=Q with assignment; Described low phase error trims the value of the trimming m in the mechanism controller, in backoff interval T time memory value of trimming at R Q+1, (T-R) value of trimming of individual Q.
6. real-time clock temperature compensation as claimed in claim 5 is characterized in that,
In the backoff interval time T, if compare life period error delta T with standard time Ts, namely there is time error Δ t in Δ T=T-Ts in 1 seconds, satisfies
The N bit that trims register-stored trims data M, by low phase error trim mechanism controller obtain T in second p.s. the corresponding value of trimming m, m satisfies and concerns
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104977978A (en) * | 2015-07-17 | 2015-10-14 | 上海无线电设备研究所 | Acquiring and processing method for non-synchronizing signals of system clock |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5327404A (en) * | 1990-11-27 | 1994-07-05 | Vlsi Technology, Inc. | On-chip frequency trimming method for real-time clock |
| US5481507A (en) * | 1993-11-29 | 1996-01-02 | Mitsubishi Denki Kabushiki Kaisha | Electronic timekeeping device reduced adjustment data storage requirement |
| CN101452307A (en) * | 2007-12-07 | 2009-06-10 | 联发科技股份有限公司 | System and method of calibrating real time clock utilizing average calibration |
| CN102638225A (en) * | 2012-04-01 | 2012-08-15 | 北京集创北方科技有限公司 | On-chip clock frequency regulating circuit and regulating method |
-
2012
- 2012-11-22 CN CN201210480377.2A patent/CN102981551B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5327404A (en) * | 1990-11-27 | 1994-07-05 | Vlsi Technology, Inc. | On-chip frequency trimming method for real-time clock |
| US5481507A (en) * | 1993-11-29 | 1996-01-02 | Mitsubishi Denki Kabushiki Kaisha | Electronic timekeeping device reduced adjustment data storage requirement |
| CN101452307A (en) * | 2007-12-07 | 2009-06-10 | 联发科技股份有限公司 | System and method of calibrating real time clock utilizing average calibration |
| CN102638225A (en) * | 2012-04-01 | 2012-08-15 | 北京集创北方科技有限公司 | On-chip clock frequency regulating circuit and regulating method |
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105572621A (en) * | 2014-10-11 | 2016-05-11 | 国家电网公司 | Compensation calibration method and compensation calibration device for RTC module applied in electric energy meter |
| CN104977978A (en) * | 2015-07-17 | 2015-10-14 | 上海无线电设备研究所 | Acquiring and processing method for non-synchronizing signals of system clock |
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| CN105223872B (en) * | 2015-10-19 | 2017-12-08 | 浙江卓奥科技股份有限公司 | A kind of electric terminal control panel square-wave generator |
| CN106444966A (en) * | 2016-09-30 | 2017-02-22 | 大唐微电子技术有限公司 | Device and method for adjusting real time clock (RTC) |
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| CN108255232A (en) * | 2017-12-06 | 2018-07-06 | 中国航空工业集团公司西安航空计算技术研究所 | A kind of precision improvement method of IEEE1588 time-codes timer |
| CN108599758A (en) * | 2018-02-10 | 2018-09-28 | 国网河南省电力公司郑州供电公司 | The algorithm and device of high-precision trigger pulse are generated based on GPS |
| CN108599758B (en) * | 2018-02-10 | 2022-11-22 | 国网河南省电力公司郑州供电公司 | Algorithm and device for generating high-precision trigger pulse based on GPS |
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