CN102006059B - Sigma delta controlled phase locked loop and calibration circuit and calibration method thereof - Google Patents

Abstract

The invention discloses a calibration circuit of a sigma delta controlled phase locked loop. The calibration circuit comprises a storage module, a pulse width modulation coefficient acquisition module, a calibration pulse amplitude processing module and a first adder. The storage module correspondingly stores calibration pulse amplitude and pulse width modulation coefficient, and the calibration pulse amplitude is acquired according to the difference between the actual output and the ideal output of a phase frequency discriminator; the pulse width modulation coefficient acquisition module calculates the pulse width modulation coefficient according to the output of a sigma delta modulator; the calibration pulse amplitude processing module searches and calls the corresponding calibration pulse amplitude according to the pulse width modulation coefficient, and generates a calibration compensation value according to the called calibration pulse amplitude; and the first adder adds the calibration compensation value and a decimal frequency division command. The invention also discloses a corresponding calibration method and the phase locked loop with the calibration circuit. The internal distortion of phase frequency discriminator (PFD) output due to pulse width modulation can be continuously counteracted so that the phase noise is reduced.

Description

A kind of phase-locked loop and calibration circuit and calibration steps of ∑ △ control

Technical field

The present invention relates to a kind of frequency synthesizer, relate in particular to a kind of phase-locked loop and calibration circuit and calibration steps of the ∑ Δ control for frequency synthesizer.

Background technology

Frequency synthesizer in the Wireless Telecom Equipment generally is used for reception and the emission of radiofrequency signal.When the radiofrequency signal that receives was down-converted to baseband signal, frequency synthesizer produced a reference waveform, usually was named as local oscillator, was used for deleting the carrier signal that receives signal.When frequency synthesizer was applied to radio signal transmission, the baseband signal uppermixing was to radiofrequency signal, and frequency synthesizer just is used to produce radio-frequency carrier.

Frequency synthesizer generally includes voltage controlled oscillator and phase-locked loop, and this phase-locked loop be used for to be measured the output frequency of voltage controlled oscillator, then provide a closed loop feedback signal to voltage controlled oscillator to adjust its output frequency.Along with the development of the communication technology, for the resolution of improving phase-locked loop to improve the frequency resolution of frequency synthesizer, existing phase-locked loop all adopts decimal frequency divider to carry out frequency division usually.Concrete, existing phase-locked loop structures as shown in Figure 1, comprise: frequency divider 11, ∑ Delta modulator 12, PFD (Phase Frequency Detector, phase frequency detector) 13 and pulse width modulator 14, frequency divider 11 is used for the output signal of voltage controlled oscillator is carried out frequency division to produce feedback signal, ∑ Delta modulator 12 is used for providing Frequency Dividing Factor to described frequency divider 11, the feedback signal that the more described frequency divider 11 of PFD13 produces and the phase difference of reference signal also are converted into pulse signal, reference clock is generally base when high steady, and pulse width modulator 14 is used for the pulse signal of described PFD13 output is carried out pulse-width modulation.Different from integer-N PLL, the decimal frequency divider of fractional frequency-division phase-locked loop produces by the ∑ Delta modulator, differing of PFD output is constantly to change, and the output pulse signal of PFD is subjected to present after the pulse width modulation non-linear, and the distortion that causes thus is called as the near-end distortion.Can carry out filtering by loop filter by the far-end distortion that the ∑ Delta modulator forms, however the near-end distortion but filtering do not fall, this has just increased the near-end phase noise of the output frequency of voltage controlled oscillator.The pulse-width modulation degree of depth is darker, affect more serious, generally on 4 rank or more the impact of high order modulation is larger.Therefore, demand urgently providing a kind of phase-locked loop of ∑ Δ control and calibration circuit thereof and calibration steps to overcome defects.

Summary of the invention

The technical problem to be solved in the present invention is to provide a kind of phase-locked loop and calibration circuit and calibration steps of ∑ Δ control, it carries out compensation for calibrating errors by the input data to the ∑ Delta modulator of described phase-locked loop, thereby simulate the ideal output and the output formation calibration of the actual difference of exporting to PFD of PFD at the PFD output, and then to the counteracting that the inside distortion that PFD output causes because of pulse width modulation continues, reduce phase noise.

In order to solve the problems of the technologies described above, the invention provides a kind of phase-locked loop of ∑ Δ control, it comprises frequency divider, ∑ Delta modulator, PFD, pulse width modulator and calibration circuit.Wherein, described frequency divider is used for the output signal of voltage controlled oscillator is carried out frequency division to produce feedback signal; Described ∑ Delta modulator is used for providing Frequency Dividing Factor according to input command for described frequency divider, and described input command comprises fractional frequency division order and integral frequency divisioil order; The phase difference that described PFD is used for feedback signal that more described frequency divider produces and reference signal is with the generation phase signal and be converted into pulse signal; Described pulse width modulator is used for the pulse signal of described PFD output is carried out pulse-width modulation.Described calibration circuit comprises memory module, pulse-width modulation coefficient acquisition module, calibration pulse amplitude processing module and first adder.Wherein, described memory module is used for calibrating pulse amplitude and pulse-width modulation coefficient corresponding stored, and described calibration pulse amplitude obtains according to the actual output of described phase frequency detector and the difference of desirable output; Described pulse-width modulation coefficient acquisition module is used for calculating the pulse-width modulation coefficient according to the output of ∑ Delta modulator; Described calibration pulse amplitude processing module is used for searching and call corresponding calibration pulse amplitude according to the pulse-width modulation coefficient that described pulse-width modulation coefficient acquisition module obtains in described memory module, and generates the compensation for calibrating errors value according to invoked calibration pulse amplitude; Compensation for calibrating errors value and described fractional frequency division order that described first adder is used for described calibration pulse amplitude processing module is generated are sued for peace.

The present invention also provides a kind of calibration circuit of phase-locked loop of ∑ Δ control, and it comprises memory module, pulse-width modulation coefficient acquisition module, calibration pulse amplitude processing module and first adder.Wherein, described memory module is used for calibrating pulse amplitude and pulse-width modulation coefficient corresponding stored, and described calibration pulse amplitude obtains according to the actual output of described phase frequency detector and the difference of desirable output; Described pulse-width modulation coefficient acquisition module is used for calculating the pulse-width modulation coefficient according to the output of ∑ Delta modulator; Described calibration pulse amplitude processing module is used for searching and call corresponding calibration pulse amplitude according to the pulse-width modulation coefficient that described pulse-width modulation coefficient acquisition module obtains in described memory module, and generates the compensation for calibrating errors value according to invoked calibration pulse amplitude; Compensation for calibrating errors value and described fractional frequency division order that described first adder is used for described calibration pulse amplitude processing module is generated are sued for peace.

The present invention also provides a kind of calibration steps of phase-locked loop of ∑ Δ control, and it may further comprise the steps: will calibrate pulse amplitude and pulse-width modulation coefficient corresponding stored; The pulse-width modulation coefficient is calculated in output according to the ∑ Delta modulator; Search corresponding calibration pulse amplitude according to described pulse-width modulation coefficient; Generate the compensation for calibrating errors value according to corresponding calibration pulse amplitude; And to the fractional frequency division order of described compensation for calibrating errors value and ∑ Delta modulator summation.

Compared with prior art, the phase-locked loop of ∑ Δ control of the present invention and calibrating installation thereof and calibration steps come to add the compensation for calibrating errors value at the input of ∑ Delta modulator by the actual output of simulation PFD and the difference of desirable output, thereby form a calibration stack at the pulse width modulator end, and then to the counteracting that the inside distortion that PFD output causes because of pulse width modulation continues, reduce phase noise.

By following description also by reference to the accompanying drawings, it is more clear that the present invention will become, and these accompanying drawings are used for explaining embodiments of the invention.

Description of drawings

Fig. 1 is the structured flowchart of existing phase-locked loop for frequency synthesizer;

Fig. 2 is the structured flowchart of an embodiment of the phase-locked loop of ∑ Δ of the present invention control;

Fig. 3 is the structured flowchart of calibration circuit of the phase-locked loop of ∑ Δ shown in Figure 2 control;

Fig. 4 is the detailed structure schematic diagram of the phase-locked loop of ∑ Δ control shown in Figure 2;

Fig. 5 is the schematic flow sheet of an embodiment of calibration steps of the phase-locked loop of ∑ Δ of the present invention control.

Embodiment

With reference now to accompanying drawing, describe embodiments of the invention, similar element numbers represents similar element in the accompanying drawing.As mentioned above, the invention provides a kind of phase-locked loop and calibration circuit and calibration steps of ∑ Δ control, it carries out compensation for calibrating errors by the input data to the ∑ Delta modulator of described phase-locked loop, thereby the difference in PFD output simulate ideal PFD output and actual PFD output is calibrated the output formation of PFD, and then to the counteracting that the inside distortion that PFD output causes because of pulse width modulation continues, reduce phase noise.

Elaborate the technical scheme of the embodiment of the invention below in conjunction with accompanying drawing.As shown in Figure 2, the phase-locked loop of the ∑ Δ of the present embodiment control comprises frequency divider 21, ∑ Delta modulator 22, PFD23, pulse width modulator 24 and calibration circuit 25.Wherein, described frequency divider 21 is used for the output signal of voltage controlled oscillator (figure does not look) is carried out frequency division to produce feedback signal; Described ∑ Delta modulator 22 is used for providing Frequency Dividing Factor according to input command for described frequency divider 21, and described input command comprises fractional frequency division order 0.F and integral frequency divisioil order N, and N, F are integer; The phase difference that described PFD23 is used for feedback signal that more described frequency divider 21 produces and reference signal is with the generation phase signal and be converted into pulse signal; Described pulse width modulator 24 is used for the pulse signal of described PFD23 output is carried out pulse-width modulation.

As shown in Figure 3, described calibration circuit 25 comprises memory module 251, pulse-width modulation coefficient acquisition module 252, calibration pulse amplitude processing module 253 and first adder 254.Wherein, described memory module 251 is used for calibrating pulse amplitude and pulse-width modulation coefficient corresponding stored, and described calibration pulse amplitude obtains according to the actual output of described PFD23 and the difference of desirable output; Described pulse-width modulation coefficient acquisition module 252 is used for calculating the pulse-width modulation coefficient according to the output of ∑ Delta modulator 22; Described calibration pulse amplitude processing module 253 is used for searching and call corresponding calibration pulse amplitude according to the pulse-width modulation coefficient that described pulse-width modulation coefficient acquisition module 252 obtains in described memory module 251, and generates the compensation for calibrating errors value according to invoked calibration pulse amplitude; Described first adder 254 is used for compensation for calibrating errors value and described fractional frequency division order 0.F that described calibration pulse amplitude processing module 253 generates are sued for peace.

Described input command comprises integral frequency divisioil order N and fractional frequency division order 0.F, and N, F are integer.Easily know, described input command can also comprise pseudo-random signal, also is called dither signal.In addition, each reference cycle of input command can only change once, and desirable calibration transition meeting is shorter, and the intermodulation of the output pulse of actual PFD is processed and is after one-period.

Further, as shown in Figure 4, described pulse modulation coefficient acquisition module 252 comprises accumulator 252a, integrator 252b and multiplier 252c.Wherein, described accumulator 252a is used for the Frequency Dividing Factor of ∑ Delta modulator 22 outputs and the difference of frequency division standard value N.F are added up; Described integrator 252b is used for the accumulation result of described accumulator 252a is carried out integration; Described multiplier 252c is used for calculating the pulse-width modulation factor alpha according to the integral result of the relation of reference signal frequency and voltage controlled oscillator output frequency and described integrator 252b.

When the MASH accumulator of the quantizer 221 of ∑ Delta modulator 22 was zero, it was zero that integrator 252b is set, and at this moment is very accurately.To calibrate offset and fractional frequency division order 0.F summation, then as the new input command of quantizer.Because 0≤0.F＜1, calibration may cause overflows, and for processing this phenomenon, the calibration circuit 25 of the present embodiment also comprises second adder 255, is used for overflowing and described integral frequency divisioil order N summation described first adder 254.

Fig. 5 is the schematic flow sheet of an embodiment of calibration steps of the phase-locked loop of ∑ Δ of the present invention control.As shown in Figure 5, the calibration steps of the present embodiment may further comprise the steps.

Step S101: will calibrate pulse amplitude and pulse-width modulation coefficient corresponding stored, described calibration pulse amplitude obtains according to the actual output of described phase frequency detector and the difference of desirable output.

Step S102: the pulse-width modulation coefficient is calculated in the output according to the ∑ Delta modulator.

Concrete, this step comprises the Frequency Dividing Factor of described ∑ Delta modulator output and the difference of frequency division standard value is added up; Accumulation result is carried out integration; And calculate the pulse-width modulation coefficient according to the relation of reference signal frequency and voltage controlled oscillator output frequency and integral result.

Step S103: search corresponding calibration pulse amplitude according to described pulse-width modulation coefficient.

Step S104: generate the compensation for calibrating errors value according to corresponding calibration pulse amplitude.

Step S105: to the fractional frequency division order summation of described compensation for calibrating errors value and ∑ Delta modulator.

When the fractional frequency division order summation of described compensation for calibrating errors value and ∑ Delta modulator is overflowed, with the integral frequency divisioil order summation of overflow position and described ∑ Delta modulator.

The calibrating principle of phase-locked loop of the ∑ Δ control of the present embodiment is described below.At first, obtain the calibration pulse sequence according to the actual output of PFD and the difference of desirable output, and with pulse amplitude and pulse-width modulation factor alpha corresponding stored in described memory module.Concrete, calibration pulse sequence S _kFourier transform be:

$H\left(\mathrm{\ω}\right)=\underset{k=1}{\overset{3}{\mathrm{\Σ}}}{s}_k{e}^{\mathrm{j\ωk}}---\left(1\right)$

Frequency and time are carried out normalization:

τ＝1

0≤ω≤π，

The Fourier transform H of the desirable PFD output that calibration pulse width Delta t is corresponding _N(ω) and the Fourier transform H of actual PFD output _U(ω) as follows respectively:

$H_N\left(\mathrm{\&omega;}\right)=\frac{1}{\mathrm{i\&omega;}}({\mathrm{<figure-callout\; id="1"\; label="e"\; filenames="HSA00000279555500022.png"\; state="\{\{state\}\}">e</figure-callout>}}^{\frac{1}{2}\mathrm{i\&omega;\&alpha;}}-e^{-\frac{1}{2}\mathrm{i\&omega;\&alpha;}})---\left(2\right)$

$H_U\left(\mathrm{\&omega;}\right)=\frac{1}{\mathrm{i\&omega;}}(e^{\mathrm{j\&omega;\&alpha;}}-1)---\left(3\right)$

H(ω)＝H _N(ω)-H _U(ω) (4)

Each pulse duration is corresponding with unique a series of calibration pulses, and pulse amplitude is generally certain value, is subjected to hardware constraints, is stored among the memory module ROM251.

Under Chebyshev (Chebyshev) pattern, 0 to ω _MaxCoupling is 50 times in the scope, ω _MaxBe maximum collimation angle frequency, can calculate the angular frequency of calibration by formula (5):

${\mathrm{\&omega;}}_r={\mathrm{\&omega;}}_{\max }\cos \left[(r-\frac{1}{2})\frac{\mathrm{\&pi;}}{100}\right]---\left(5\right)$

Wherein, r represents the number of times that mates.

Export s1 in order to obtain pulse, s2, s3 must obtain s1, s2-s1, s3-s2 ,-s3, the coefficient of these acquisitions must be stored among the ROM.The ROM address, i.e. pulse-width modulation factor alpha and ROM output { s _kNormalization all.{ s _kAnd α just can obtain good result as long as guarantee 6bit, do not need with the decimal order of ∑ Delta modulator equally wide.

The output frequency f of the frequency of reference signal and voltage controlled oscillator VCO _VCORelation as follows:

$f_{\mathrm{VCO}}=\frac{1}{{\mathrm{\&tau;}}_{\mathrm{VCO}}}=\frac{N+0.F}{{\mathrm{\&tau;}}_{\mathrm{REF}}}---\left(6\right)$

Suppose that phase-locked loop locks, voltage controlled oscillator is that stable and order able to programme are constant, and cycle reference signal is so:

At t _V(k) VCO carries out frequency division the k time constantly, and reference signal frequency is at t _R(k) constantly just carry out the k time frequency division, just have with reference to Fig. 4 so:

$\frac{t_V\left(k\right)}{{\mathrm{\&tau;}}_{\mathrm{VCO}}}=\frac{N+\mathrm{\&Delta;N}\left(k\right)}{1-z^{-1}}---\left(7\right)$

$\frac{t_R\left(k\right)}{{\mathrm{\&tau;}}_{\mathrm{VCO}}}=\frac{N+0.F}{1-z^{-1}}---\left(8\right)$

Δt(k)＝t _V(k)-t _R(k) (9)

$\frac{\mathrm{\&Delta;t}\left(k\right)}{{\mathrm{\&tau;}}_{\mathrm{VCO}}}=\frac{\mathrm{\&Delta;N}\left(k\right)-0.F}{1-z^{-1}}---\left(10\right)$

Δ t (k) is at the k time width of VCO cycle PFD output pulse, ROM address so, i.e. pulse-width modulation factor alpha=Δ t (k)/τ _REF

Described calibration pulse amplitude processing module 253 searches and calls corresponding calibration pulse amplitude according to this pulse-width modulation coefficient in described memory module 251, and generates the compensation for calibrating errors value according to invoked calibration pulse amplitude.With reference to Fig. 4, use equation (10) can calculate the output pulse of PFD, to Δ N+N '-N.F integration, when the MASH of quantizer accumulator 221 was zero, it was zero that integrator 251b is set, and at this moment is very accurately.To calibrate offset and fractional frequency division order 0.F summation, 0.F is as the new input command of quantizer 251.

As 4 rank as example, its formula is as follows take quantizer:

ΔN(k)＝0.F(k)+e ₄(k)(1-z ^-1) ⁴ (11)

ΔN(k)＝0.F(k)+e _q(k) (12)

Wherein: quantizing output Δ N is signed number, and 0.F is signless decimal order, 0≤0.F＜1, e ₄The white noise of last accumulator, e _qIt is the quantizing noise that rises with the 80dB/decade slope.Because the MASH quantizer has desirable step response, the reaction that any change of 0.F can both be very fast is at the output of MASH quantizer, and quantizing output Δ N is the width of 4bit, and the input of 0.F decimal is 32bit.Obviously, described quantizer also can be high-order more.The present invention is successful in the high order modulation on 4 rank or more, can improve more than the 20dB at the near-end phase noise according to the pattern of Fig. 4.

Above disclosed is preferred embodiment of the present invention only, certainly can not limit with this interest field of the present invention, and the equivalent variations of therefore doing according to claim of the present invention still belongs to the scope that the present invention is contained.

Claims (3)

1. phase-locked loop that is used for the ∑ Delta modulator control of frequency synthesizer comprises:

Frequency divider is used for the output signal of voltage controlled oscillator is carried out frequency division to produce feedback signal;

The ∑ Delta modulator is used for providing Frequency Dividing Factor according to input command for described frequency divider, and described input command comprises fractional frequency division order and integral frequency divisioil order;

Phase frequency detector, the phase difference that is used for feedback signal that more described frequency divider produces and reference signal is with the generation phase signal and be converted into pulse signal; And

Pulse width modulator is used for the pulse signal of described phase frequency detector output is carried out pulse-width modulation;

It is characterized in that, also comprise calibration circuit, described calibration circuit comprises:

Memory module, for the pulse-width modulation coefficient corresponding stored that will calibrate pulse amplitude and described pulse width modulator, described calibration pulse amplitude obtains according to the actual output of described phase frequency detector and the difference of desirable output;

Pulse-width modulation coefficient acquisition module comprises:

Accumulator is used for the Frequency Dividing Factor of ∑ Delta modulator output and the difference of frequency division standard value are added up;

Integrator is used for the accumulation result of described accumulator is carried out integration;

Multiplier is used for calculating the pulse-width modulation coefficient according to the relation of reference signal frequency and voltage controlled oscillator output frequency and the integral result of described integrator;

Calibration pulse amplitude processing module is used for searching and call corresponding calibration pulse amplitude according to the pulse-width modulation coefficient that described pulse-width modulation coefficient acquisition module obtains in described memory module, and generates the compensation for calibrating errors value according to invoked calibration pulse amplitude; And adder,

Adder comprises first adder and second adder, compensation for calibrating errors value and described fractional frequency division order that first adder is used for described calibration pulse amplitude processing module is generated are sued for peace, if the generation carry, second adder is used for carry and the integral frequency divisioil order addition with first adder.

2. the calibration circuit of the phase-locked loop of a ∑ Δ control is characterized in that, comprising:

Memory module, for the pulse-width modulation coefficient corresponding stored that will calibrate pulse amplitude and pulse width modulator, described calibration pulse amplitude obtains according to the actual output of phase frequency detector and the difference of desirable output;

Pulse-width modulation coefficient acquisition module comprises:

Accumulator is used for the Frequency Dividing Factor of ∑ Delta modulator output and the difference of frequency division standard value are added up;

Integrator is used for the accumulation result of described accumulator is carried out integration;

Multiplier is used for calculating the pulse-width modulation coefficient according to the relation of reference signal frequency and voltage controlled oscillator output frequency and the integral result of described integrator;

Calibration pulse amplitude processing module is used for searching and call corresponding calibration pulse amplitude according to the pulse-width modulation coefficient that described pulse-width modulation coefficient acquisition module obtains in described memory module, and generates the compensation for calibrating errors value according to invoked calibration pulse amplitude; And adder,

Adder comprises first adder and second adder, the compensation for calibrating errors value and the fractional frequency division order that are used for described calibration pulse amplitude processing module is generated are sued for peace, compensation for calibrating errors value and fractional frequency division order that first adder is used for described calibration pulse amplitude processing module is generated are sued for peace, if the generation carry, second adder is used for carry and the integral frequency divisioil order addition with first adder.

3. the calibration steps of the phase-locked loop of a ∑ Δ control is characterized in that, may further comprise the steps:

Compare the actual output of feedback signal of frequency divider generation and the phase difference of reference signal by phase frequency detector, this phase signal is converted to pulse signal;

Obtain the calibration pulse amplitude according to described pulse signal;

To calibrate pulse amplitude and pulse-width modulation coefficient corresponding stored;

Calculate the pulse-width modulation coefficient according to the output of ∑ Delta modulator, the pulse-width modulation factor alpha be width Delta t (k) and the cycle reference signal τ in VCO phase frequency detector output pulse the k time in the cycle _REFRatio, i.e. α=Δ t (k)/τ _REF

Search corresponding calibration pulse amplitude according to described pulse-width modulation coefficient;

Generate the compensation for calibrating errors value according to corresponding calibration pulse amplitude; And

Fractional frequency division order summation to described compensation for calibrating errors value and ∑ Delta modulator; When summed result is overflowed, the integral frequency divisioil order of overflow position and described ∑ Delta modulator is sued for peace, and summed result is inputted in the quantizer, as the new input command of quantizer.

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