CN106209082B - Phase-locked loop circuit - Google Patents
Phase-locked loop circuit Download PDFInfo
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- CN106209082B CN106209082B CN201610536439.5A CN201610536439A CN106209082B CN 106209082 B CN106209082 B CN 106209082B CN 201610536439 A CN201610536439 A CN 201610536439A CN 106209082 B CN106209082 B CN 106209082B
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- 238000006243 chemical reaction Methods 0.000 claims abstract description 29
- 230000005669 field effect Effects 0.000 claims description 62
- 238000003708 edge detection Methods 0.000 claims description 32
- 230000000630 rising effect Effects 0.000 claims description 25
- 230000000694 effects Effects 0.000 claims description 9
- 210000001367 artery Anatomy 0.000 claims description 4
- 210000003462 vein Anatomy 0.000 claims description 4
- 238000001514 detection method Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000010355 oscillation Effects 0.000 description 4
- 230000005611 electricity Effects 0.000 description 3
- 238000001914 filtration Methods 0.000 description 2
- 238000001228 spectrum Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 1
- 230000007850 degeneration Effects 0.000 description 1
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- 238000012986 modification Methods 0.000 description 1
- 230000000306 recurrent effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
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Abstract
The invention discloses a kind of phase-locked loop circuits, it includes phase discriminator, low-pass filter and voltage controlled oscillator, external reference clock inputs an input terminal of phase discriminator, the output end of phase discriminator and the input terminal of low-pass filter connect, the output end of low-pass filter and the input terminal of voltage controlled oscillator connect, and the output end of voltage controlled oscillator and another input terminal of phase discriminator connect；Wherein further include way selectors, voltage/pulse width conversion device, pulsewidth/electric pressure converter and local oscillator, the input terminal of way selectors and the output end of phase discriminator connect, the output end of way selectors is selectively connect with the input terminal of the input terminal of low-pass filter or pulsewidth/electric pressure converter, the output end of pulsewidth/electric pressure converter is connect with the input terminal of voltage/pulse width conversion device, and the output end of voltage/pulse width conversion device and the input terminal of low-pass filter connect.The phase-locked loop circuit of the present invention reduces the high fdrequency component of voltage controlled oscillator input terminal control signal, reduces the reference spur of phase-locked loop circuit output signal, the frequency of output signal is more stable and reliable.
Description
Technical field
The present invention relates to integrated circuit fields, relate more specifically to a kind of phase-locked loop circuit.
Background technology
Referring to FIG. 1, Fig. 1 is the structure chart of the phase-locked loop circuit of the prior art, as shown, existing phase-locked loop circuit
It is made of phase discriminator, low-pass filter (being made of in Fig. 1 resistance R1 and capacitance C1) and voltage controlled oscillator three parts.Mirror
Two input terminals of phase device respectively with the output end of phase-locked loop circuit (namely output end of voltage controlled oscillator) and external reference
Clock source is connected, and the reference clock signal that external reference clock source is generated is input to phase discriminator, when phase discriminator will refer to
The difference conversion pulsewidth of the phase Φ out of the phase Φ ref and voltage controlled oscillator output signal OUT of clock source signal REF are △ Φ, week
Phase be reference clock source frequency Fref pulse signal V1 (i.e. the voltage pulse signal of node V1), V1 waveforms as shown in Fig. 2, its
In：
△ Φ=Φ ref- Φ out,
T=1/Fref.
The radio-frequency component of low-pass filter suppressor pulse signal V1 simultaneously retains its low-frequency component so that its output node voltage
Signal V2 has smaller shake ripple.According to the DC component size of voltage signal V2, generate a period shakes voltage controlled oscillator
Signal is swung, frequency of oscillation Fout and phase Φ out meet following relationship respectively：
Fout=K*V2dc(V2dcIndicate the DC component of V2)
Phase-locked loop circuit generally degeneration factor, when the phase difference of reference clock signal and voltage controlled oscillator output signal
When changing, the negative-feedback characteristic of phase-locked loop circuit can inhibit the variation, finally so that phase difference △ Φ are a fixed value, from
And make Fout=Fref, achieve the purpose that phase and frequency locks.
It is one of the shortcomings that phase-locked loop circuit shown in Fig. 1 in the frequency spectrum of its output signal other than Fout, there is also
Centered on Fout, deviate the spurious frequency signal of integral multiple reference clock signal frequency Fref, as shown in Figure 3.Spuious generation
The reason of be non-ideal characteristic because of the low-pass filter of class phase-locked loop circuit.Pulse signal V1 after low-pass filter,
High fdrequency component can only be suppressed and not be completely eliminated.Since pulse signal V1 is the recurrent pulse letter for being 1/Fref in the period
Number, Fourier's variation, high frequency division are carried out to it
Amount can be expressed as
(Ak indicates the amplitude of high fdrequency component, and size is related with the amplitude of pulse signal V1, and t indicates that time, k are just whole
Number)
Ignore other high fdrequency components, it is A1*cos (2* π * Fref*t) only to study maximum high fdrequency component, when it is logical
After crossing low-pass filter, amplitude becomesTherefore V2 includes the height that amplitude is B1
Frequency component, the high fdrequency component can modulate the input terminal of voltage controlled oscillator so that when its output frequency has deviation integral multiple reference
The spurious frequency signal of clock source signal frequency Fref.And the presence of spurious frequency signal can influence phase-locked loop circuit output spectrum
Pure property so that the cycle of oscillation of output is unstable.
Therefore, it is necessary to provide a kind of improved phase-locked loop circuit to overcome drawbacks described above.
Invention content
The object of the present invention is to provide a kind of phase-locked loop circuit, it is defeated that phase-locked loop circuit of the invention reduces voltage controlled oscillator
The high fdrequency component for entering end control signal, reduces the stray power of voltage controlled oscillator output signal, it is defeated to reduce phase-locked loop circuit
Go out the reference spur of signal, the frequency of output signal is more stable and reliable.
To achieve the above object, the present invention provides a kind of phase-locked loop circuit, including phase discriminator, low-pass filter and voltage-controlled
Oscillator, external reference clock input an input terminal of the phase discriminator, the output end of the phase discriminator and the low-pass filtering
The input terminal of device connects, and the output end of the low-pass filter is connect with the input terminal of the voltage controlled oscillator, described voltage-controlled to shake
The output end for swinging device connect with another input terminal of the phase discriminator and exports the output signal of the phase-locked loop circuit；Wherein institute
It further includes way selectors, voltage/pulse width conversion device, pulsewidth/electric pressure converter and local oscillator to state phase-locked loop circuit, described
The input terminal of way selectors is connect with the output end of the phase discriminator, the output ends of the way selectors selectively with institute
State low-pass filter input terminal or the pulsewidth/electric pressure converter input terminal connection, the pulsewidth/electric pressure converter it is defeated
Outlet is connect with the input terminal of the voltage/pulse width conversion device, and the local oscillator exports local oscillated signal to described
The output end of voltage/pulse width conversion device, the voltage/pulse width conversion device is connect with the input terminal of the low-pass filter.
Preferably, the phase-locked loop circuit is operable with general mode and low spurious pattern, when the phase-locked loop circuit work
When making in general mode, the output end of the way selectors is connect with the input terminal of the low-pass filter, when the locking phase
When loop circuit works in low spurious pattern, the input terminal of the output end of the way selectors and the pulsewidth/electric pressure converter
Connection.
Preferably, pulsewidth/the electric pressure converter includes current source, first switch, second switch, third switch, first
Capacitance, the second capacitance, failing edge detection unit and rising edge detection unit；The output end of the way selectors selectively with
The input terminal of the failing edge detection unit connects, the output end of the failing edge detection unit and the rising edge detection unit
Input terminal connection；Described current source one end is connect with external power supply, and the other end is connect with one end of the first switch, institute
The other end for stating first switch is connect with one end of first capacitance, the other end ground connection of first capacitance；Described second
One end of switch is connect with one end that the third switchs, and the other end of the second switch and one end of second capacitance connect
Connect and formed the output end of the pulsewidth/electric pressure converter；The other end of second capacitance, the other end of third switch connect
Ground.
Preferably, the pulse signal of the way selectors output controls the ON/OFF of the first switch, the failing edge
The pulse signal of detection unit output controls the ON/OFF of the second switch, the pulse letter of the rising edge detection unit output
The ON/OFF of number control third switch.
Preferably, the first switch, second switch and third switch are controlled when signal is high level at it and are closed.
Preferably, the failing edge detection unit include the first phase inverter, the second phase inverter, third phase inverter and first with
Door, first phase inverter are connect with the output end of the way selectors with the input terminal of the second phase inverter, and described first
The output end of phase inverter is connect with described first with an input terminal of door；The output end of second phase inverter and the third are anti-
The input terminal of phase device connects, and the output end of the third phase inverter is connect with described first with another input terminal of door；Described
One connect with the output end of door with the input terminal of the rising edge detection unit, and exports pulse signal control described second and open
The ON/OFF of pass.
Preferably, the rising edge detection unit includes the 4th phase inverter and second and door, described first with the output of door
End connect respectively with an input terminal of door with the input terminal of the 4th phase inverter, described second, the 4th phase inverter it is defeated
Outlet is connect with described second with another input terminal of door, described in the described second output end output one pulse signal control with door
The ON/OFF of third switch.
Preferably, the voltage/pulse width conversion device includes the first field-effect tube, the 5th phase inverter and hex inverter, institute
The source electrode for stating the first field-effect tube is connect with external power supply, and the grid of first field-effect tube is converted with the pulsewidth/voltage
The output end of device connects, and the drain electrode of first field-effect tube is connect with the control terminal of the 5th phase inverter, and the described 5th is anti-
The input terminal of phase device is connect with the local oscillator, the input of the output end and the hex inverter of the 5th phase inverter
End connection, the output end of the hex inverter are connect with the input terminal of the low-pass filter.
Preferably, the 5th phase inverter includes the second field-effect tube and third field-effect tube, second field-effect tube
Source electrode ground connection, the grid of second field-effect tube connect with the grid of the third field-effect tube and with the local oscillations
Device connects, the drain electrode of second field-effect tube connected with the drain electrode of the third field-effect tube and with the hex inverter
Input terminal connects, and the source electrode of the third field-effect tube is connect with the drain electrode of first field-effect tube.
Preferably, the hex inverter includes the 4th field-effect tube and the 5th field-effect tube, the 5th field-effect tube
Source electrode ground connection, the grid of the 4th field-effect tube connect with the grid of the 5th field-effect tube and with described second effect
Should pipe people drain connection, the drain electrode of the 4th field-effect tube connect with the drain electrode of the 5th field-effect tube and with the low pass
The input terminal of filter connects, and the source electrode of the 4th field-effect tube is connect with external power supply.
Compared with prior art, phase-locked loop circuit of the invention is due to further including way selectors, voltage/pulse width conversion
Device, pulsewidth/electric pressure converter and local oscillator so that can be selected in the phase discriminator and low pass by the way selectors
Voltage/pulse width conversion device, pulsewidth/electric pressure converter and local oscillator are connected between filter, and it is defeated to increase the phase discriminator
The frequency for going out signal reduces the high fdrequency component of input voltage controlled oscillator signal, reduces the miscellaneous of voltage controlled oscillator output signal
Power is dissipated, to reduce the reference spur of phase-locked loop circuit output signal.
By description below and in conjunction with attached drawing, the present invention will become more fully apparent, these attached drawings are for explaining the present invention
Embodiment.
Description of the drawings
Fig. 1 is the structure chart of prior art phase-locked loop circuit.
Fig. 2 is the oscillogram of the phase discriminator output pulse signal of prior art phase-locked loop circuit.
Fig. 3 is the spectrogram of the output signal of prior art phase-locked loop circuit.
Fig. 4 is the structure chart of phase-locked loop circuit of the present invention.
Fig. 5 is the circuit diagram of pulsewidth/electric pressure converter of phase-locked loop circuit of the present invention.
Fig. 6 is the circuit diagram of voltage/pulse width conversion device of phase-locked loop circuit of the present invention.
Specific implementation mode
The embodiment of the present invention described referring now to the drawings, similar element numbers represent similar element in attached drawing.Such as
Upper described, the present invention provides a kind of phase-locked loop circuit, the present invention passes through voltage/pulse width conversion under low spurious operating mode
Device, pulsewidth/electric pressure converter make the frequency multiplication of the pulse signal of phaselocked loop phase detector circuit output, reduce voltage controlled oscillation
Device input terminal controls the high fdrequency component of signal, the stray power of voltage controlled oscillator output signal is reduced, to reduce phaselocked loop
The reference spur of circuit output signal.
Referring to FIG. 4, Fig. 4 is the structure chart of phase-locked loop circuit of the present invention.As shown, the phase-locked loop circuit packet of the present invention
Include phase discriminator PD, low-pass filter LPF, voltage controlled oscillator VCO, way selectors MUX, voltage/pulse width conversion device VPC, pulsewidth/
Electric pressure converter PVC and local oscillator LO, external reference clock Fref input an input terminal of the phase discriminator PD；The mirror
The output end of phase device PD is connect with the input terminal of the low-pass filter LPF, the output end of the low-pass filter LPF with it is described
The input terminal of voltage controlled oscillator VCO connects, another input terminal of the output end of the voltage controlled oscillator VCO and the phase discriminator PD
Connect and export the output signal Fout of the phase-locked loop circuit；In addition, the output end of the phase discriminator PD and the low pass filtered
Way selectors MUX, voltage/pulse width conversion device VPC, pulsewidth/electric pressure converter are also associated between the input terminal of wave device LPF
PVC and local oscillator L0；Specifically, the input terminal of the way selectors is connect with the output end of the phase discriminator PD, institute
State the output ends of way selectors selectively with the input terminal of the low-pass filter LPF or the pulsewidth/electric pressure converter
The input terminal of PVC connects, the input of the output end of the pulsewidth/electric pressure converter PVC and the voltage/pulse width conversion device VPC
End connection, and local oscillator LO output local oscillated signal Fe to the voltage/pulse width conversion device VPC, the voltage/
The output end of pulse width conversion device VPC is connect with the input terminal of the low-pass filter LPF.In addition, the phaselocked loop of the present invention
Circuit is operable with general mode and low spurious pattern, when the phase-locked loop circuit works in general mode, the access choosing
The output end for selecting device MUX is connect with the input terminal of the low-pass filter LPF, when the phase-locked loop circuit works in low spurious mould
When formula, the output end of the way selectors MUX is connect with the input terminal of the pulsewidth/electric pressure converter VPC；That is, working as institute
When stating phase-locked loop circuit and working in low spurious pattern, by the way selectors MUX the phase discriminator PD output end with
Voltage/pulse width conversion device VPC, pulsewidth/electric pressure converter PVC and sheet are connected between the input terminal of the low-pass filter LPF
Ground oscillator L0；To increase the phase discriminator by the voltage/pulse width conversion device VPC and pulsewidth/electric pressure converter PVC
The frequency of PD output signals reduces the high fdrequency component of input voltage controlled oscillator VCO signal, it is defeated to reduce voltage controlled oscillator VCO
The stray power for going out signal, to reduce the reference spur of phase-locked loop circuit output signal Fout.
Please in conjunction with reference to figure 5, Fig. 5 is the circuit diagram of pulsewidth/electric pressure converter of phase-locked loop circuit of the present invention.As schemed
Show, the pulsewidth/electric pressure converter PVC includes current source IS, first switch S1, second switch S2, third switch S3, the first electricity
Hold CS1, the second capacitance CS2, failing edge detection unit and rising edge detection unit；The output end of the way selectors MUX can
It is selectively connect with the input terminal of the failing edge detection unit, to low miscellaneous when selecting the phase-locked loop circuit of the present invention to work in
When dissipating pattern, the way selectors MUX outputs it signal V1X and is input to the failing edge detection unit.The failing edge
The output end of detection unit is connect with the input terminal of the rising edge detection unit, in the present invention, when the input failing edge
When the voltage value of detection unit from high level variation is low level while becoming low from height (namely the voltage of signal V1X), output
End will produce the pulse signal VA1 of a high level；And when the voltage value (pulse for the input terminal for inputting the rising edge detection unit
The voltage value of signal VA1) when by low level variation being high level, it is high that the output end of the rising edge detection unit then will produce one
The pulse signal VA2 of level.The one end the current source IS is connect with external power supply VDD, the other end and the first switch S1
One end connection, the other end of the first switch S1 connect with one end of the first capacitance CS1, the first capacitance CS1
The other end ground connection；One end of the second switch CS2 is connect with one end of the third switch S3, the second switch S2's
The other end connect with one end of the second capacitance CS2 and forms the output end of the pulsewidth/electric pressure converter PVC, and exports
Signal V2X；The other end of the second capacitance CS2, the other end of third switch S3 are grounded.One as the present invention is preferably
The pulse signal V1X of embodiment, the way selectors MUX outputs controls the ON/OFF of the first switch S1, the decline
The ON/OFF of the second switch S2 is controlled along the pulse signal VA1 of detection unit output, the rising edge detection unit output
Pulse signal VA2 controls the ON/OFF of the third switch S3；And the first switch S1, second switch S2 and third switch S3
It controls when signal is high level and is closed at it；That is, when signal V1X is high level, the first switch S1 is closed, and works as arteries and veins
When to rush signal VA1 be high level, the second switch S2 is closed, when pulse signal VA2 is high level, the third switch S3
It is closed.
Specifically：
The failing edge detection unit include the first phase inverter X1, the second phase inverter X2, third phase inverter X3 and first with
Door A1, the first phase inverter X1 connect with the output end of the way selectors MUX with the input terminal of the second phase inverter X2,
The output end of the first phase inverter X1 is connect with described first with an input terminal of door A1；The output of the second phase inverter X2
End is connect with the input terminal of the third phase inverter X3, and the output end of the third phase inverter X3 is another with door A1 with described first
One input terminal connects；Described first connect with the output end of door A1 with the input terminal of the rising edge detection unit, and exports one
Pulse signal VA1 controls the ON/OFF of the second switch S2.To as input the first phase inverter X1 and the second phase inverter X2
The voltage of signal V1X when becoming low from height, described first with the pulse that the pulse signal VA1 of door A1 outputs is a high level.
The rising edge detection unit includes the 4th phase inverter X4 and second and door A2, the output end of described first and door A1
It is connect respectively with an input terminal of door A2 with the input terminal of the 4th phase inverter X4, described second, by the pulse signal
VA1 is input to the input terminal of the 4th phase inverter X4, described second and an input terminal of door A2；The 4th phase inverter X4's
Output end is connect with described second with another input terminal of door A2, and the output end of described second and door A2 exports a pulse signal
VA2 controls the ON/OFF of the third switch S3.To be high level when the voltage value of pulse signal VA1 is changed by low level
When, the pulse signal VA2 that described second and door A2 is exported is the pulse of a high level.
Please in conjunction with reference to figure 6, Fig. 6 is the circuit diagram of voltage/pulse width conversion device of phase-locked loop circuit of the present invention.As schemed
Show, the voltage/pulse width conversion device includes the first field-effect tube M1, the 5th phase inverter and hex inverter, first effect
Should the source electrode of pipe M1 connect with external power supply VDD, grid and the pulsewidth/electric pressure converter of the first field-effect tube M1
The output end of PVC connects, i.e., the described signal V2X is input to the grid of the first field-effect tube M1；First field-effect tube
The drain electrode of M1 is connect with the control terminal of the 5th phase inverter, input terminal and the local oscillator LO of the 5th phase inverter
Local oscillated signal Ft is input to the 5th phase inverter by connection, the local oscillator LO, the 5th phase inverter it is defeated
Outlet is connect with the input terminal of the hex inverter, and the output end of the hex inverter is with the low-pass filter LPF's
Input terminal connects.
Specifically, the 5th phase inverter includes the second field-effect tube M2 and third field-effect tube M3, second effect
Should pipe M2 source electrode ground connection, the grid of the second field-effect tube M2 connect with the grid of the third field-effect tube M3 and with institute
It states local oscillator LO and connects the local oscillator LO and local oscillated signal Ft is input to the second field-effect tube M2's
The grid of grid and the third field-effect tube M3；The drain electrode of the second field-effect tube M2 is with the third field-effect tube M3's
Drain electrode is connected and is connect with the input terminal of the hex inverter, the source electrode of the third field-effect tube M3 and described first effect
Should pipe M1 drain electrode connection.The hex inverter include the 4th field-effect tube M4 and the 5th field-effect tube M5, described 5th
The source electrode of effect pipe M5 is grounded, the grid of the 4th field-effect tube M4 connect with the grid of the 5th field-effect tube M5 and with
The drain electrode of the second field-effect tube M2 connects, the leakage of the drain electrode and the 5th field-effect tube M5 of the 4th field-effect tube M4
Pole connects and is connect with the input terminal of the low-pass filter LPF, source electrode and the external power supply VDD of the 4th field-effect tube M4
Connection
In addition, as a preferred embodiment of the present invention, the low-pass filter LPF is by resistance R1 and capacitance C1 groups
At specific connection relation is as shown in figure 4, not described in detail herein.
The course of work of phase-locked loop circuit of the present invention is described with reference to Fig. 4-6：
As described above, the phase-locked loop circuit of the present invention is operable with general mode and low spurious pattern.It is general when working in
When logical pattern, way selectors MUX selections are connect with the low-pass filter LPF so that phase discriminator PD is directly and low-pass filtering
Device LPF is connected, at this point, the working characteristics of phase-locked loop circuit is identical as existing phase-locked loop circuit shown in Fig. 1, will not consume additional
Power consumption, it is not described in detail herein.
When the phase-locked loop circuit works in low spurious pattern, way selectors MUX selections turn with the pulsewidth/voltage
Parallel operation PVC connections so that phase discriminator PD is connected with pulsewidth/electric pressure converter PVC.Under low spurious pattern, phase-locked loop circuit
Output signal Fout have lower output factors, to obtain better output frequency stability；Specifically,
When pulse signal V1X inputs the pulsewidth/electric pressure converter PVC, first switch S1 can be in the effect of high level
Lower closure, the first capacitance Cs1 are connected with current source IS, and current source IS charges to the first capacitance Cs1, and its charging time
The voltage change of pulsewidth △ Φ 1 equal to input pulse signal V1X, the first capacitance Cs1 are △ Φ 1*IS.As pulse signal V1X
When becoming low level from high level, failing edge detection unit will produce a high level pulse signal VA1, to be closed second switch
The charge of S2, the first capacitance Cs1 will flow to the second capacitance Cs2.In addition the rising edge of high level pulse VA1 can trigger rising edge
Detection unit so that second generates a high level pulse VA2 with door A2, to be closed third switch S3 so that the first capacitance Cs1
The charge of upper storage is reset, and voltage becomes zero potential.After input pulse signal V1X is by several periods, the second electricity
A stationary value can be reached by holding the charge stored on Cs2, to make its both end voltage reach a stationary value, and as the arteries and veins
The output signal V2X of width/electric pressure converter PVC.The size of V2X meets following relationship：
V2X=ΔΦs 1*IS/Cs1
From the above equation, we can see that the size of V2X is directly proportional to the pulsewidth △ Φ 1 of input pulse signal V1X.
The output signal V2X of pulsewidth/electric pressure converter PVC inputs the input terminal of the voltage/pulse width conversion device VPC,
In voltage/pulse width conversion device VPC the first field-effect tube M1 be used as variable resistance, resistance value size by signal V2X voltage swing
It is determined, to modulate the rising edge pace of change of the 5th phase inverter output node Vm signals.The voltage of signal V2X is bigger, the
The resistance of one field-effect tube M1 is bigger, and the rising edge of Vm is slower.The voltage of signal V2X is smaller, the electricity of the first field-effect tube M1
Hinder smaller, the rising edge of Vm is more precipitous.Hex inverter is being according to the steep of the output signal Vm rising edges of the 5th phase inverter
High and steep degree, it is Ft and the pulse signal V3X outputs with certain pulsewidth to generate frequency, and it is wider that more slow rising edge generates pulsewidth
Pulse, more precipitous rising edge generates the narrower pulse of pulsewidth, and the pulsewidth △ Φ 2 of pulse signal V3X meet following relationship
Formula：
ΔΦ 2=V2X* λ (λ is the constant that the size and characteristic of M5 are codetermined by M1, M2, M3, M4)
The input signal Fe of 5th phase inverter is provided by local oscillator LO.Local oscillator LO only needs to provide a frequency
Square-wave signal (Ft be the frequency of the square-wave signal, frequency multiplication coefficient M=Ft/Fref) of the rate much larger than Fref, and not
It needs to consider its precision and noise objective, therefore smaller cost can be used to realize.
Pulsewidth/electric pressure converter PVC and voltage/pulse width conversion device VPC are concatenated together to the voltage arteries and veins to form the present invention
Rush multiplication modules.Under low spurious operating mode, the frequency of the pulse signal V3X corresponding to multiplication modules output node is Ft=
M*Fref, pulsewidth ΔΦ 2=ΔΦ 1*IS* λ/Cs1=α * ΔΦs 1 (α=IS* λ/Cs1).Suitable α values are set, can be made
Pulse signal V1X is the scaled down of the pulse signal at V1, to not change its waveform spy while doubling its frequency
Sign.
In conclusion the phase-locked loop circuit of the present invention under low spurious operating mode, passes through phase discriminator PD outputs of doubling
The frequency of pulse signal reduces the high fdrequency component of voltage controlled oscillator VCO input terminal control signal, reduces voltage controlled oscillator VCO
The stray power of output signal Fout, to reduce the reference spur of phase-locked loop circuit output signal Fout.
Above in association with most preferred embodiment, invention has been described, but the invention is not limited in implementations disclosed above
Example, and modification, equivalent combinations that various essence according to the present invention carry out should be covered.
Claims (10)
1. a kind of phase-locked loop circuit, including phase discriminator, low-pass filter and voltage controlled oscillator, external reference clock inputs the mirror
One input terminal of phase device, the output end of the phase discriminator are connect with the input terminal of the low-pass filter, the low-pass filter
Output end connect with the input terminal of the voltage controlled oscillator, the output end of the voltage controlled oscillator is another with the phase discriminator
Input terminal connects and exports the output signal of the phase-locked loop circuit；It is characterized in that, further including way selectors, voltage/arteries and veins
Wide converter, pulsewidth/electric pressure converter and local oscillator, the output of the input terminal of the way selectors and the phase discriminator
End connection, the output ends of the way selectors selectively with the input terminal of the low-pass filter or the pulsewidth/voltage
The input terminal of converter connects, and the output end of the pulsewidth/electric pressure converter and the input terminal of the voltage/pulse width conversion device connect
It connects, and the local oscillator exports local oscillated signal to the voltage/pulse width conversion device, the voltage/pulse width conversion device
Output end connect with the input terminal of the low-pass filter.
2. phase-locked loop circuit as described in claim 1, which is characterized in that the phase-locked loop circuit be operable with general mode with
Low spurious pattern, when the phase-locked loop circuit works in general mode, the output end of the way selectors and the low pass
The input terminal of filter connects, when the phase-locked loop circuit works in low spurious pattern, the output end of the way selectors
It is connect with the input terminal of the pulsewidth/electric pressure converter.
3. phase-locked loop circuit as claimed in claim 2, which is characterized in that the pulsewidth/electric pressure converter includes current source,
One switch, second switch, third switch, the first capacitance, the second capacitance, failing edge detection unit and rising edge detection unit；Institute
The output end for stating way selectors is selectively connect with the input terminal of the failing edge detection unit, and the failing edge detection is single
The output end of member is connect with the input terminal of the rising edge detection unit；Described current source one end is connect with external power supply, another
One end is connect with one end of the first switch, and the other end of the first switch is connect with one end of first capacitance, institute
State the other end ground connection of the first capacitance；One end of the second switch is connect with one end that the third switchs, and described second opens
The other end of pass connect with one end of second capacitance and forms the output end of the pulsewidth/electric pressure converter；Described second
The other end of capacitance, the other end of third switch are grounded.
4. phase-locked loop circuit as claimed in claim 3, which is characterized in that the pulse signal control of the way selectors output
The pulse signal of the ON/OFF of the first switch, the failing edge detection unit output controls the ON/OFF of the second switch,
The pulse signal of the rising edge detection unit output controls the ON/OFF of the third switch.
5. phase-locked loop circuit as claimed in claim 4, which is characterized in that the first switch, second switch and third switch
It controls when signal is high level and is closed at it.
6. phase-locked loop circuit as claimed in claim 3, which is characterized in that the failing edge detection unit includes the first reverse phase
Device, the second phase inverter, third phase inverter and first and door, the input terminal of first phase inverter and the second phase inverter with it is described
The output end of way selectors connects, and the output end of first phase inverter is connect with described first with an input terminal of door；Institute
The output end for stating the second phase inverter is connect with the input terminal of the third phase inverter, the output end of the third phase inverter with it is described
First connect with another input terminal of door；Described first connects with the output end of door and the input terminal of the rising edge detection unit
It connects, and exports the ON/OFF that a pulse signal controls the second switch.
7. phase-locked loop circuit as claimed in claim 6, which is characterized in that the rising edge detection unit includes the 4th phase inverter
And second and door, described first with the output end of door respectively with the input terminal of the 4th phase inverter, described second and the one of door
Input terminal connects, and the output end of the 4th phase inverter connect with described second with another input terminal of door, and described second and door
Output end export the ON/OFF that a pulse signal controls third switch.
8. phase-locked loop circuit as claimed in claim 7, which is characterized in that the voltage/pulse width conversion device includes first effect
The source electrode of Ying Guan, the 5th phase inverter and hex inverter, first field-effect tube is connect with external power supply, first effect
Should the grid of pipe connect with the output end of the pulsewidth/electric pressure converter, the drain electrode of first field-effect tube and the described 5th
The control terminal of phase inverter connects, and the input terminal of the 5th phase inverter is connect with the local oscillator, the 5th phase inverter
Output end connect with the input terminal of the hex inverter, the output end of the hex inverter and the low-pass filter
Input terminal connects.
9. phase-locked loop circuit as claimed in claim 8, which is characterized in that the 5th phase inverter include the second field-effect tube with
Third field-effect tube, the source electrode ground connection of second field-effect tube, the grid of second field-effect tube are imitated with the third field
Should the grid of pipe connect and connect with the local oscillator, the drain electrode of second field-effect tube and the third field-effect tube
Drain electrode connect and connect with the input terminal of the hex inverter, the source electrode of the third field-effect tube with described first imitate
Should pipe drain electrode connection.
10. phase-locked loop circuit as claimed in claim 9, which is characterized in that the hex inverter includes the 4th field-effect tube
With the 5th field-effect tube, the source electrode of the 5th field-effect tube is grounded, the grid of the 4th field-effect tube with described 5th
The grid of effect pipe, which connects, simultaneously connect with the drain electrode of second field-effect tube, the drain electrode of the 4th field-effect tube and described the
The drain electrodes of five field-effect tube, which connects, simultaneously connect with the input terminal of the low-pass filter, the source electrode of the 4th field-effect tube with outside
Portion's power supply connection.
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| CN201610536439.5A CN106209082B (en) | 2016-07-08 | 2016-07-08 | Phase-locked loop circuit |
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| CN201610536439.5A CN106209082B (en) | 2016-07-08 | 2016-07-08 | Phase-locked loop circuit |
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| CN107872414B (en) * | 2017-12-01 | 2020-07-14 | 珠海亿智电子科技有限公司 | Novel phase discriminator for BPSK signal demodulation |
| CN117439692A (en) * | 2023-12-21 | 2024-01-23 | 安康鸿天科技股份有限公司 | Clock synchronization device for private network deployment IMS system |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101719767A (en) * | 2009-11-17 | 2010-06-02 | 中国航天科技集团公司第九研究院第七七一研究所 | Phase-locked loop with quick response |
| CN102006059A (en) * | 2010-09-21 | 2011-04-06 | 湖北众友科技实业股份有限公司 | Sigma delta controlled phase locked loop and calibration circuit and calibration method thereof |
| CN103441759A (en) * | 2013-08-28 | 2013-12-11 | 电子科技大学 | Phase frequency detector |
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| AU2010343096A1 (en) * | 2009-12-28 | 2012-08-16 | Flyback Energy, Inc. | Controllable universal power supply with reactive power management |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101719767A (en) * | 2009-11-17 | 2010-06-02 | 中国航天科技集团公司第九研究院第七七一研究所 | Phase-locked loop with quick response |
| CN102006059A (en) * | 2010-09-21 | 2011-04-06 | 湖北众友科技实业股份有限公司 | Sigma delta controlled phase locked loop and calibration circuit and calibration method thereof |
| CN103441759A (en) * | 2013-08-28 | 2013-12-11 | 电子科技大学 | Phase frequency detector |
Non-Patent Citations (1)
| Title |
|---|
| 低杂散锁相环中鉴频鉴相器与电荷泵的设计;李森，江金光;《微电子学》;20160430;第46卷(第2期);第228页-第232页 * |
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