CN101242182A - Phase locked ring with phase rotary frequency spreading - Google Patents
Phase locked ring with phase rotary frequency spreading Download PDFInfo
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- CN101242182A CN101242182A CNA2007100035354A CN200710003535A CN101242182A CN 101242182 A CN101242182 A CN 101242182A CN A2007100035354 A CNA2007100035354 A CN A2007100035354A CN 200710003535 A CN200710003535 A CN 200710003535A CN 101242182 A CN101242182 A CN 101242182A
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Abstract
The invention discloses a phase lock loop with phase rotating spread spectrum. A phase discriminator receives a reference time sequence signal and a feedback time sequence signal to generate a false signal; a charge bump converts the false signal to a current signal; a filter converts the current signal to a voltage signal; a voltage controlled oscillator generates N time sequence signals with the same frequency according to the voltage signal; wherein, the phases of the N time sequence signals are theta<0>, theta<1>, theta<2>,..., theta<N-1>, theta<j> exceeding theta<j+1> by 2 pi/N; j=0, 1, 2,..., N-2; a selector selects a time sequence signal from the N time sequence signals according to a preset sequence to generate a target time sequence signal and regulate the frequency of the target time sequence signal finely, so as to spread spectrum for the target time sequence signal.
Description
Technical field
The present invention relates to a kind of phase-locked loop, be specifically related to a kind of phase-locked loop with phase place rotation spread spectrum.
Background technology
Along with the quick progress of electronic science and technology, diversified application can be provided by various electronic product, because the application of various electronic products is increasingly sophisticated, thus need various sequential, so that different application to be provided.In order to satisfy the demand of saving cost and different sequential being provided, phase-locked loop becomes best selection.Fig. 1 is the structure chart of prior art phase-locked loop 100, as shown in Figure 1, this phase-locked loop by phase discriminator 110, charge pump (CP, Charge Pump) 120, low pass filter 130, voltage controlled oscillator 140 (VCO, Voltage Control Oscillator), and frequency divider 150 form.It is the input signal of Fin that phase-locked loop 100 receives a frequency, and to produce frequency be the output signal of Fout, and wherein, Fout=Y * Fin, Y can be integer or mark.Because output signal frequency Fout much larger than the frequency Fin of input signal, so often can't detect by electromagnetic radiation, also interferes with other electronic building brick simultaneously easily.
For addressing the above problem, United States Patent (USP) is announced (title: Spread Spectrumat Phase Lock Loop Feedback Path) provide a method with the pll output signal spread spectrum No. 6377646, this method is utilized the correction value of a read-only memory (ROM) record frequency divider, to change the divisor of frequency divider, and on existing frequency divider, utilize phase place to engulf (phase swallow) method, so that pll output signal is carried out spread spectrum.Yet this kind method is to utilize the divisor that changes frequency divider to change output frequency basically, equal the phase-locked loop of incoming frequency for output frequency, its spectrum spreading method is just infeasible, perhaps when the divisor of frequency divider is too small, the rub-out signal that its phase discriminator is exported can be very big, and then influence the spread spectrum effect.Hence one can see that, and existing phase-locked loop still has the space of improvement.
Summary of the invention
In view of this, the invention provides a kind of phase-locked loop, reduce electromagnetic radiation, and avoid interference other electronic building brick with phase place rotation spread spectrum.
For achieving the above object, technical scheme of the present invention is achieved in that
A kind of phase-locked loop with phase place rotation spread spectrum comprises a phase discriminator, a charge pump, a filter, a voltage controlled oscillator and a selector.This phase discriminator receives one with reference to a clock signal and a feedback clock signal, to produce a rub-out signal; This charge pump is connected to this phase discriminator, so that this rub-out signal is converted to a current signal; This filter is connected to this charge pump, converts this current signal to a voltage signal; This voltage controlled oscillator is connected to this filter, and in order to produce N the clock signal with same frequency according to this voltage signal, wherein, the phase place of this N clock signal is θ in regular turn
0, θ
1, θ
2..., θ
N-1, θ
jThan θ
J+1In advance
, j=0,1,2 ..., N-2; This selector is connected to this voltage controlled oscillator, chooses one of them clock signal with foundation one predesigned order by this N clock signal, and produces a target clock signal.
Description of drawings
Fig. 1 is the structure chart of prior art phase-locked loop.
Fig. 2 has the structure chart of the phase-locked loop of phase place rotation spread spectrum for the present invention.
Fig. 3 is the circuit diagram of passive low ventilating filter of the present invention.
Fig. 4 is the circuit diagram of active low-pass filter of the present invention.
Fig. 5 is the schematic diagram of voltage controlled oscillator of the present invention and selector.
Fig. 6 does not carry out the schematic diagram of spread spectrum for the present invention.
Fig. 7 carries out the upwards schematic diagram of spread spectrum for the present invention.
Fig. 8 carries out the schematic diagram of downward spread spectrum for the present invention.
Embodiment
The present invention is described in detail below in conjunction with drawings and the specific embodiments.
Fig. 2 is the structure chart that the present invention has the phase-locked loop 200 of phase place rotation spread spectrum, comprises a phase discriminator 210, a charge pump 220, a filter 230, a voltage controlled oscillator 240, a selector 250 and a frequency divider 260.
This phase discriminator 210 is used to receive one with reference to a clock signal Vref and a feedback clock signal Vfbk, and to produce a rub-out signal, this rub-out signal is a phase error signal.
This charge pump 220 is connected to this phase discriminator 210, so that this rub-out signal is converted to a current signal.
This filter 230 is connected to this charge pump 220, converts this current signal to a voltage signal, and wherein, this filter 230 is a low pass filter.
This low pass filter can be a passive filter (passive filter).Fig. 3 is the circuit diagram of this passive low ventilating filter, and it can be a third-order low-pass filter, is made up of one first resistance R 1, first capacitor C 1, second capacitor C 2, second resistance R 2 and the 3rd capacitor C 3.
One end of this first resistance R 1 is connected to this charge pump 220, and the other end is connected to this first capacitor C 1, and the other end of this first capacitor C 1 is connected to an electronegative potential.First end of this second capacitor C 2 is connected to this charge pump 220, and its other end is connected to an electronegative potential.First end of this second resistance R 2 is connected to this charge pump 220, and the other end that its other end is connected to the 3rd capacitor C 3 and this voltage controlled oscillator 240, the three capacitor C 3 is connected to an electronegative potential.
This first resistance R 1 and this first capacitor C 1 provide one first limit and a zero point (zero).This second capacitor C 2 provides one second limit.This second resistance R 2 and the 3rd capacitor C 3 provide one the 3rd limit.
This filter 230 also can be an active low-pass filter (active filter).Fig. 4 is the circuit diagram of this active low-pass filter, and it is a second-order low-pass filter, and it is made up of one the 3rd resistance R 3, the 4th capacitor C 4, the 5th capacitor C 5 and an operational amplifier OP1.
First end of the 3rd resistance R 3 is connected to the inverting input (-) of this charge pump 220 and this operational amplifier OP1, the other end that its other end is connected to the 4th capacitor C 4, the four capacitor C 4 is connected to the noninverting output (+) of this operational amplifier OP1.First end of the 5th capacitor C 5 is connected to the inverting input (-) of this charge pump 220 and this operational amplifier OP1, and its other end is connected to the noninverting output (+) of this operational amplifier OP1.The non-inverting input (+) of this operational amplifier OP1 is connected to an electronegative potential.
The active low-pass filter of Fig. 4 uses operational amplifier OP1, can increase the amplitude of oscillation scope (voltage swing) of output voltage, the also easier adjustment limit of while and the position at zero point, and then obtain better frequency response.
Fig. 5 is the schematic diagram of voltage controlled oscillator 240 and selector 250.This voltage controlled oscillator 240 is connected to this filter 230, to produce N the clock signal with same frequency according to this voltage signal.This voltage controlled oscillator 240 is preferably the oscillator of ring oscillation (ring oscillation) pattern, can provide N phase place to be θ in regular turn
0, θ
1, θ
2..., θ
N-1Clock signal, wherein, θ
jThan θ
L+1In advance
J=0,1,2 ..., N-2.
This selector 250 is connected to this voltage controlled oscillator 240, chooses one of them clock signal with foundation one predefined order by this N clock signal, and then produces a target clock signal.This selector 250 is formed a MUX 252 by phase place rotation and multichannel control logic 251 and a N.
This frequency divider 260 is connected to this selector 250, so that this target clock signal frequency division is produced this feedback clock signal Vfbk.This frequency divider 260 is that this target clock signal Vtar is carried out integral frequency divisioil and produces this feedback clock signal Vfbk.In other embodiments, this frequency divider 260 also can carry out fraction division and produce this feedback clock signal Vfbk this target clock signal Vtar.
Fig. 6 is the schematic diagram that the present invention does not carry out spread spectrum.It is θ that MUX 252 is selected phase place
0Signal CLK0 as this target clock signal Vtar.This target clock signal Vtar carries out frequency division and produces this feedback clock signal Vfbk (divisor in this example=1) via this frequency divider 260.Owing to do not carry out spread spectrum, after phase place was pinned, this feedback clock signal Vfbk and this phase difference with reference to clock signal Vref were 0.
Fig. 7 is that the present invention carries out the upwards schematic diagram of spread spectrum (up spreading).When the phase-locked loop that has a phase place rotation spread spectrum as the present invention was carried out upwards spread spectrum, this MUX 252 is chosen in regular turn had phase theta
0, θ
1, θ
2..., θ
N-1Corresponding clock signal CLK0, CLK1 ..., CLKN-1, with as this target clock signal Vtar.This target clock signal Vtar carries out frequency division (divisor in this example=1) and produces this feedback clock signal Vfbk via this frequency divider 260.As shown in Figure 7, because the phase place of this feedback clock signal Vfbk continues to fall behind this phase place with reference to clock signal Vref, so this phase discriminator 210 can continue to produce a phase error signal, and then improves the frequency of this target clock signal Vtar, reaches the upwards purpose of spread spectrum.
Fig. 8 is the schematic diagram that the present invention carries out downward spread spectrum (down spreading).When the phase-locked loop that has a phase place rotation spread spectrum as the present invention was carried out downward spread spectrum, this MUX 252 is chosen in regular turn had phase theta
0, θ
N-1, θ
N-2..., θ
2, θ
1Corresponding clock signal CLK0, CLKN-1, CLKN-2 ..., CLK1, as this target clock signal Vtar.This target clock signal Vtar carries out frequency division (divisor in this example=1) and produces this feedback clock signal Vfbk via this frequency divider 260.As shown in Figure 8, because the phase place of this feedback clock signal Vfbk continues in advance should be with reference to the phase place of clock signal Vref, so this phase discriminator 210 can continue to produce a phase error signal, and then reduces the frequency of this target clock signal Vtar, reaches the purpose of downward spread spectrum.
Similarly, when the frequency with this target clock signal Vtar was center and spread spectrum, this selector was chosen θ in regular turn
0, θ
1, θ
2..., θ
N-1, θ
0, θ
N-1, θ
N-2..., θ
2, θ
1Corresponding clock signal is as this target clock signal.
In comparison, United States Patent (USP) is announced the divisor of No. 6377646 change frequency divider, and utilizes phase place to engulf (phase swallow) method on frequency divider, so that pll output signal is carried out spread spectrum.Yet this kind mode is the divisor that utilize to change frequency divider changing output frequency basically, need equal the phase-locked loop of incoming frequency for output frequency, and its spectrum spreading method is just infeasible.Perhaps when the divisor of frequency divider is too small, the rub-out signal that its phase discriminator is exported can be very big and influences the spread spectrum effect.And the present invention only need increase phase place rotation and multichannel control logic 251 and N newly to a MUX 252, can overcome described restriction and reach identical spread spectrum effect.Simultaneously, because its spread spectrum do not need to reach by the divisor that changes frequency divider, thus equal the phase-locked loop of incoming frequency for output frequency, or too small because of the divisor of frequency divider, and the spread spectrum poor effect that causes all can be avoided.
As shown in the above description, the mode that the present invention utilizes phase place rotation and multichannel control logic 251 and N that one MUX 252 is arranged in pairs or groups mutually selects N phase place of this voltage controlled oscillator output to be θ in regular turn according to a predefined order
0, θ
1, θ
2..., θ
N-1Clock signal, can reach the purpose of spread spectrum.Simultaneously can reduce the use amount of assembly, and reach the purpose that reduces cost.
The foregoing description only is to give an example for convenience of description, and interest field of the presently claimed invention should be as the criterion so that claim is described, but not only limits to the foregoing description.
Claims (15)
1. the phase-locked loop with phase place rotation spread spectrum is characterized in that this phase-locked loop comprises phase discriminator, charge pump, filter, voltage controlled oscillator and selector,
Described phase discriminator is used to receive one with reference to a clock signal and a feedback clock signal, and then produces a rub-out signal;
One charge pump is connected to this phase discriminator, is used for this rub-out signal is converted to a current signal;
One filter is connected to this charge pump, is used for this current signal is changed into a voltage signal;
One voltage controlled oscillator is connected to this filter, is used for producing N clock signal according to this voltage signal, and this N clock signal has same frequency, and wherein, the phase place of this N clock signal is θ in regular turn
0, θ
1, θ
2..., θ
N-1, θ
jThan θ
J+1In advance
J=0,1,2 ..., N-2; And
One selector is connected to this voltage controlled oscillator, is used for choosing one of them described clock signal according to a predefined order by this N clock signal, and then produces a target clock signal.
2. phase-locked loop as claimed in claim 1 is characterized in that, this phase-locked loop further comprises:
One frequency divider is connected to this selector, is used for this target clock signal frequency division, and then produces this feedback clock signal.
3. phase-locked loop as claimed in claim 1 is characterized in that described voltage controlled oscillator is the oscillator of ring oscillation pattern, is used to provide this N phase place to be θ in regular turn
0, θ
1, θ
2..., θ
N-1Clock signal.
4. phase-locked loop as claimed in claim 1 is characterized in that, when making progress spread spectrum, this selector is chosen θ in regular turn
0, θ
1, θ
2..., θ
N-1Clock signal, as this target clock signal.
5. phase-locked loop as claimed in claim 1 is characterized in that, when downward spread spectrum, this selector is chosen θ in regular turn
0, θ
N-1, θ
N-2..., θ
2, θ
1Clock signal, as this target clock signal.
6. phase-locked loop as claimed in claim 1 is characterized in that, when the frequency with this target clock signal is center when carrying out spread spectrum, this selector is chosen θ in regular turn
0, θ
1, θ
2..., θ
N-1, θ
0, θ
N-1, θ
N-2..., θ
2, θ
1Clock signal, as this target clock signal.
7. phase-locked loop as claimed in claim 2 is characterized in that, this rub-out signal is a phase error signal.
8. phase-locked loop as claimed in claim 2 is characterized in that, this filter is a low pass filter.
9. phase-locked loop as claimed in claim 8 is characterized in that, this low pass filter is a passive filter or an active low-pass filter.
10. phase-locked loop as claimed in claim 9 is characterized in that, this passive low ventilating filter is a third-order low-pass filter.
11. phase-locked loop as claimed in claim 10, it is characterized in that, this third-order low-pass filter is by one first resistance, one first electric capacity, one second electric capacity, one second resistance and one the 3rd electric capacity are formed, first end of this first resistance is connected to this charge pump, second end of this first resistance is connected to first end of this first electric capacity, second end of this first electric capacity is connected to an electronegative potential, first end of this second electric capacity is connected to this charge pump, second end of this second electric capacity is connected to described electronegative potential, first end of this second resistance is connected to this charge pump, second end of this second resistance is connected to first end and this voltage controlled oscillator of the 3rd electric capacity, and second end of the 3rd electric capacity is connected to described electronegative potential.
12. phase-locked loop as claimed in claim 9 is characterized in that, this active low-pass filter is a second-order low-pass filter.
13. phase-locked loop as claimed in claim 12, it is characterized in that, this second-order low-pass filter is by one the 3rd resistance, one the 4th electric capacity, one the 5th electric capacity and an operational amplifier are formed, first end of the 3rd resistance is connected to the inverting input of this charge pump and this operational amplifier, second end of the 3rd resistance is connected to first end of the 4th electric capacity, second end of the 4th electric capacity is connected to a noninverting output of this operational amplifier, first end of the 5th electric capacity is connected to an inverting input of this charge pump and this operational amplifier, second end of the 5th electric capacity is connected to this noninverting output of this operational amplifier, and a non-inverting input of this operational amplifier is connected to an electronegative potential.
14. phase-locked loop as claimed in claim 2 is characterized in that, this frequency divider is that this target clock signal is carried out integral frequency divisioil or fraction division, and then produces this feedback clock signal.
15. phase-locked loop as claimed in claim 1 is characterized in that, this selector is that a N is to a MUX.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2007100035354A CN101242182A (en) | 2007-02-06 | 2007-02-06 | Phase locked ring with phase rotary frequency spreading |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2007100035354A CN101242182A (en) | 2007-02-06 | 2007-02-06 | Phase locked ring with phase rotary frequency spreading |
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| Publication Number | Publication Date |
|---|---|
| CN101242182A true CN101242182A (en) | 2008-08-13 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2007100035354A Pending CN101242182A (en) | 2007-02-06 | 2007-02-06 | Phase locked ring with phase rotary frequency spreading |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101436086B (en) * | 2008-11-20 | 2010-06-16 | 四川和芯微电子股份有限公司 | System for initially generating stabilized in-chip clock |
| CN101854162A (en) * | 2009-03-13 | 2010-10-06 | 瑞昱半导体股份有限公司 | Method and device for avoiding pulse due to clock switch in phase interpolation circuit |
| CN102361454A (en) * | 2011-10-18 | 2012-02-22 | 四川和芯微电子股份有限公司 | System and method for detecting spread spectrum clock signals |
| CN103959654A (en) * | 2011-11-28 | 2014-07-30 | 高通股份有限公司 | Dividing a frequency by 1.5 to produce a quadrature signal |
| CN104158553A (en) * | 2014-08-28 | 2014-11-19 | 上海航天电子通讯设备研究所 | Hybrid loop of phase-locked receiver |
| CN108628388A (en) * | 2017-03-17 | 2018-10-09 | 安立股份有限公司 | The production method of frequency-spreading clock generator, pattern generator and the two |
| CN117118433A (en) * | 2023-10-25 | 2023-11-24 | 成都九洲迪飞科技有限责任公司 | Novel high-order phase-locked loop system, loop filter circuit and implementation method |
-
2007
- 2007-02-06 CN CNA2007100035354A patent/CN101242182A/en active Pending
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101436086B (en) * | 2008-11-20 | 2010-06-16 | 四川和芯微电子股份有限公司 | System for initially generating stabilized in-chip clock |
| CN101854162A (en) * | 2009-03-13 | 2010-10-06 | 瑞昱半导体股份有限公司 | Method and device for avoiding pulse due to clock switch in phase interpolation circuit |
| CN102361454A (en) * | 2011-10-18 | 2012-02-22 | 四川和芯微电子股份有限公司 | System and method for detecting spread spectrum clock signals |
| CN102361454B (en) * | 2011-10-18 | 2013-04-24 | 四川和芯微电子股份有限公司 | System and method for detecting spread spectrum clock signals |
| CN103959654A (en) * | 2011-11-28 | 2014-07-30 | 高通股份有限公司 | Dividing a frequency by 1.5 to produce a quadrature signal |
| CN103959654B (en) * | 2011-11-28 | 2016-08-24 | 高通股份有限公司 | For frequency being carried out 1.5 frequency dividings with the method and apparatus producing orthogonal signalling |
| CN104158553A (en) * | 2014-08-28 | 2014-11-19 | 上海航天电子通讯设备研究所 | Hybrid loop of phase-locked receiver |
| CN104158553B (en) * | 2014-08-28 | 2017-03-08 | 上海航天电子通讯设备研究所 | A kind of phase-locked receive mixing loop |
| CN108628388A (en) * | 2017-03-17 | 2018-10-09 | 安立股份有限公司 | The production method of frequency-spreading clock generator, pattern generator and the two |
| CN108628388B (en) * | 2017-03-17 | 2021-04-20 | 安立股份有限公司 | Spread spectrum clock generator, pattern generator and generating method thereof |
| CN117118433A (en) * | 2023-10-25 | 2023-11-24 | 成都九洲迪飞科技有限责任公司 | Novel high-order phase-locked loop system, loop filter circuit and implementation method |
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