WO2009083501A2

WO2009083501A2 - A phase locked loop

Info

Publication number: WO2009083501A2
Application number: PCT/EP2008/068038
Authority: WO
Inventors: Paavo Sakari VÄÄNÄNEN; Niko Juhani Mikkola; Petri Antero HEILÖ; Janne Olavi Peltonen; Sami Tapani Vilhonen
Original assignee: Nokia Corporation
Priority date: 2007-12-28
Filing date: 2008-12-19
Publication date: 2009-07-09
Also published as: GB0725318D0; WO2009083501A3

Abstract

A phase locked loop circuit comprising; a digitally controlled oscillator configured to receive a first signal and output a second signal dependent on the first signal and at least one mapping function; a phase comparator configured to receive the second signal and output a third signal dependent on the second signal, a reference signal and at least one phase comparator parameter; a loop filter configured to receive the third signal and generate the first signal dependent on the third signal and at least one filter parameter; and a controller configured to control at least one of: the at least one mapping function; the at least one phase comparator parameter; and the at least one filter parameter.

Description

A PHASE LOCKED LOOP

Field of the Invention

The present invention is related to a phase locked loop, and more particularly but not exclusively a digitally controlled local oscillator frequency synthesizer phase locked loop.

Background

One of the key building blocks found in electronic equipment with a transmitter, receiver or transceiver component is the frequency synthesizer. The frequency synthesizer outputs an oscillator output which may be used for signal generation, signal mixing, and modulation.

Signal mixing may be used for example in a receiver to down convert a received radio frequency signal to a baseband frequency signal in order that the modulating/information signal, in the received signal may be separated from the carrier signa!. Similarly signal mixing may be used in a transmitter to up convert the information/modulating signal to the carrier frequency.

In a transmitter the modulating signal is formed in the base band frequency (i.e. around zero frequency). For example a phase of certain selected pulse form is modulated depending on the information that is to be transmitted. In a communication system using a radio channel to transmit the information, the base band signal is then up-converted to a radio frequency of the radio channel by mixing it with a local oscillator (LO) signal. In a direct conversion transmitter the mixing is carried out in one stage and the base band signal is therefore multiplied with a local oscillator signai which has a frequency determined by the radio channel used in that particular communication system. In a frequency domain representation this can be described as the base band signal being transferred from a zero frequency to the local oscillator frequency which in the case of the direct conversion transmitter is in the middle of the transmitted channel. In a receiver the local oscillator is used to convert the received signal down in frequency from the received signal radio frequency to the base band (zero frequency) or intermediate frequency. In case of a direct conversion receiver the received signal is mixed to the zero frequency in a single stage. In this way the carrier component (i.e. the frequency component in the LO frequency band) of the received signal is removed and the synchronization to the modulated base band signal is possible

Frequency synthesizers and loca! oscillators have been created using crystal oscillators to provide a reference frequency for a phase locked loops (PLL). The phase locked loop is typically used to generate the loca! oscillator signal using a voltage controlled oscillator (VCO) which has a analogue input - in other words an analogue phase difference signal representing the phase difference between the reference oscillator and the VCO is converted to a frequency output at the VCO.

An ideal wide-band controllable frequency synthesizer is one in which it is possible to produce a wide adjustable frequency range output. In other words a controllable output able to provide both small and large adjustments in output frequency. The output frequency range of the frequency synthesizer needs to cover the requirements of the system that it is used for. In a typical communication system this means that the output of the frequency synthesizer needs to cover all the LO frequencies required in the particular transmitter/receiver/transceiver part. It is common that a transceiver may be designed so that it can be used for multiple communications systems. The synthesizer is required to be able to be tuned with fine enough frequency resolution in order to meet the channel raster specifications of the communication systems that the transceiver is required to operate in.

Furthermore the output must be stable, and should not drift from the original frequency because of time or environmental changes. The integrated phase-locked loop (in other words a phase-locked loop implemented on an integrated circuit) is arranged with a voltage controlled oscillator (VCO) connected to a frequency divider. The frequency divider produces an output frequency of the VCO signal divided by the frequency division ratio (M). The frequency divider output is input to a phase detector which compared the frequency divider output phase with the phase of a reference clock (F_ref). The phase detector outputs a current pulse whose width is relative to the phase difference between the edges of the reference frequency signal and the frequency divider output.

A loop filter network, typically a passive resistor-capacitor network, can be considered to be a transimpedance filter, in other words the filter receives the current pulse and outputs an integrated or filtered voltage output relative to the measured phase error, filtering out the high frequency components. This voltage is then input to the voltage controlled oscillator (VCO) which therefore determines the output of the voltage controlled oscillator (VCO).

Typically the VCO control input is considered to be high impedance

The PLL settles to a value which forces the voltage controlled oscillator (VCO) to oscillate on a frequency defined by M x F_ref.

It is known that fractional division ratios may be obtained by using a delta- sigma modulator connected to the frequency divider and modulating the value of M in such a manner that the fractional average division ratio is obtained.

Analogue phase-locked loop (PLL) circuits have problems when impiemented in silicon. The capacitors used in the loop filter require significant integrated circuit area to implement (or external components are required which increase a circuit board area). Particularly where the division ratio M is small and the loop filter impedance level is required to be relatively low in order to produce suitable values for the phase detector output current and the voltage control oscillator gain the capacitance required produces strain on integrated circuit design for valuable chip area. Furthermore process variations in integrated circuit production affects the phase locked loop (PLL) oscillator to an extent that further integrated circuitry is required to be able to fine-tune the loop filter to produce a consistent result throughout the production run. This additional circuitry increases the complexity of the system and furthermore testing and fine tuning of the circuit is required.

Partially digitally implemented PLL circuits have been proposed. Golten describes in the paper "Analog-Input Digital Phase Locked Loops for Precise Frequency and Phase Modulation", IEEE transactions on Circuits and Systems - II; Analog and Digital Signal Processing, Volume 42, No 10, October 1995, how the analogue loop filter can be replaced with a discrete- time loop filter, the phase detector replaced by a sampled phase detector, and the voltage control oscillator replaced by a digitally controlled oscillator (DCO).

Practical implementations of such systems may be seen from US published patents US-6734741 and US-7006589. However, such systems still have the following problems.

The main disadvantage of the above implementations is that the implementation requires a high frequency clock for the DCO modulation interface.

The high frequency clock is required to be divided from the DCO output which then is fed back to a sϊgma-delta modulator clock. This creates a secondary feedback loop for the DCO noise which is hard to analyze and therefore difficult to account for and may also produce channel selection dependent errors.

The use of a high frequency clock derived from the DCO output also requires special synchronization of all the logic running in reference clock domain to the high frequency clock domain. Summary of the Invention

It is an object of the present invention to provide a phase-locked loop which overcomes the disadvantages of the prior art, or at least provides a useful alternative.

According to a first aspect of the present invention there is provided a phase locked loop circuit comprising a digitally controlled oscillator configured to receive a first signal and output a second signal dependent on the first signal and at least one mapping function; a phase comparator configured to receive the second signal and output a third signal dependent on the second signal, a reference signal and at least one phase comparator parameter; a loop filter configured to receive the third signal and generate the first signal dependent on the third signal and at least one filter parameter; and a controller configured to control at least one of: the at least one mapping function; the at least one phase comparator parameter; and the at least one filter parameter.

According to a second aspect of the present invention there is provided a method for operating a phase locked loop circuit comprising generating in a digitally controlled oscillator a second signal dependent on a first signal and at least one mapping function; generating a third signal dependent on the second signal, a reference signal and at least one phase comparator parameter; generating the first signal dependent on the third signal and at least one filter parameter; controlling at least one of: the at least one mapping function; the at least one phase comparator parameter; and the at least one filter parameter.

According to a third aspect of the present invention there is provided a computer program product configured to perform a method for operating a phase locked loop circuit comprising generating a second signal dependent on a first signal and at least one mapping function; generating a third signal dependent on the second signal, a reference signal and at least one phase comparator parameter; generating the first signal dependent on the third signal and at least one filter parameter; controlling at least one of: the at least one mapping function; the at least one phase comparator parameter; and the at least one filter parameter.

According to a fourth aspect of the invention there is provided a phase locked loop circuit comprising oscillator means for receiving a first signal and output a second signal dependent on the first signal and at least one mapping function; comparator means configured to receive the second signal and output a third signal dependent on the second signal, a reference signal and at least one phase comparator parameter; filter means for receiving the third signal and generate the first signal dependent on the third signal and at least one filter parameter; and controller means configured to control at least one of: the at least one mapping function; the at least one phase comparator parameter; and the at least one filter parameter.

According to a fifth aspect of the invention there is provided an apparatus comprising at least one stage, wherein each stage receives an input signal and at least two clock inputs and outputs at least two outputs with output values dependent on the value of the input signal and the value of the at least two clock signals.

According to a sixth aspect of the invention there is provided a method of operating apparatus comprising the steps of receiving an input signal and at least two clock inputs; generating at least two outputs with output values dependent on the value of the input signal and the value of the at least two clock signals.

According to a seventh aspect of the invention there is provided a computer program product configured to perform a method for operating apparatus comprising receiving an input signal and at least two clock inputs; and generating at least two outputs with output values dependent on the value of the input signal and the value of the at least two clock signals.

According to a eighth aspect of the invention there is provided an apparatus comprising at least one stage, wherein each stage comprises input means for receiving an input signal and at least two clock inputs; signal generation means for generating at least two outputs with output values dependent on the value of the input signal and the value of the at least two clock signals.

The phase-locked loop as described above may be incorporated into a mixer.

The phase-locked loop as described above may be incorporated into a transmitter.

The phase-locked loop as described above may be incorporated into a receiver.

The phase-locked loop as described above may be incorporated into a user equipment.

The phase-locked loop as described above may be incorporated into a base station.

Brief Description of the Drawings

Embodiments of the invention will now be described, by way of example only, with reference to the accompanying drawings in which:

Figure 1 shows a schematic diagram of a device capable of implementing embodiments of the invention;

Figure 2 shows a schematic diagram illustrating a frequency synthesizer capable of being implemented within the device of Figure 1 ;

Figure 3 shows a schematic diagram illustrating a DCO accumulator and time to digital converter capable of being implemented within the frequency synthesizer of Figure 2;

Figure 4 shows a schematic diagram illustrating a time to digital converter circuit as shown in Figure 3;

Figure 5 shows a further schematic diagram illustrating a further time to digital converter circuit as shown in Figure 3; Figure 6 shows a schematic example of the waveforms within a time to digital converter circuit as shown in Figure 5;

Figure 7 shows a further example of the waveforms within a time to digital converter circuit as shown in Figure 5;

Figure 8 shows a schematic diagram illustrating a full cycle error detector and fractional phase error sealer capable of being implemented within the frequency synthesizer of figure 2;

Figure 9 shows a flow diagram illustrating the embodiments of the invention implementing a phase-locked loop (PLL) settling process;

Figure 10 shows a flow diagram illustrating the embodiments of the invention implementing a digitally controlled oscillator (DCO) coarse frequency settling procedure; and

Figure 1 1 shows a flow diagram illustrating the embodiments of the invention implementing a time to digital converter (TDC) calibration operation.

Detailed Description of Preferred Embodiments

Figure 1 shows a schematic partially sectioned view of a possible electronic device capable of implementing embodiments of the invention. The electronic device may be a user equipment as shown in Figure 1 used for various tasks such as making and receiving phone calls, for receiving and sending data to and from a data network and for receiving and transmitting the data in the form of multimedia content. Although an electronic device is shown in the form of user equipment and specifically the implementation of the oscillator for communication purposes embodiments of the invention may be implemented in any electronic device requiring a stable but tuneable oscillator.

An appropriate electronic device may be any device capable of sending or receiving radio signals. Non-limiting examples include mobile stations (MS), user equipment (UE), portable computer equipment provided with a wireless interface card or other wireless interface facility, personal data assistants (PDA) provided with wireless communication capabilities, or any combinations of these or the like. The electronic device may communicate via an appropriate radio interface arrangement of the mobile device. The interface arrangement may be provided by means of a radio frequency and associated antenna arrangement 7. The antenna arrangement may be arranged internalfy or externally to the electronic device. The radio part may comprise at least one mixer configured to down-convert or up-convert signals to and from the mobile station. The mixer device may comprise a tuneable frequency synthesiser according to the embodiments of the invention. The term frequency synthesiser may also be known as a frequency oscillator. The frequency synthesiser/frequency oscillator may be capable of supplying an oscillation signal of various predetermined or defined frequencies.

The electronic device is typically provided with at least one data processor 3 and at least one memory 4 for storing data and instructions used by the data processor 3. The data processor 3 and memory 4 may be provided on an appropriate circuit board and/or in chip sets 6.

The user may control the operation of the electronic device by means of a suitable user interface such as a keypad 2, voice command, touch-sensitive screen or pad, or a combination thereof or the like. A display 5, a speaker and a microphone are also typically provided. Furthermore, an electronic device may comprise appropriate connectors (either wired or wireless) to other electronic devices and/or for connecting externa! accessories, for example hands-free equipment, thereto.

The remainder of the parts of the electronic device are known generally and do not assist in the understanding of the invention and will not be described in further detail hereafter.

Figure 2 shows a schematic view of a frequency synthesiser as implemented within the radio part 7 of Figure 1.

The frequency synthesiser 101 may be considered to comprise a series of interconnected functional blocks. The phase detector (PD) 107 receives the reference source input F_ref and the output of the digitally controlled oscillator 105 and outputs a detected phase signal to the discrete time loop filter 103.

The phase detector 107 comprises a digitally controlled oscillator (DCO) accumulator and time-to-digital converter (TDC) 127. The DCO accumulator may be a discrete time integrator which receives inputs from the output of the digitally controlled oscillator 105 and the reference frequency source and produces an output which is read for every reference source input signal cycle.

The time-to-digital converter measures the timing difference between the digitally controlled oscillator (DCO) and the reference source input signal.

The output of the TDC is a fractional part of the phase error between the DCO and the reference frequency signal.

With respect to figure 3, a schematic view of the digitally controlled oscillator (DCO) accumulator and time-to-digital converter (TDC) 127 is shown.

The DCO accumulator and TDC 127 are configured to receive two inputs. The DCO input 361 is configured to receive the DCO output. The reference input 363 is configured to receive the reference frequency source.

The DCO counter (CNT) 353 is configured to receive the DCO input and output an accumulated value or count of the DCO. The DCO counter is configured to be able to count the number of full DCO cycles within a specific period. The accumulated value is output from the DCO counter and passed to a first input of a synchronizer 355.

The synchronizer (SYNC) 355 furthermore is configured to receive a second input from the DCO input 361 directly and a third input from the reference input 363. The synchronizer 355 is configured to output an accumulation or complete number of cycles of the DCO within a time period defined by the reference frequency signal and to produce an output synchronized with the TDC 351.

In a radio frequency PLL system, the DCO counter 353 and the synchronizer 355 may be built using standard high-speed logic cells.

The Time to digital converter (TDC) 351 is configured to receive the DCO input 361 DCO signal and the reference input 363 reference frequency signal and measure an accurate phase difference between the two input signals.

The TDC 351 may also be built using standard logic cells. However in order to get high accuracy phase measurement results, special full-custom cells may also be used.

With respect to figure 4 the operation of a possible implementation of the TDC is described in further detail. The TDC comprises a plurality of TDC cells of which a first cell 451 , a second cell 453 and an n'th cell 455 is shown. Each cell is configured to be connected to a preceding and succeeding cell, except for the first cell 451 which is connected to a DCO input 461 and reference input 463 instead of a preceding cell, and the n'th cell 455 which is connected to a DCO output 477 and reference output 479 instead of a succeeding cell.

Each TDC cell comprises a first delay element 471 , 473, 475, which is configured to receive a DCO signal from a preceding cell or (for the first cell 451 ) the DCO input 461, perform a delay of a first predetermined time period (Delay_A) on the received DCO signal, and then output a delayed DCO signal to a succeeding stage or (for the n'th cell 455) the DCO output 477.

Each TDC cell furthermore comprises a second delay element 491 , 493, 495, which is configured to receive a reference signal from a preceding cell or (for the first cell 451) the reference input, perform a delay of a second predetermined time period (Delay_B) on the received reference signal, and then output a delayed reference signal to a succeeding stage or (for the n'th cell 455) the reference output 479.

In some embodiments of the invention the TDC cell may be constructed without using the delay element in the reference path 463 (de!ay_B cells).

Each TDC cell also comprises a memory or latch element 481 , 483, 485, which is configured to receive a data input from the DCO signal from a preceding cell or (for the first cell 451 ) the DCO input, and is docked from the reference signal from a preceding cell or {for the first cell 451 ) the reference input. The memory/latch outputs at the memory/latch output 461 , 463, 465 the value of the DCO signal at the sampling time determined by the reference signal.

The configuration of the cells is therefore to create two delay lines with different delay element values, one for the DCO signal (determined by the predetermined delay period Delay_A) and other for the reference signal (determined by the predetermined delay period Delay J3). The delay lines may then measure the phase differences between the signals. The latch/memory elements store the thermo-coded time difference between the DCO and REF signal edges.

The term thermo-coded means that the time difference is presented in certain digital format. For example a binary, decimal(analogue), and thermo-coded example is shown below: binary thermo-coded analogue small time difference 0010 000000000000111 3 big time difference 1010 0000001111111111 10

In thermo-coded digital words, number of ones defines the magnitude of the signal - i.e. anaiog 1 is equal to 00000001 , 2 is equal to 00000011 , 3 is equal to 00000111 up to the 8 being equal to 11111111 , (the maximum for a 8-bit thermo-coded digital word). The thermo-coded digital word is so called as it appears to be like a moving alcohol pillar in thermometers... For example, if the first delay period (DeIay_A) is 20ps and the second delay period (Delay_B) is 30ps and the therm o-coded word from the memory/latch changes at the second cell memory/latch 483, the phase difference between the DCO and REF signal edges can be calculated to be 10ps (1xDelay_A- 1xDelay_B). Similarly, with same deiay element values, a change detected at the output of a fifth memory/latch indicates a phase difference of 40ps (4xDelay_A-4xDelay_B).

However this type of TDC, known as a vernier delay line (VDL) may have drawbacks. In the situation where the required phase resolution is very small, the delay lines become very long, because the delay path length is proportional to required resolution. If for example the required phase measurement window is 500ps and required resolution is 10ps, the required number of delay elements is 50 (500ps/1 Ops).

Also mismatches in delay line elements may cause measurement errors, and the measurement resolution may become very bad. If e.g. one delay element has certain error in delay value, this error may be directly seen at the phase measurement result. As the TDC measures very small time period differences tolerances of individual delay elements must be very small. However practical implementation costs and parasitic production problems may result in such required .tolerances to be impossible to realize or may require significant amount of fine tuning and time consuming calibration operations to achieve.

With respect to figure 5 a TDC implementation is shown which may be employed in further embodiments of the invention. The further embodiment TDC is known as a multi-triggered vernier delay line (MT VDL). The MT VDL comprises a plurality of MT VDL cells of which a first cell 452, a second cell 454 and an n'th cell 456 are shown. Each cell is configured to be connected to a preceding and succeeding cell, except for the first cell 452 which is connected to the DCO input 461 and reference input 463 instead of a preceding cell, and the n'th cell 456 which is connected to the DCO output 477 and reference output 479 instead of a succeeding cell.

Each MT VDL cell comprises a first delay element 471 , 473, 475, which is configured in the same way as in the TDC implementation described above to receive a DCO signal from a preceding cell or (for the first cell 452) the DCO input 461 , perform a delay of a first predetermined time period (Delay_A) on the received DCO signal, and then output a delayed DCO signal to a succeeding stage or (for the n'th cell 456) the DCO output 477.

Each MT VDL cell furthermore comprises a second delay element 491 , 493, 495, which is configured to receive a reference signal from a preceding cell or (for the first cell 451 ) the reference input, perform a delay of a second predetermined time period (Delay_B) on the received reference signal, and then output a delayed reference signal to a succeeding stage or (for the n'th cell 455) the reference output 479.

Each TDC cell also comprises a memory or bank of latch elements 482, 484, 486, which are configured to receive a data input from the DCO signal from a preceding cell or (for the first cell 451 ) the DCO input, and are clocked from the reference signals from all cells. The memory/latch outputs at the memory/latch output 462, 464, 466 the value of the DCO signal at the sampling time determined by the reference signal. As each latch 482 is a latch bank containing N-times latches. Meaning that output of latch bank 482 is a N-bit digital word (not a single digital output

The use of multi-triggering allows the errors in individual delay elements to be averaged away by having multiple phase measurement results. Multiple results are generated by having several triggering memory/latches, for different REF signal delays.

With respect to figure 6 the averaging of errors in MT VDL implementations may be shown. Using the previous example where there is a difference time (Delta) of 20ps between the DCO and the reference signal REF, the basic VDL generates a delay result of 20ps as shown at reference point 2 501a and shown by the output of the latch/memory elements shown by reference 501b.

The 20ps delay result however produces in the MT VDL two additional results, which are shown with respect to the timing differences by references 503a and 505a and the output of the latch/memory elements by references 503b and 505b respectively.

If in an implementation of the MT VDL, due to parasitic components, mismatches etc., the multiple measurement results were 10ps, 20ps and 30ps, it may be possible to average the values to produce a delay result of 20ps.

In such embodiments as the MT VDL, where calibration is carried out for the whole delay path, errors in the individual deiay elements can be allowed for by averaging them. For example, in the previous example, delay element inaccuracies of -10ps and +10ps can be found and tolerated provided the cumulative offset is 0.

One possible calibration method is may be achieved by configuring the DCO and REF delay lines into a ring-mode, in other words connecting the DCO output 477 to the DCO input 461 and connecting the reference output 479 to the reference input 463, and analyzing the oscillation frequency. In one embodiment of the invention the oscillation frequency of the loops may be measured by using a counter for each loop. By adjusting the first and second delay periods (Delay_A and Delay_B) the delay path for the whole loop may then be set to have certain average delay values. For example an average first (Delay_A) time delay may be 20ps (for DCO path delay elements) and an average second (Delay_B) time delay may be 30ps (for REF delay path elements).

By using the general first and second predetermined delay element adjustment, in other words calibrating the whole delay line length and using multi-triggering topology, there is no need for exact calibration and tuning of individual delay line elements.

With respect to figure 7, the MT VDL implementation may be further shown to be advantageous, The graph of figure 7 shows a series of conversion curves. Each curve represents a 'single-triggered' VDL structure graph. As described above the individual delay elements may because of process errors and other parasitical effects, produce a conversion curve clearly suffering from non-ideal conversion curve behaviour. This is shown as each step is not regular but some steps in the curve are larger than others - indicating the time delay is not consistent between delay elements. In conventional VDL only curve 601 is available to provide a result, however using MT VDL implementations in time- to-digital conversion, two additional results shown by the intersections in curves 603 and 605 will be available. As the average of these three results, the final result accuracy will be improved and errors from any single curve will be averaged out as if the loop is calibrated then any sub-delay errors will be on average matched with a super-delay error.

The DCO accumulator and TDC 127 output the integer and fractional differences, the DCO count and the TDC output respectively to the phase comparator 121.

An example of a time-to-digital converter which may be implemented within an embodiment of the invention is shown in a co-pending application by the same applicant as shown in GB application XXXX (Nokia Reference 61289: PWF Reference 316141GB). In other embodiments of the invention any controllable Vernier delay line (VDL) time-to-digital converter (TDC) may be used to produce an output.

The phase comparator 121 receives the DCO accumulator result and the TDC result value and samples these values for each reference source input signal cycle. Furthermore the phase comparator 121 is configured to produce a scaling of TDC result value according to the desired frequency (which in a transceiver is dependent on the transceiver channel being used). In other words the TDC result value may be normalized by the phase comparator 121 to produce a TDC result value which is normalized to the full cycle of the desired digitally controlled oscillator (DCO) period. The scaled TDC result and DCO accumulator result values are summed for comparison with the reference source input signal as described previously above.

The phase comparator 121 outputs the scaled difference value to the discrete-time loop filter 103.

With respect to figure 8 the phase comparator 121 is shown in further detail.

The phase comparator comprises a full cycle error detector 851 and a fractional error detector 853.

The full cycle error detector 851 receives at a control input 855 a channel control signal from the synthesizer controller 135, and at a DCO input 857 a DCO counter value from the DCO accumulator and TDC 127 as described above and outputs a full cycle error value from a full cycle error output 859.

The channel control signal is input to an accumulator 810. The channel control signal represents the required ratio between the DCO output frequency and reference signal frequency. The accumulator may be implemented as shown in figure 8 by an adder 809 with one input receiving the control signal and a second input from the output of a unit delay (z^~1) 811. The output of the adder is input to the unit delay 811 . In other embodiments of the invention the accumulator 810 is implemented by other suitable circuitry as known in the art.

The accumulator 810 creates a reference phase-stamp value which is arranged to be output to an input of a selection block 813. The selection block filters a first number (N) of the most significant bits of the phase stamp. This fϋtered value is then output to an input of the comparator 815. The value of the first number (N) is a natural number equal to word length of the DCO counter output word length.

The comparator 815 furthermore receives a second input from the DCO input 857 with the DCO counter value. The comparator 815 may subtract the DCO counter value from the reference phase-stamp value which is output to the full cycle error output 859.. As is described later during loop settling and locked condition the reference and DCO accumulators may overflow at the same pace and therefore the calculated phase-error may remain in right scale.

The fractional error detector 853 receives at a TDC input 861 a TDC value from the DCO accumulator and TDC 127, and at a TDC normalize input 863 a TDC normalization signal from the TDC calibrator and outputs a fractional error value from a fractional error output 865.

In a preferred embodiment of the invention the TDC input signal from the TDC is a 4-bit coded output from each 16-bit latch row indicating in which phase the reference clock is compared to the DCO output signal. In the example described above there is 15 delay-A elements, 10 delay-B elements, and 11x16 latches. The first latch column is connected to "0-delay" node of delay line edge as well as the first clock signal is taken from the "0-delay" node of the delay-B branch, as shown in the Figure 5.

The 4-bit unsigned TDC input is passed to a mapper 801 which is configured to map the input 4 bit unsigned values into 6-bit signed values presenting the fractional phase-error. The mapper 801 may be a mapping table of size 11 x 15, 6-bit signed integers, and each row has its own mapping vector.

The mapping table is programmable in embodiments of the invention since the mapping may be changed according to the target DCO frequency. The TDC Input provides the indices for each row mapping. In some embodiments of the invention if the coded memory/latch row value is zero, this provides an indication that there is an error in the measurement of the fractional error, the TDC is not enabled, or the DCO frequency is out of the TDC detection range.

Where any of the above situations occur the mapper 801 may force the output to be mapped to zero. Otherwise the output value of the mapper 801 corresponds to the measured delay.

The output of the mapper 801 is passed to a summer 803 to generate a summed output dependent on the value of the mapper 801 output. The summed output is passed to a sealer 805.

The scaler 806 receives the sum of the mapped values and scales the received values to produce an averaged result and furthermore to normalize the result to the DCO cycle.

The normalization factor is dependent on channel selection in other words the required DCO value. The required DCO value may be passed to the sealer 806 via the TDC normalize input 863 from the synthesizer controller 135. The sealer 806 may be implemented as shown in figure 8 by a separate scaling/normalizer 805 followed by a summer 807. Furthermore in some embodiments of the invention the normalization multiplier may be implemented for example by a programmable shift operation and summing the shifted values. The output of the scaler is passed to the fractional error output 865.

The outputs from the fractional error output 865 and the full cycle error output 859 may then be combined in an adder 817 and the output phase error passed to the configurable discrete-time loop filter, which may be implemented as infinite impulse response filter (IiR).

The discrete-time loop filter (which may be a configurable infinite impulse response filter) 103 receives the detected phase error signal from the phase comparator 121 of the phase detector 107 and outputs a filtered phase difference to the digitally controlled oscillator 105. The discrete-time loop filter 103 may be configured to produce a zero-pole pair for the loop transfer function in order to stabilise the loop. The discrete-time loop filter 103 may be configured so that the location of the zero and the pole may be adjustable in order to optimise the in-band noise for a certain system or to tune the filter during the settling sequence in such a manner that the settling period is shorter.

The digitally controlled oscillator (DCO) 105 receives the input from the discrete-time loop filter 103 (configurable infinite impulse response filter) and outputs the digitally controlled oscillator output to the phase detector 107.

The DCO block 105 comprises a digitally controlled oscillator (DCO) control mapper 131 , a digitally controlled oscillator 133, and a DCO calibrator 111 .

The DCO control mapper 131 receives outputs from the configurable infinite impulse response filter 103 and the discrete controlled oscillator (DCO) calibrator 111. The DCO control mapper 131 comprises a series of mappings by which input signals are mapped to produce a control output for the digitally controlled oscillator 133. The digitally controlled oscillator control mapper 131 in practice has several parallel control matrices to produce the mapping function.

The DCO calibrator 111 receives the output of the DCO and determines if there has been any potential drift of the digitally controlled oscillator tuning characteristics due to IC processing variations and environmentally variations and provides a trimming or adjustment signal to the DCO control mapper 131 to assist in the prevention in any change of the output frequency due to environmental conditions or construction changes.

The TDC calibrator 109 receives the output from the reference frequency signal and outputs to the DCO accumulator and TDC 127. The TDC calibrator 109 maintains control of the DCO accumulator and TDC 127 such that the TDC signal is kept within certain limits. For example, the TDC calibrator 109 may track changes in the measurement resolution due to environmental changes and compensate for effects in both environmental changes and IC production variations to prevent these limits being exceeded.

The synthesizer controller 135 controls the operation of the frequency synthesizer 101 so that there may be a separate phase-locked loop settling state and a locked-in state.

With respect to Figure 9, the overall process of settling the phase-locked loop as controlled by the DCO calibrator 1 11 , the TDC calibrator 109, the discrete- time loop filter 103, and the synthesizer controller 135 as performed by embodiments of the invention is shown in further detail. As briefly described above, the PLL settling process is the process performed when the PLL acquires a new synthesized frequency output.

The settling process, required to stabilize and maintain control of the phase locked loop digitally controlled oscillator frequency synthesizer may be divided into four parts or phases. The first part/phase is an initialisation phase 201 , the second part/phase is a locking phase 203, the third part/phase is a performance tuning phase 205 and the fourth part/phase is a run-time adjustment phase 207.

The initialisation phase 201 may be divided into the operations of setting the digitally controlled oscillator (DCO) coarse centre frequency 251 , calibrating the time to digital converter (TDC) 253 and an initialization check 255. The initialization check 255 holds the control process in the initialisation phase 201 until it detects that the steps of setting the digitally controlled osciliator (DCO) coarse centre frequency 251 and calibrating the time to digital converter 253 operations have been completed. Once the Initialisation check 255 determines that both of the operations have been completed the initialisation check 255 releases the hold and the process enters the locking phase 203. The setting of the DCO coarse frequency 251 operation is further described with respect to Figure 10.

The setting of the DCO coarse frequency 251 operation may be divided into a measurement stage 301, a comparison stage 303, and a ready stage 305.

The setting of the DCO coarse frequency 251 operation is described with respect to a DCO system 105 having three digitally controlled oscillator tuning ladders or scales. The operation and performance of an oscillator tuning ladder may be seen in co-pending patent application number xxxx (PWF Reference 316143, Nokia Reference NC 60280). However similar control operations may be performed using other oscillation tuning systems. In further embodiments of the invention more than 3 tuning ladders or scales may be employed.

In such tuning ladder or scales, each ladders or scale is a series of discrete inputs each input configured to produce a specific tuneable output frequency from the digitally controlled oscillator and therefore each ladder defining a series of inputs which define a range of possible frequency tuning steps.

In the embodiments described above the three digitally controlled oscillator tuning ladders are a fine setting ladder (DCO_fine), where the differences between control steps produce a relatively small change in output frequency, a first coarse setting ladder (DCO_coarse1), which has a relatively larger difference in frequency output for each control step selection when compared to the fine setting ladder, and a second coarse setting ladder (DCO_coarse2) which has a relatively larger difference in frequency output for each control step selection when compared against both the first coarse setting ladder and the fine control ladder. The three ladder controls are configured so that the first coarse setting ladder is configured to produce a controlled frequency range within the controlled frequency range of the second coarse setting ladder and that the fine setting ladder is configured to produce a controlled frequency range within the controlled frequency range of the first coarse setting ladder. However both the first coarse setting ladder and the fine setting ladder is configured to be adjustable within the range defined by the second coarse setting ladder and the first coarse setting ladder respectively.

The measurement stage defines a series of steps where the DCO output is measured to aliow a comparison to be carried out in defining the setting ladder settings.

The first step within the measurement stage is to set the fine setting ladder (DCOJine) control and the first coarse setting ladder (DCO_coarse1 ) control to a constant value (relative to the second coarse setting ladder) and set the second coarse setting ladder (DCO_coarse2) control as well as the iteration increment to an initial setting. Iteration increment is the amount that the DCO_coarse2 control is increased or decreased on iteration round.

This step may be carried out by performing an initial frequency measurement of the output frequency of the DCO. This second coarse setting centre frequency calibration measurement may require an accuracy of approximately 40MHz in order to provide a suitable starting reference point for the second coarse setting control to improve on after the phase locked loop is closed and the filter takes the control.

In some embodiments of the invention the PLL initialized or configured for this measurement operation and whilst the DCO coarse centre frequency setting operation is in progress the measurement value may be derived from the output of the phase comparator directly. Thus the output of the phase comparator, the DCO accumulated value and the TDC value may be generated bypassing the loop filter arrangement. This initial loop configuration step is shown in figure 10 by step 311.

The measurement of the frequency output is started as shown in figure 10 by step 313. The measurement may in some embodiments be carried out by the phase detector, however in preferred embodiments of the invention the measurement is carried out according to the methods described in US patent 7142062, "VCO TUNING METHOD BASED ON FREQUENCY MEASUREMENTAND ARITHMETICAL ESTIMATES".

The controller detects when the measurement is ready. This can be seen in figure 10 by step 315. The measurement period may be defined by a period set by the reference frequency as described previously in the DCO accumulator and TDC. If the measurement is not ready the step holds the operation until the measurement is ready. When the measurement is ready the operation passes to the comparison stage 303 and the iteration detection step 321.

The comparison stage 303 uses the measurement values and compares the measurement against a target value to initialize the ladder settings.

The first step of the comparison stage 303, is the iteration detection step 303. In order to prevent the operation from remaining in an endless loop of configuration adjustments the controller determines if a required number of measurement iterations have been completed. If the number of measurement iterations has reaches a predetermined target then the operation passes directly to the ready stage 305 done step 331 , otherwise the method passes to the comparison step 323. The number of iterations required is chosen dependent on the particular DCO design.

The measurement comparison step 323, compares the measured frequency output from the DCO against the required or target frequency. If the measured frequency is greater than the required or target frequency, the operation passes to step 325 otherwise the operation passes to step 327.

In step 325, the DCO calibrator 1 11 is configured to set the DCO control mapper 131 new DCO tuning word to be 0.5 times the current increment value subtracted from the current DCO tuning word value. This amended word value is stored in the DCO mapper 131. Furthermore the number of iterations count increases by 1 , and the operation passes to the start measurement step 313 of the measurement phase 301 to begin another loop iteration.

In step 327, the DCO calibrator 111 is configured to set the DCO control mapper 131 new DCO tuning word to be 0.5 times the current increment value added to the current DCO tuning word. The amended word value is stored in the DCO mapper 131 , the number of iterations count increases by 1 , and the operation passes back to the start measurement step 313 of the measurement phase 301 to begin another loop iteration.

After a sufficient number of iterations the measured frequency will be on average close enough to use run-time tuning to reduce the error between the measured and closest second coarse tuning ladder setting (the DCO_coarse2 tuning word).

The ready stage 305 and the done step 331 signifies the end of the DCO coarse setting operation and passes the process back to the initialisation phase of the PLL settling process 201 and specifically step 255 where the initialization steps are checked to see if they have been carried out.

With respect to Figure 11 , the time to digital conversion (TDC) calibration operation is shown in further detail. As described above the TDC process is arranged to output the fractional difference between the DCO output and the reference signal and that by calibrating a delay chain length within the TDC then individual delay element errors may be allowed for and not produce errors in the phase detection process.

The TDC calibration operation 253 may be considered to comprise three stages: the configure stage 401; the detect locking stage 403; and the ready stage 405.

The configuration stage describes a series of steps which initialize and configure the TDC calibrator 109. The TDC calibration operation 253 configuration phase 401 configuration step 411 selects delay eiements or in this example two inverter ring-oscillators with inverter cells which are arranged in the same manner as the delay elements used within the actual TDC circuit. Furthermore the first set of delay elements (inverter ring oscillator) is configured to operate in a phase locked loop arrangement with the reference clock signal as the reference signal, and the second set of delay elements (inverter ring oscillator) is configured to operate in a phase locked loop arrangement with a defined frequency offset value.

In other words the TDC calibrator 109 comprises two delay lines similar to actual TDC delay lines connected so that they operate in a se!f-oscil!atiπg mode. In this calibration mode the two self-oscillating deiay lines are configured to oscillate at different frequencies. The frequency offset is the difference of the two oscillation frequencies.

For example the required time delay period (Delay_A) for each buffer cell in one of the delay element chains is such that the seif oscillating replica of delay chain A is oscillating at a frequency 80 times the reference frequency.

Furthermore the delay difference between delay elements in each chain are such that the self oscillating frequency of the other delay chain (generated from delay elements with a time delay period of C) is 87 times the reference frequency.

The digital control signals which are used to set these self-oscillating calibration delay chains are known as the TDC tuning word.

Following this configuration step 41 1 the operation passes to the start calibration step 413.

The start calibration step passes the operation to the detect locking phase 403 and specifically to the detect tuning word change step 425.

The detect locking phase 403 is a series of steps which determine the configuration of the TDC for a new frequency setting. The detect tuning word change step detects or determines a TDC tuning word change, (n other words the output difference between consecutive tuning words TDC calibrator 109 is calculated.

When the loop locks the tuning word of the ring-oscillator may start to oscillate between two values. This oscillation is detected by the correlate with lock pattern step 423 which will detect a correlation with the lock pattern step where the difference between consecutive words starts to oscillate having two values -1 and 1.

However as the oscillation pattern may also occur during the settling of the calibration loop a further step of integrating the absolute value of the correlator output may be carried out.

The output of the correlator is then compared against a limit which providing the limit is exceeded the TDC correctly locked and the method passes to a setting of the TDC control step 431. Otherwise the process is looped back to the detection/determination of the difference in the TDC tuning word value generated by the replica delay element loops.

The iimit may be predetermined by simulations when the loop response is designed.

The setting of the TDC tuning controls step 431 , occurs when the controller detects that the ring-oscillators control loops are locked. When a lock is detected the converged tuning words can be read from the ring-oscillators and used by the TDC calibrator to set the actual TDC delay element chain controls accordingly.

Once the TDC tuning controls are set the next step is the TDC calibration operation done step 433. The operation then passes to the phase-locked loop setup process step 255 which checks whether or not initialization has been carried out. With reference to Figure 9 foliowing the initialization operations and the initialization checking step 255 determining that both a coarse DCO centre frequency has been set and that the TDC has been calibrated the process passes to the locking phase 203 of the process and specifically step 261 , the setting of the filter coefficients with respect to the current DCO_coarse2 settings.

The setting the filter coefficients for the infinite impulse response (IiR) filter with respect to the second coarse DCO control ladder settings, as shown by step 261 of figure 9, may then carried out. The synthesizer controller 135 writes predefined values to the control registers which control the filter 103. These values thus may be considered to define the transfer function of the closed loop. The synthesizer controller 135 by changing the programmable parameters that affect the filter frequency response and gain therefore determine the phase margin and the open loop bandwidth of the loop.

The next step, step 263, sets the filter coefficients for the MR filter according to the first coarse DCO control ladder settings.

These parameters may be set or reset to different values for locking each of the DCO tuning controls since each of the DCO control arrays may have a different gain value. For example the resolution of the second coarse ladder tuning settings (DCO_coarse2) may be 10 MHz, and the resolution of the first coarse ladder tuning setting (DCO_coarse1) may be 10OkHz, and the resolution of the fine ladder tuning setting (DCO_fine) may be 500Hz. Each of these ladder tuning arrays may comprise different parallel capacitor arrays to generate this range which would require different settings for the programmable parameters of the filter in order to maintain a consistent loop gain.

Furthermore the programmable parameters of the filter may be set to different values to optimize the settling time in the locking phase. In the above examples it is not required to optimize the filter coefficients to gain optimum bandwidth with the two coarse DCO tunings. Thus for locking these coarse steps the filter parameters may be set so that a loop bandwidth and the phase margin is optimized to produce a fast settling time. In fine tuning the filter parameters may be set so that the loop response is optimized for the system requirements of the focal oscillator signal.

When locking the coarse tunings the corresponding DCO tuning word is set to its final value achieved after the tuning word has settled. Hence only one of the tuning arrays is settled at each time.

The next step in the locking phase 203, step 265, sets the filter coefficients for the MR filter according to the fine DCO control ladder settings. Whereas in embodiments of the invention the first and second coarse control ladder filter predetermined parameters are fixed when set, the fine tuning word filter parameters are not fixed or constant but may be further controlled by the synthesizer controller 135 during further running of the DCO to correct for any environmental condition changes.

Following this step in the locking phase 203, the process passes to the performance tuning phase 205.

The performance tuning phase 205 describes a series of steps within which while the PLL has been locked further steps are taken to optimize the performance of the PLL.

The first step, step 271 , measures the digitally controlled oscillator (DCO) gain. The DCO gain may be measured for example by inserting a simple reference measurement into the PLL by modulating the DCO input (which may be achieved by adding a predetermined signal to the loop filter output) and detecting the signal change at the phase detector output.

The DCO gain estimate may then be used to estimate the DCO gain difference to the initial estimated DCO gain. In other words, the locking phase, uses an assumed DCO gain value from which the filter gain value is calculated from to adjust the overall open loop gain (to produce the desired closed loop response). The DCO gain estimate may then permit a more accurate filter gain adjustment as shown in step 273.

In step 273, the filter gain is adjusted dependent on the measured DCO gain. In other words using the measured DCO gain difference to the initial estimated DCO gain the filter gain may be re-adjusted to generate the desired loop response.

The advantage by applying this additional stage of performance tuning is that it is possible to reduce the variation of the PLL loop response. For example in a WCDMA system the PLL may have a certain allowed phase noise contribution from the local oscillator signal on the overall noise level in the receiver output. In such a system an average DCO gain value over the frequency band and over the process variation range may produce a resultant noise contribution which may not meet the requirements in all transceiver circuits. However any loop response variation may be reduced by the self- calibration and adjustment methods described above permitting better process yield and performance.

Following the adjustment of the filter gain, the process passes to the run time adjustment phase 207. The run-time adjustment phase 207 is a series of steps which monitor and adjust the DCO calibration and the TDC calibration to counter any run time environmental changes affecting the PLL behaviour.

The first step of the run-time adjustment phase 207, step 281 , is setting and starting a timer to measures a count value. The counter is used to cause a delay in each run-time adjustment loop so that the run-time adjustments are only carried out at specified time periods.

The following step, step 283, determines if the counter is greater than 1 ms. If the counter value is less than 1 ms then the process passes back to the timer step 281. When the counter value is greater than 1ms then the process moves to step 285. The steps 281 and 283 may be seen as being a counter which at a predefined period triggers the following two steps. Although the time period is described above and shown in figure 9 as being 1ms, it would be appreciated by the person skilled in the art that other time periods may be applied - where the longer the time period the greater the energy and complexity saving as DCO and TDC adjustments are further apart but with the greater possibility of drift errors, and the shorter the time period the smaller the possibility of drift errors but the more complex and energy consumed by the more frequent adjustments.

In step 285, the controller is configured to adjust the digitally controlled oscillator first coarse frequency control settings. During this step the tuning word of the DCO fine tuning (DCO_fine) ladder is sampled. The sampled tuning word is then compared against a predetermined upper error and lower error limit and where the value is over the predefined upper limit or under the predefined lower limit the first coarse tuning value (DCO_coarse1 ) is readjusted so that the DCO_fine tuning range settles again between the predefined limits. This in embodiments of the invention may be performed by either increasing or decreasing by one the DCO first coarse tuning word depending if the limit crossed was the upper or the lower limit.

Following the adjustment of the digitally controlled oscillator first coarse frequency control settings (DCO_coarse1 ), the following step, step 287, is to calibrate the TDC. Furthermore as the delay of the delay elements (which may as described above be inverters) used in the time to digital domain conversion may be temperature dependent, the TDC calibration step needs to be carried out from time to time. This step therefore carries out the operation described with respect to figure 11 and step 253 using the. Following the calibration of the TDC the timer is reset and process passes back to step 281 to restart the counter.

The reason for carrying out a TDC calibration in this phase is because of the possible environment changes. These environment changes are mainly temperature related but may also be changes in supply voltage, which cause the delay period of the delay elements to change.

The run time adjustments in step 285 are carried out to the DCO design variables because the DCO frequency will drift according to any temperature change. Any drift of the DCO frequency may cause the fine DCO control settings (DC0_fine) to overflow.

Whilst in time division communication standards with short frame lengths, for example in GSM, this is not a problem, in wideband code division multiple access (WCDMA) where the loop is settled only once at the beginning of the connection, this may produce an unacceptable error value.

The overflow may be prevented in further embodiments of the invention by the run time adjustment process having the first coarse and the fine frequency control ladders (DCO_coarse1 and DCO_fine) arranged such that they overlap so that the tuning range DCO_fine covers at least two DCO_coarse1 steps.

The DCO_fine tuning control may then be monitored and when exceeding or going below a certain limit, the controller may be arranged to increase or decrease the DCO coarse step by a value. Although, this may cause a short peak in the phase error of the phase-locked loop output signal, since the loop is a control feedback loop, the DCO_fine ladder settles again quickly.

The advantages of the system described above over the examples provided by the prior art are that the embodiments of the invention do not require dynamic control operations in other words, there is no requirement to create time division deita-sigma modulation control of the switching element.

Furthermore, in embodiments of the present invention, the clock rate of the digitally controlled osciilator interface does not have to be significantly high in terms of several hundred of megahertz in order to suppress the high frequency noise produced by the dynamic control as indicated in the prior art documents.

User equipment may comprise an apparatus such as those described in embodiments of the invention above.

It shall be appreciated that the term user equipment is intended to cover any suitable type of wireless user equipment, such as mobile telephones, portable data processing devices or portable web browsers.

Furthermore elements of a public land mobile network (PLMN) may also comprise apparatus as described above.

In general, the various embodiments of the invention may be implemented in hardware or special purpose circuits, software, logic or any combination thereof. For example, some aspects may be implemented in hardware, while other aspects may be implemented in firmware or software which may be executed by a controller, microprocessor or other computing device, although the invention is not limited thereto. While various aspects of the invention may be illustrated and described as block diagrams, flow charts, or using some other pictorial representation, it is well understood that these blocks, apparatus, systems, techniques or methods described herein may be implemented in, as non-limiting examples, hardware, software, firmware, special purpose circuits or logic, general purpose hardware or controller or other computing devices, or some combination thereof.

For example the embodiments of the invention may be implemented as a chipset, in other words a series of integrated circuits communicating among each other. The chipset may comprise microprocessors arranged to run code, application specific integrated circuits (ASICs), or programmable digital signal processors for performing the operations described above.

The embodiments of this invention may be implemented by computer software executable by a data processor of the mobile device, such as in the processor entity, or by hardware, or by a combination of software and hardware. Further in this regard it should be noted that any blocks of the logic flow as in the Figures may represent program steps, or interconnected logic circuits, blocks and functions, or a combination of program steps and logic circuits, blocks and functions.

The memory may be of any type suitable to the local technical environment and may be implemented using any suitable data storage technology, such as semiconductor-based memory devices, magnetic memory devices and systems, optical memory devices and systems, fixed memory and removable memory. The data processors may be of any type suitable to the local technical environment, and may include one or more of genera! purpose computers, special purpose computers, microprocessors, digital signal processors (DSPs) and processors based on multi-core processor architecture, as non-limiting examples.

Embodiments of the inventions may be practiced in various components such as integrated circuit modules. The design of integrated circuits is by and large a highly automated process. Complex and powerful software tools are available for converting a iogic level design into a semiconductor circuit design ready to be etched and formed on a semiconductor substrate.

Programs, such as those provided by Synopsys, Inc. of Mountain View, California and Cadence Design, of San Jose, California automatically route conductors and locate components on a semiconductor chip using well established rules of design as well as libraries of pre-stored design modules. Once the design for a semiconductor circuit has been completed, the resultant design, in a standardized electronic format (e.g., Opus, GDSII, or the like) may be transmitted to a semiconductor fabrication facility or "fab" for fabrication.

The foregoing description has provided by way of exemplary and non-limiting examples a full and informative description of the exemplary embodiment of this invention. However, various modifications and adaptations may become apparent to those skilled in the relevant arts in view of the foregoing description, when read in conjunction with the accompanying drawings and the appended claims. However, all such and similar modifications of the teachings of this invention will still fall within the scope of this invention as defined in the appended claims.

Claims

1 . A phase locked loop circuit comprising; a digitally controlled oscillator configured to receive a first signal and output a second signal dependent on the first signal and at least one mapping function; a phase comparator configured to receive the second signal and output a third signal dependent on the second signal, a reference signal and at least one phase comparator parameter; a loop filter configured to receive the third signal and generate the first signal dependent on the third signal and at least one filter parameter; and a controller configured to control at least one of: the at least one mapping function; the at least one phase comparator parameter; and the at least one filter parameter.

2. The phase locked loop circuit as claimed in claim 1 , wherein the phase comparator comprises a fractional error circuit comprising at least one delay line, each delay line comprising a plurality of delay elements having a nominal time delay period controlled by the at least one phase comparator parameter; wherein the controller is configured to control each delay line total delay period by adjusting the at least one phase comparator parameter.

3. The phase locked loop circuit as claimed in claim 2, wherein the phase controller comprises at least one further delay line, and each of the at least one further delay lines is associated with the at least one delay line.

4. The phase locked loop circuit as claimed in claim 3, wherein controller is configured to determine a control signal for each of the at least one delay line dependent on a further control signal configured to generate a required delay period for the associated further delay line.

5. The phase locked loop as claimed in claims 1 to 4, wherein each mapping function is configured to be adjustable.

6. The phase locked loop as claimed in claim 5, wherein each mapping function may be described in terms of a digitally controlled oscillator output centre frequency and frequency range.

7. The phase locked loop as claimed in claim 6, wherein the digitally controlled oscillator comprises at least three mapping functions.

8. The phase locked loop as claimed in claims 6 and 7, wherein the controller is configured to monitor the input of the digitally controlled oscillator and adjust the digitally controlled oscillator output centre frequency for at least one of the mapping functions dependent on the monitor output.

9. The phase locked loop as claimed in claims 1 to 8, wherein the controller is configured to determine the at least one filter parameter dependent on at least one of the phase locked loop closed loop response and the phase locked loop phase margin.

10. The phase locked loop as claimed in claim 9 when dependent on claim 8, wherein the controller is configured to determine the at least one filter parameter for each of the at least one mapping functions.

11. The phase locked loop as claimed in claim 10, wherein the controller is further configured to determine a digitally controlled oscillator gain for each of the determined at least one filter parameters for each of the at least one mapping functions.

12. The phase locked loop as claimed in claim 1 1 , where the controller is further configured to redetermine the at least one filter parameter for each of the at least one mapping functions dependent on the determined digitally controlled oscillator gain.

13. A method for operating a phase locked loop circuit comprising: generating in a digitally controlled oscillator a second signal dependent on a first signal and at least one mapping function; generating a third signal dependent on the second signal, a reference signal and at least one phase comparator parameter; generating the first signal dependent on the third signal and at least one filter parameter; controlling at least one of:^' the at least one mapping function; the at least one phase comparator parameter; and the at least one filter parameter.

14. The method for operating a phase locked loop circuit as claimed in claim 13, further comprising: generating a fractional error value from at least one delay line, each delay line comprising a plurality of delay elements having a nominal time delay period controlled by the at least one phase comparator parameter; wherein the controller is configured to control each delay line total delay period by adjusting the at least one phase comparator parameter.

15. The method for operating a phase locked loop circuit as claimed in claim 14, further comprising associating at least one further delay line with each of the at least one delay line.

16. The method for operating a phase locked loop circuit as claimed in claim 15, further comprising determining the at least one phase comparator parameter for each of the at least one delay line dependent on determining at least one control signal configured to generate a required delay period for each associated further delay line.

17. The method for operating a phase locked loop as claimed in claims 12 to 16, wherein each mapping function is configured to be adjustable.

18. The method for operating a phase locked loop as claimed in claim 17, wherein each mapping function may be described in terms of a digitally controlled oscillator output centre frequency and frequency range.

19. The method for operating a phase locked loop as claimed in claim 18, wherein the digitally controlled oscillator comprises at least three mapping functions.

20. The method for operating a phase locked loop as claimed in claims 18 and 19, further comprising monitoring the input of the digitally controlled osciilator and adjusting the digitally controlled oscillator output centre frequency for at least one of the mapping functions dependent on the monitoring.

21. The method for operating a phase locked loop as claimed in claims 13 to 2O₁ further comprising determining the at least one filter parameter dependent on at least one of the phase locked loop closed loop response and the phase locked loop phase margin.

22. The method for operating a phase locked loop as claimed in claim 21 when dependent on claim 20, further configured to determine the at least one filter parameter for each of the at least one mapping functions.

23. The method for operating a phase locked loop as claimed in claim 22, further comprising determining a digitally controlled oscillator gain for each of the determined at least one filter parameters for each of the at least one mapping functions.

24. The method for operating a phase locked loop as claimed in claim 23, further comprising redetermining the at least one filter parameter for each of the at least one mapping functions dependent on the determined digitally controlled oscillator gain.

25. An apparatus comprising a phase locked loop as claimed in claims 1 to 12.

26. A frequency synthesizer comprising a phase locked loop as claimed in claims 1 to 12.

27. A chipset comprising a phase locked loop as claimed in claims 1 to 12.

28. An electronic device comprising a phase locked loop as claimed in claims 1 to 12.

29. A computer program product configured to perform a method for operating a phase locked loop circuit comprising: generating a second signal dependent on a first signal and at least one mapping function; generating a third signal dependent on the second signal, a reference signal and at least one phase comparator parameter; generating the first signal dependent on the third signal and at least one filter parameter; controlling at least one of: the at least one mapping function; the at least one phase comparator parameter; and the at least one filter parameter.

30. A phase locked loop circuit comprising; oscillator means for receiving a first signal and output a second signal dependent on the first signal and at least one mapping function; comparator means configured to receive the second signal and output a third signal dependent on the second signal, a reference signal and at least one phase comparator parameter; filter means for receiving the third signal and generate the first signal dependent on the third signal and at least one filter parameter; and controller means configured to control at least one of: the at least one mapping function; the at least one phase comparator parameter; and the at least one filter parameter.

31. Apparatus comprising at least one stage, wherein each stage receives an input signal and at least two clock inputs and outputs at least two outputs with output values dependent on the value of the input signal and the value of the at least two clock signals.

32. The apparatus as claimed in claim 31, wherein each stage comprises at least two latches, each latch configured to receive the input signal and one of at least two clock signals, and output the value of the input signal dependent on the value of the received clock signal,

33. The apparatus as claimed in claims 31 and 32, wherein the second of the at least two clock signals is a time delayed version of the first of the at least two dock signals.

34. The apparatus as claimed in claims 31 to 33, wherein each stage comprises a delay celi, wherein the delay cell is configured to receive the input signal and generate a time delayed output signal.

35. The apparatus as claimed in claim 34, wherein the time delayed output signal is received as the input signal for a successive stage.

36. The apparatus as claimed in claims 31 to 35, wherein each of the two outputs indicates the time difference between the input signal and a clock signal.

37. A method of operating apparatus comprising the steps of: receiving an input signal and at least two clock inputs; generating at least two outputs with output values dependent on the value of the input signal and the value of the at least two clock signals.

38. The method as claimed in claim 37, wherein each stage comprises at least two latches, the method comprising receiving at each latch the input signal and a different one of at least two clock signals, and generating at each latch the value of the input signal dependent on the value of the received different one of the clock signals.

39. The method as claimed in claims 37 and 38, further comprising generating a second of the at least two clock signals by time delaying a first of the at least two clock signals.

40. The method as claimed in claims 37 to 39, further comprising generating a delayed input signal.

41. The method as claimed in claim 40, further comprising receiving in a successive stage the delayed input signal.

42. The method as claimed in claims 37 to 41 , wherein each of the two outputs indicates the time difference between the input signal and a clock signal.

43. A computer program product configured to perform a method for operating apparatus comprising: receiving an input signal and at least two clock inputs; and generating at least two outputs with output values dependent on the value of the input signal and the value of the at least two clock signals.

44. Apparatus comprising at least one stage, wherein each stage comprises input means for receiving an input signal and at least two clock inputs; signal generation means for generating at least two outputs with output values dependent on the value of the input signal and the value of the at least two dock signals.