JPH04368020A - Frequency synthesizer - Google Patents

Abstract

PURPOSE:To attain miniaturization and low power consumption by forming a phase comparator circuit with a counter circuit and a latch circuit as a digital circuit and adopting a digital circuit for a loop filter connecting to its post-stage. CONSTITUTION:A phase comparator circuit consists of a counter circuit 15 and a 1st latch circuit 16 as digital configuration and a digital circuit is adopted for a loop filter connecting to a post-stage. Moreover, a D/A converter circuit 18 is connected to a post stage of the digital loop filter 17 to use an output of the digital loop filter for a control voltage of a voltage controlled oscillator (VSO). Thus, since the phase comparator circuit and the loop filter 17 being major circuits of a conventional frequency synthesizer are configured as digital circuits, an A/D converter circuit having been used for a conventional frequency synthesizer is not required. Thus, the compensation error in a VCO characteristic fluctuation due to a difference between the A/D converter circuit and the D/A converter circuit is eliminated.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the structure of a frequency synthesizer that is small in size, has low power consumption, and can switch frequencies at high speed, and particularly relates to a frequency synthesizer that can be applied to a local oscillator of a mobile communication radio device.

0002

2. Description of the Related Art Radio equipment for mobile communication uses a frequency synthesizer as an internal local oscillator in order to perform transmission and reception at a plurality of different frequencies. This frequency synthesizer is a phase-locked loop (hereinafter referred to as PLL) as shown in Figure 12.
It consists of The output frequency of a voltage controlled oscillator circuit (hereinafter referred to as VCO) changes according to the input DC voltage (control voltage). Local oscillators used in mobile communications and the like require frequency stability on the PPM order, but it is difficult to achieve such frequency stability with a single VCO. In order to stabilize this, a PLL is configured to increase the stability of the output frequency to that of the reference oscillator. The output frequency of this frequency synthesizer is determined by the frequency division ratio N of the variable frequency divider circuit.
It can be switched by Since the PLL operates so that the output frequency fref of the reference oscillation circuit and the output frequency f0/N of the variable frequency divider circuit are equal,

0003

[Math 1]

0004

[Math 2]

[0005] Since the frequency division ratio is an integer, it can be set at intervals of the output frequency fref. In order to incorporate such a frequency synthesizer into a mobile radio communication device, it is important to miniaturize the circuit. For this reason, the phase comparator circuit and the variable frequency divider circuit are implemented using digital circuits to facilitate circuit integration. In this way, conventionally used phase comparator circuits are implemented as digital circuits, but they are semi-analog circuits that output the detected phase difference in proportion to the pulse width. An example of its operation is shown in FIG. When the variable frequency divider circuit output signal lags behind the reference oscillation circuit output signal, the phase comparator circuit outputs a lag signal D having a pulse width proportional to the phase difference. Also,
If the variable frequency divider circuit output signal leads the reference oscillation circuit output signal, the phase comparator circuit outputs a lead signal U having a pulse width proportional to the phase difference. The phase difference detected in this way is added to a loop filter as shown in Fig. 14,
This loop filter output was used as the control voltage of the VCO. As described above, since the conventional phase comparison circuit operates in a semi-analog manner, the loop filter connected to the subsequent stage is realized by an analog circuit. Therefore, it becomes difficult to digitize the circuit including the loop filter.

On the other hand, in recent years, there has been an increasing need for high-speed switching of radio frequencies in wireless devices for mobile communication. Therefore, high-speed switching of the frequency of the frequency synthesizer is required. As described above, since the frequency synthesizer constitutes a negative feedback loop using a PLL, a certain switching time depending on the characteristics of the loop is required in order to switch to a desired frequency. When designing an 800MHz band synthesizer for mobile communication with the configuration shown in Figure 12,
The switching time to switch the frequency to 25MHz is approximately 20
ms. However, systems that require a frequency switching time of 1 ms or less are also taking shape. In order to speed up such frequency switching, a synthesizer as shown in FIG. 15 has been proposed (Japanese Patent Application No. 63-21858).
No. 6). This synthesizer includes an A/D conversion circuit, a D/A
It is composed of a conversion circuit, a setting circuit, and a PLL circuit shown in FIG. Furthermore, the setting circuit is composed of a voltage setting circuit and a frequency division ratio setting circuit, and is connected to a microprocessor, ROM, RA
This is realized using a digital circuit such as M. This frequency switching of the synthesizer presets the control voltage of the VCO from the D/A conversion circuit at the same time as the frequency division ratio N is changed. Since the preset voltage is the VCO control voltage corresponding to the desired frequency, the output voltage of the loop filter does not change with frequency switching. Therefore, the frequency can be switched at high speed.

In the configuration shown in FIG. 15, when frequency data is input from the outside, the frequency division ratio setting circuit sets a frequency division ratio N corresponding to the frequency in the variable frequency division circuit. Moreover, when the voltage setting circuit receives external frequency data, it sets control voltage data to be preset in the VCO in the D/A conversion circuit. The control voltage VC of the VCO corresponding to a certain frequency f (
f) is the preset voltage from the D/A conversion circuit
If the control voltage of ST and PLL circuit is VPLL,

0
008]

[Math 3]

##EQU1## The VPLL is constant regardless of the frequency. In this way, if the control voltage of the VCO is set in the PLL circuit using a D/A conversion circuit, the output voltage of the loop filter will be controlled regardless of the change in the output frequency, as long as the control voltage vs. output frequency characteristic of the VCO does not change. VPLL remains unchanged. However, if the ambient temperature fluctuates significantly, the VC
The output frequency vs. control voltage characteristic of O changes. For this reason,
Even if the control voltage of the VCO is preset by the D/A conversion circuit, the output voltage of the loop filter will not be constant regardless of the frequency, and since VPLL depends on the frequency, VPLL (
f). In this case, the loop filter output voltage changes with frequency switching, making it impossible to perform frequency switching at high speed. To prevent this, the voltage setting circuit uses an A/D conversion circuit to monitor the output frequency versus control voltage characteristics of the VCO. The voltage setting circuit uses an A/D conversion circuit to read changes in the loop filter output voltage, and based on this result, D
Modify the data to be set in the /A conversion circuit so that the frequency can always be switched at high speed. A VCO like this
A method of compensating for changes in output frequency vs. control voltage characteristics has already been disclosed in Japanese Patent Application No. 1-273773. If a preset circuit for presetting the control voltage of the VCO is provided in the PLL circuit in this manner, the frequency can be switched at high speed. However, if there is a difference in conversion characteristics between the A/D conversion circuit and the D/A conversion circuit, the difference results in a compensation error for VCO characteristic fluctuations, making it impossible to switch the frequency at high speed over a wide temperature range. Furthermore, in consideration of miniaturization and lower power consumption, it is desirable to reduce the circuit scale of the preset circuit.

0010

A frequency synthesizer mounted on a mobile communication radio device must be small. For this reason, it is necessary to have a circuit configuration that is easy to integrate, but in the past, since the main circuits could not be digitized, it was difficult to integrate and the device could not be made compact. In addition, shortening the frequency switching time can be achieved by
This is realized with the configuration shown in FIG. 15, but if there is a difference in conversion characteristics between the A/D conversion circuit and the D/A conversion circuit,
There was a drawback that VCO characteristic fluctuations could not be compensated with high precision. Furthermore, as the speed of frequency switching increases, the circuit size increases, making it impossible to reduce the power consumption of the device.

[0011]

[Means for solving the problem] In order to solve the above problem, the phase comparison circuit is constructed from a counter circuit and a latch circuit and is digitized, and the loop filter connected to the subsequent stage is also constructed from a digital circuit. This is how it was done.

0012

[Operation] Therefore, since the phase comparator circuit and loop filter, which are the main circuits of the conventional frequency synthesizer, are digitized, the conventional A/D conversion circuit is no longer necessary. As a result, it is possible to eliminate compensation errors for VCO characteristic fluctuations caused by differences in conversion characteristics between the A/D conversion circuit and the D/A conversion circuit, and
High-speed frequency switching is always possible even if the characteristics of

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be explained below with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of the present invention. The difference from the conventional example shown in FIG. 12 is that the phase comparator circuit is composed of a counter circuit and a latch circuit 1, and the loop filter connected to the subsequent stage is digitalized. Further, in order to use the digital loop filter output as the control voltage of the VCO, a D/A conversion circuit is connected to the downstream of the digital loop filter. Note that the variable frequency divider circuit is the same as the conventional one. The operation of each circuit will be explained below, focusing on the digital phase comparator circuit. Digital phase comparison circuits have generally been used in the past as well. However, it had a semi-analog configuration in which the phase difference was expressed as a pulse width. On the other hand, the digital phase comparison circuit of this configuration shown in FIG. 1 is composed of a counter circuit and a first latch circuit. FIG. 2 shows the operation of the digital phase comparison circuit when an 8-bit counter is used as the counter. The counter counts the output pulses of the reference oscillation circuit and outputs the count result as 8-bit parallel data. The sawtooth signal in FIG. 2 represents an 8-bit count value, and to be more precise, it is a step-like sawtooth signal synchronized with the output pulse of the reference oscillation circuit. The maximum value of the count value is "255" since it is 8-bit data, and returns to "0" when the number of input pulses exceeds "255". Also, the count value of the counter is from "0" to "255".
The repetition period 1/fref for one round is as follows, where fCLK is the output frequency of the reference oscillation circuit, and m is the number of bits of the counter.

[0014]

[Math 4]

This corresponds to fref of the synthesizer shown in FIG. In the example of FIG. 2, the value of the 8-bit counter represents the phase in offset binary, which corresponds to the phase from +πrad to −πrad. Figure 2
represents the variable frequency divider circuit output and the reference phase φref, which is the counter output value, in a phase synchronized state. In the entire circuit, the rising edge of the variable frequency divider circuit output is the reference phase 0.
This is a negative feedback loop that matches rad. Detection of the phase difference between the reference phase φref, which is the count value of the digital phase comparison circuit, and the variable frequency divider circuit output is performed by latching the count value of the counter circuit with the variable frequency divider circuit output (Latch1). The synchronization process of the PLL circuit with this configuration is similar to that of a conventional synthesizer, and if an integral element is added to the digital loop filter, the PLL circuit
The circuit behaves as a secondary system, and the rise of the variable frequency divider circuit output coincides with the reference phase 0rad in a steady state. The frequency f0 in steady state is

[0016]

[Math 5]

It can be expressed as follows. The output of the digital phase comparison circuit described above is applied to a digital loop filter. If the digital loop filter is designed to have the same frequency characteristics as the analog loop filter of FIG. 14 in the frequency domain, the PLL circuit of FIG. 1 will operate in the same manner as the conventional example of FIG. 12. Note that a method for realizing the digital loop filter will be explained in detail in the following second embodiment. As described above, according to this embodiment, all parts except the VCO and the reference oscillation circuit can be digitized. On the other hand, since the capacitor inside a conventional analog loop filter must be on the order of microfarads, it is difficult to miniaturize it by using an IC.

Next, a second embodiment will be explained. This second embodiment relates to a method of supplying a timing signal necessary to a digital loop filter circuit, and its configuration is shown in FIG. The difference from FIG. 1 is that a timing circuit is provided after the variable frequency divider circuit, and this circuit supplies latch signals to the digital phase comparator circuit and the digital loop filter circuit. Next, a method for implementing a digital loop filter will be explained in comparison with an analog type loop filter. Conventionally, an analog loop filter used in a PLL frequency synthesizer has a configuration as shown in FIG. becomes a constant value,

[0019]

[Math 6]

It can be expressed as follows. A digital loop filter circuit is realized to have frequency characteristics similar to this. An embodiment of the digital loop filter circuit is shown in FIG. Integration of the filter input signal is performed by a digital adder circuit 2 and a latch circuit 2. Furthermore, in order to obtain a gain in the high frequency range of the filter, the digital addition circuit 3 adds the output of the latch 2, which is the integration result, and the filter input signal and outputs the result. Furthermore, the first and second weighting circuits are circuits that multiply the input value by K1 and K2, respectively. The transfer function F(s) of this filter is expressed as follows, assuming that the latch period of the second latch circuit is flatch2.

[0021]

[Math 7]

It can be expressed as follows. Therefore, K1, K2,
If flatch2 is selected appropriately, characteristics similar to those of an analog type filter can be achieved. Note that the latch 3 is provided to avoid outputting an uncertain signal during the carry signal propagation time of the digital adder circuit 3. The timing circuit supplies a latch signal to the phase comparator circuit and the loop filter described above. An example of the timing of these latch signals is shown in FIG. The timing circuit detects the rising edge of the output signal of the variable frequency divider circuit, and latches the phase immediately after this by the rising edge of Latch1. Next, Latch2 is output to the loop filter to perform integration, and finally the determined loop filter output is latched at Latch3. In the example of FIG. 5, the latch period of Latch2 is flatc
h2 is the same as the variable frequency divider circuit output frequency,
flatch2 can be selected to an appropriate value. Therefore, the digital loop timing is K1, K2, fl
By varying atch2, its characteristics can be set appropriately. If a timing circuit as described above is provided, a PLL can be configured using a digital loop filter as shown in FIG.

Next, a third embodiment will be explained. This embodiment relates to speeding up frequency switching in a PLL frequency synthesizer. An example of this is shown in FIG. This configuration differs from the conventional high-speed switching frequency synthesizer shown in FIG. 15 in that the PLL circuit is digitized, so the A/D conversion circuit provided at the input of the voltage setting circuit is eliminated. Additionally, a digital adder circuit is used to preset the VCO control voltage. In order to switch the frequency at high speed in this embodiment, the VCO control voltage is preset at the same time as the frequency division ratio N of the variable frequency divider circuit is changed, similar to the conventional high speed switching frequency synthesizer shown in FIG. Conventionally, the output of the voltage setting circuit and the output of the loop filter are added by an analog adder circuit and the added output is used as the VCO control voltage, but in this embodiment, the preset circuit includes a D/
Without an A conversion circuit, the digital value of the voltage setting circuit output is added to the digital loop filter output using a digital addition circuit, and the addition result is added to the VC using a D/A conversion circuit.
Convert to O control voltage. The VCO control voltage VC is as follows, assuming that the voltage setting circuit output is VPRST(f) and the digital loop filter output is VPLL.

[0024]

[Math. 8]

It is expressed as follows. Therefore, if VPRST(f) corresponding to the desired frequency is set, VPLL is constant regardless of the output frequency, and the frequency can be switched at high speed. Additionally, in order to monitor variations in the output frequency vs. control voltage characteristics of the VCO, the voltage setting circuit must monitor the loop filter output VPLL. While the voltage setting circuit of a conventional high-speed switching frequency synthesizer uses an A/D conversion circuit to monitor the loop filter output, in this embodiment, the loop filter output is a digital quantity, so the voltage setting circuit is To monitor loop filter output without using an A/D conversion circuit.

Next, a fourth embodiment of this synthesizer is shown in FIG. The difference from the third embodiment is that the output of the digital adder circuit 1 is input to the voltage setting circuit. As explained in the third embodiment, the change in VCO control voltage versus output frequency is determined by the digital loop filter output V
Monitor by measuring PLL. This monitoring can be similarly performed by measuring the output of the digital adder circuit. However, in this case, the digital adder circuit output becomes the control voltage VC of the VCO, so the VPLL is

[0027]

[Math. 9]

As shown in the following, it is necessary to subtract the voltage setting circuit output VPRST(f) from the measured value VC(f). Next, a fifth embodiment of this synthesizer is shown in FIG. This embodiment has a configuration in which a timing circuit is inserted into the output of the variable frequency divider circuit in the third embodiment. The timing circuit detects the rise or fall of the variable frequency divider output and supplies a latch signal to the digital phase comparison circuit and the digital loop filter. The operation of this timing circuit may be performed in the same manner as in the second embodiment.

Next, a sixth embodiment of this synthesizer is shown in FIG. The difference from the fifth embodiment is that the output of the digital adder circuit 1 is input to the voltage setting circuit. The digital loop filter output VPLL may be calculated in the same manner as in the third embodiment.

Next, a seventh embodiment of this synthesizer is shown in FIG. This embodiment has a configuration in which a reset control circuit is added to the embodiment of FIG. As described above, in order to switch the frequency at high speed, in the embodiment of FIG. 6, the voltage setting circuit presets the control voltage of the VCO in the D/A conversion circuit at the same time as setting the frequency division ratio of the variable frequency dividing circuit. However, the output frequency fluctuates during frequency switching due to the following reasons.

[0031] At the time of frequency switching, VC is applied to the D/A conversion circuit.
The control voltage of O is set, but the D/A conversion circuit requires time to set the input data and then convert it into an analog voltage value. This time is usually shorter than the reference frequency fref, and the output frequency reaches the desired frequency within this time. However, the phase of the output of the variable frequency divider circuit changes slightly over time. When this phase difference occurs, P
Since LL corrects this, the output frequency fluctuates. This phase difference increases in proportion to the frequency division ratio. Particularly in the case of mobile communications, the frequency division ratio is as large as 30,000 or more, so the phase difference at the time of frequency switching becomes a problem.

To solve this problem, a reset control circuit is provided to reset the variable frequency divider circuit when switching frequencies. In FIG. 10, the reset control circuit consists of a zero phase detection circuit and a pulse generation circuit. Next, the timing at the time of frequency switching is shown in FIG. When switching the frequency from f1 to f2, the frequency division ratio N and the D/A conversion circuit output voltage VP
Simultaneously with setting RST, the reset control circuit sends a reset signal to the variable frequency divider circuit. In this example, the variable frequency divider circuit is reset to the initial state by the "H" level of the reset signal, and is released from reset by the "L" level of the reset signal, and starts operating from the initial state. In FIG. 11, the time when the reset signal changes from the "H" level to the "L" level is synchronized with the time when the phase φref of the reference signal becomes zero. In this way, if the reset signal is synchronized with φref,
Variable frequency divider circuit output signal and reference signal φre when switching frequency
The phase difference of f can be made zero.

In the reset control circuit of FIG. 10, the zero phase detection circuit is a circuit that detects zero of φref. Such phase detection may be performed using, for example, a magnitude comparator. Furthermore, when the phase is expressed in offset binary as shown in FIG. 11, the time at which the most significant bit rises from "0" to "1" may be detected. The pulse generation circuit obtains the detection result of the zero phase detection circuit and changes the output signal from "H" to "L" as shown in Figure 1.
The reset signal shown in 1 can be generated. In this way, by providing the reset control circuit, it is possible to suppress frequency fluctuations caused by phase fluctuations during frequency switching, and it is possible to switch frequencies at high speed.

[0034]

[Effects of the Invention] As explained above, the present invention digitizes the main circuit of a frequency synthesizer, so
It is possible to realize circuit miniaturization by Also, conventionally, A/
A D conversion circuit was used, but with digitalization, A/
A D conversion circuit can be eliminated. This makes it possible to eliminate compensation errors for VCO characteristic fluctuations caused by differences in conversion characteristics between the A/D conversion circuit and the D/A conversion circuit. Furthermore, it is possible to suppress an increase in circuit scale due to faster frequency switching, and thus it is possible to reduce power consumption. As described above, the frequency synthesizer according to the present invention is suitable for mobile communication radio equipment that requires small size and low power consumption, and that requires high-speed frequency switching. Furthermore, mobile communication wireless devices are often used in environments with poor temperatures, and can operate stably even in such cases.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a frequency synthesizer according to the present invention.

FIG. 2 is a timing chart showing the operation of a phase comparator circuit that constitutes the frequency synthesizer.

FIG. 3 is a block diagram showing a second embodiment of the frequency synthesizer.

FIG. 4 is a block diagram of a digital loop filter that constitutes the frequency synthesizer.

FIG. 5 is a timing chart showing the operation of each part of the frequency synthesizer.

FIG. 6 is a block diagram showing a third embodiment of the frequency synthesizer.

FIG. 7 is a block diagram showing a fourth embodiment of the frequency synthesizer.

FIG. 8 is a block diagram showing a fifth embodiment of the frequency synthesizer.

FIG. 9 is a block diagram showing a sixth embodiment of the frequency synthesizer.

FIG. 10 is a block diagram showing a seventh embodiment of the frequency synthesizer.

FIG. 11 is a timing chart showing the operation of the reset control circuit of the frequency synthesizer.

FIG. 12 is a block diagram of a conventional frequency synthesizer.

FIG. 13 is a timing chart showing the operation of a phase comparator circuit that constitutes a conventional frequency synthesizer.

FIG. 14 is a circuit diagram of an analog loop filter whose component is a conventional frequency synthesizer.

FIG. 15 is a block diagram of a conventional fast switching frequency synthesizer.

[Explanation of symbols]

1 Reference oscillation circuit 4 Voltage controlled oscillation circuit (VCO) 5 Variable frequency divider circuit 15 Counter circuit 13 Voltage setting circuit 14 Frequency division ratio setting circuit 16, 23, 25 Latch circuit 17 Digital loop filter 18 D
/A conversion circuit 19 Timing circuits 20, 21 Weighting circuits 22, 24, 26 Addition circuit 27 Zero phase detection circuit 28 Pulse generation circuit

Claims (3)

[Claims] 1. A frequency synthesizer having a phase-locked loop that synchronizes the phase of an oscillation signal of a voltage-controlled oscillation circuit with the phase of an output signal of a reference oscillation circuit, wherein the voltage-controlled oscillation circuit oscillates at a predetermined frequency division ratio. A variable frequency divider circuit that divides a signal, a counter circuit that counts output signal pulses of the reference oscillation circuit, a latch circuit that holds the count value of the counter circuit with an output signal of the variable frequency divider circuit, and the latch circuit. a digital loop filter circuit that changes the output data of the digital loop filter circuit with time; and a digital loop filter circuit that converts the output of the digital loop filter circuit into an analog voltage value and uses the analog voltage value as the control voltage of the voltage controlled oscillation circuit.
A frequency synthesizer, comprising: an A conversion circuit and forming the phase-locked loop. 2. A frequency synthesizer having a phase-locked loop that synchronizes the phase of an oscillation signal of a voltage-controlled oscillation circuit with the phase of an output signal of a reference oscillation circuit, wherein the voltage-controlled oscillation circuit oscillates at a predetermined frequency division ratio. A variable frequency divider circuit that divides a signal, a counter circuit that counts output signal pulses of the reference oscillation circuit, a latch circuit that holds the count value of the counter circuit with an output signal of the variable frequency divider circuit, and the latch circuit. a digital loop filter circuit that changes output data over time; a digital addition circuit that takes the output of the digital loop filter circuit as one input; and a digital addition circuit that converts the output of the digital addition circuit into an analog voltage value. A D/A converter circuit that serves as a control voltage for the voltage controlled oscillation circuit, and a voltage setting that outputs voltage controlled oscillator control data corresponding to a desired oscillation frequency and applies this voltage controlled oscillator control data to the other input of the digital addition circuit. circuit, and a frequency division ratio setting circuit that generates a frequency division ratio of the variable frequency divider circuit corresponding to the desired oscillation frequency, the change in the relationship between the control voltage and the oscillation frequency in the voltage controlled oscillation circuit, A frequency synthesizer characterized in that the voltage setting circuit detects a change in the output of the digital loop filter circuit, and corrects the output of the voltage setting circuit by referring to the detection result. 3. The frequency synthesizer according to claim 2, further comprising a reset control circuit having a function of detecting a unique specific signal in the output signal of the counter circuit and resetting the variable frequency divider circuit, and The frequency division ratio of the variable frequency divider circuit and the control voltage set to the D/A conversion circuit are set, and the variable frequency divider circuit is reset by a reset signal output from the reset control circuit. A frequency synthesizer featuring: