JP3365389B2 - Evaluation circuit for PLL circuit and its evaluation method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is a PLL that simplifies measurement of lock-up time and trackability and improves accuracy.
The present invention relates to a circuit evaluation circuit and an evaluation method thereof.

[0002]

2. Description of the Related Art In recent years, with the remarkable development of mobile radio communication terminals represented by mobile phones, high-quality and high-performance PLL circuits are becoming more important as system clock oscillation sources for electronic equipment. In particular, in a device such as a communication device that is frequently turned on and off, a high-speed compatible PLL circuit, that is, a lock-up time that is a time until the oscillation frequency is stabilized, is provided in order to improve responsiveness to power-on. A short PLL circuit is required.

Further, in electronic equipment in which all devices operate in synchronization with rising or falling of the system clock, large noise is generated at the rising and falling of the system clock, and this noise is generated by other electronic equipment. Phenomenon that interferes with normal operation of EMI (EMI: Elec
There is concern about tro-Magnetic Interference. One of the measures against this EMI is spectrum modulation.
The spectrum modulation is a method of changing the frequency of the system clock of the device at a constant cycle (called a modulation frequency). Specifically, by inputting the modulated reference signal to the PLL circuit, the output oscillation signal is modulated, and the timing at which the device operates is shifted to disperse the frequency distribution of the noise and reduce the noise. Decrease peak value.

FIG. 6 shows the transition of the frequency of this spectrum modulation. In this figure, the reference system clock of 10 MHz is used as the modulation frequency λ between 9 MHz and 11 MHz.
Is modulated by. Usually, this modulation frequency λ is several kHz
Although the frequency is up to several tens of kHz, the number of cases where the modulation frequency λ is set higher is increasing recently. When the modulation frequency λ is set high, it is necessary to confirm whether or not the oscillation frequency of the PLL circuit follows the modulated and input reference signal.

[0005]

As described above, a high-performance and high-quality PLL circuit is required, and accordingly, there is a demand for a measuring device for evaluating the characteristics of the PLL circuit. Is increasing. However, there are few measuring instruments that sufficiently evaluate the characteristics of the PLL circuit. For example, conventionally, in the above-described measurement of the lock-up time T and the measurement of the trackability with respect to the input signal, an external measurement device such as an oscilloscope or a spectrum analyzer is connected to an arbitrary measurement point and the waveform is observed. It was done. However, since the voltage value and frequency inside the PLL circuit change even with slight heat fluctuations and vibrations, stable measurement results cannot be obtained by measurement with an external measurement device, and the credibility of the measurement values is low, There is a problem that the performance of the PLL circuit cannot be evaluated sufficiently.

The present invention has been made in view of such circumstances, and an object of the present invention is to provide an evaluation circuit and an evaluation method for a PLL circuit capable of easily and accurately evaluating the characteristics of the PLL circuit. Specifically, there is provided a PLL circuit evaluation circuit and an evaluation method capable of easily and accurately measuring the lock-up time T and the output followability of the PLL circuit when spectrum modulation is performed, without using an external measurement device. The purpose is to provide.

[0007]

[0008]

[0009]

[0010]

[0011]

[0012]

[Means for Solving the Problems] To achieve the above object
In a first aspect of the present invention, a first PLL circuit to which a reference signal is input, a modulation circuit that modulates the frequency of the reference signal, and a reference signal that is modulated by the modulation circuit are input. Second PLL circuit, first analog-digital conversion means for digitally converting the output signal of the low-pass filter of the first PLL circuit, and the second P-circuit.
Second analog to digital conversion of the output signal of the low-pass filter LL circuit - and the digital conversion means, said first analog - is the output of the digital converter - output and before Symbol second analog digital conversion means And a subtraction unit that subtracts the other of the outputs supplied from the output and outputs the subtracted value. According to a second aspect of the present invention, the reference signal is input to the first PLL circuit, the frequency of the reference signal is modulated, and the modulated reference signal is input to the second PLL circuit. PLL
The output signal of the low-pass filter of the circuit is digitally converted, the output signal of the low-pass filter of the second PLL circuit is digitally converted, and the digitally converted output signal of the first PLL circuit and the first output signal of the first PLL circuit are digitally converted. It is characterized in that one of the output signals of the two PLL circuits is subtracted from the other , and the operation result is output.

[0013]

DETAILED DESCRIPTION OF THE INVENTION An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a configuration of an evaluation circuit of a PLL circuit according to the first embodiment of the present invention. In the figure, a phase frequency comparison circuit (PFD: Phas
e Frequency Detection) 11 is supplied with the reference signal CLK input via the input terminal 1 and the feedback signal FB-CLK obtained by dividing the oscillation signal PO by the feedback divider circuit 15, and receives these signals CLK and FB. -Compare phase and frequency with CLK. Feedback signal FB- with respect to reference signal CLK
When the phase of CLK is advanced or the frequency is high, the comparison signal DN having a pulse width proportional to the phase difference and the frequency difference is output, and conversely, when the phase of the feedback signal FB-CLK is delayed or the frequency is low. Outputs a comparison signal UP having a pulse width proportional to the phase difference and the frequency difference.

The charge pump (CP) circuit 12 outputs a charge pump signal PC which is a corresponding DC signal in response to the supplied comparison signal UP / DN. The low pass filter (LPF) 13 is a charge pump signal PC.
Is smoothed and the loop response of the entire PLL circuit 10 is appropriately set to generate the oscillation control signal VCTRL.
The voltage controlled oscillator (VCO) 14 has an oscillation control signal VCT.
An oscillation signal PO having an oscillation frequency according to the magnitude of RL is output. The feedback division circuit (DIV) 15 divides the oscillation signal PO by a predetermined division ratio N to generate a feedback signal FB-CLK and supplies it to the phase frequency comparison circuit 11.

On the other hand, an analog-digital converter (AD
C) 16 converts the oscillation control signal VCTRL into a digital oscillation control signal VCTRL-D which is a digital value,
Output to the lock detection circuit 17. FIG. 2 shows the internal configuration of the lock detection circuit 17 described above. The lock detection circuit 17 is F
An IFO (First-in First-out) type memory, m
+1 registers 18 (m = 0,1,2,3 ...), m comparators 19 provided in the registers 18 of the first and subsequent stages in a 1: 1 correspondence, and a logic circuit 30. . Each register 18 outputs the digital oscillation control signal VCTRL-D held by itself to the register 18 of the next stage, and the digital oscillation control signal VC supplied from the previous stage.
The zero-stage register 18 which holds TRL-D and is empty stores the digital oscillation control signal VCTRL-D supplied from the analog-digital converter 16.

As a result, the digital oscillation control signal VCTRL-D stored in each register 18 is moved down by one stage and stored, and the register 18 of the 0th stage is newly supplied from the analog-digital converter 16. The generated digital oscillation control signal VCTRL-D is stored.

Further, the comparator 19 compares the digital oscillation control signal VCTRL-D input to the register 18 of the stage in which the comparator 19 is provided with the output digital oscillation control signal VCTRL-D, and they match each other. If the match signal MATCH is "H", the match signal MATCH is output. Logic circuit 3
0 is the match signal MATCH output from each comparator 19.
In response, the logical product of the outputs of these match signals MATCH is output as the lock detection signal MATCH ALL.

Next, the operation of the evaluation circuit of the PLL circuit having the above structure will be described with reference to FIG. FIG. 3 is a diagram showing a transition of the oscillation signal PO from the start of inputting the reference signal CLK. In the figure, in the area A (time t0 to t1), the PLL circuit 10 operates so as to bring the oscillation signal PO close to the target frequency. That is, since the feedback signal FB-CLK supplied to the phase frequency comparison circuit 11 has a lower frequency than the reference signal CLK input via the input terminal 1,
The phase frequency comparison circuit 11 outputs a comparison signal UP having a pulse width proportional to the phase difference and the frequency difference.

The charge pump circuit 12 outputs a charge pump signal PC having a voltage corresponding to the pulse width of the comparison signal UP supplied from the phase frequency comparison circuit 11, and the low-pass filter 13 has a charge pump signal PC or the like. And generates and outputs the oscillation control signal VCTRL. The voltage controlled oscillator 14 outputs an oscillation signal PO having an oscillation frequency according to the magnitude of the oscillation control signal VCTRL. As a result, the oscillation signal PO approaches the target frequency.

On the other hand, the oscillation control signal VCTRL is also supplied to the analog-digital converter 16, is digitally converted, and is supplied to the lock detection circuit 17 (see FIG. 2). The lock detection circuit 17 receives the supplied digital oscillation control signal VCTRL-D in the register 1 in the FIFO format.
Store in 8. Further, at this time point, in each register 18, the digital oscillation control signal VCTRL-D output from the register 18 at the previous stage and the digital oscillation control signal VCTRL-D held by itself are different,
The match signal MATCH, which is the output of the comparator 19, remains held at "L". As a result, the lock detection signal MA
The output of TCH ALL is also "L".

Next, by repeating the above operation,
When the oscillation signal PO approaches the target frequency, the reference signal CLK
And a feedback signal FB-C supplied from the feedback frequency dividing circuit 15.
The phase difference and frequency difference from LK are reduced, and the output of the phase frequency comparison circuit 11 is stabilized (locked). As a result, the oscillation control signal V which is the output of the low pass filter 13
CTRL is almost constant. As a result, the digital oscillation control signal VCTR supplied to the lock detection circuit 17
L-D has a substantially constant value.

The operation of the lock detection circuit 17 in this state will be described with reference to FIG. First, at time t10, the digital oscillation control signal VCTRL- whose values match each other.
When D is supplied to the comparator 19 provided in the first stage from the register 18 in the 0th stage and the register 18 in the first stage, the comparator 19 determines that these values match and outputs the match signal MATCH. To "H" and output.

Similarly, at time t20 ..., The digital oscillation control signal VCTRL having the same value as the value supplied last time.
When -D is continuously supplied to the lock detection circuit 17, these values are sequentially stored in the register 18 of each stage from the upper stage to the lower stage. As a result, the waveform of the coincidence signal MATCH, which is the output of the comparator 19, is sequentially output as “H” from the comparator 19 provided in the first stage to the comparator 19 provided in the lower stage, The match signal MATCH is supplied to the logic circuit 30. The logic circuit 30 determines the logical product of the supplied match signals MATCH and the lock detection signal MA.
Output as TCH ALL.

In this way, when the digital oscillation control signal VCTRL-D having the same value as the value supplied the previous time is continuously supplied to the lock detection circuit 17 m times, all the comparators 19 output "H". Certain match signals MATCH are output and these signals are supplied to the logic circuit 30.
The logic circuit 30 uses the lock detection signal MATCH AL
L is output as "H". As a result, the reference signal CLK
Lock input signal MA from the start of input (t0 in FIG. 3).
Time until TCH ALL becomes "H" (t in FIG. 3)
1) can be detected as the lockup time T.

In the evaluation circuit of the PLL circuit according to the present embodiment, the number of registers 18 in the lock detection circuit 17 is determined by the lock state determination standard (for example, when the lock frequency is ± 10% of the target frequency, the lock occurs). It can be arbitrarily set according to the state). In addition, P of the present embodiment
In the evaluation circuit of the LL circuit, the logic circuit 30 described above is used.
May output a voltage value corresponding to the total number of match signals MATCH which is “H”. For example, when it is set that 1V is output for the match signal MATCH which is “H”, the match signal M which is “H” is output from the two comparators.
When ATCH is input, 2V is output as the detection result. As described above, by outputting the voltage corresponding to the number of the match signals MATCH which is “H”, it is possible to check the current lock state in more detail.

Further, in the configuration of the lock detection circuit 17 in the present embodiment, the registers 18 and the comparator 19 in the second and subsequent stages are removed, and instead of the logic circuit 30, it is output from the comparator 19 in the first stage. Match signal MATC
A count circuit for counting the number of times H is continuously "H" is provided, and the lock detection signal MATCH ALL is output as "H" when the count value reaches a preset value. Good. The count value for determining the lock state described above can be arbitrarily determined by the determination standard of the locker state (for example, the lock state is set when the frequency reaches ± 10% of the target frequency).

It is also possible to remove the logic circuit 30 of the lock detecting circuit 17 and provide m terminals externally to judge each match signal MATCH externally, or without providing the lock detecting circuit 17. , The output of the analog-digital converter 16 may be managed by software.

Next, a second embodiment of the present invention will be described. The evaluation circuit of the PLL circuit according to the second embodiment is intended to measure the followability of the PLL circuit when spectrum modulation is performed. FIG. 5 shows the circuit configuration of the evaluation circuit of the PLL circuit according to the second embodiment. In this figure, the PL according to the first embodiment is
Elements common to those of the evaluation circuit of the L circuit (see FIG. 1) are designated by common reference numerals.

In the figure, the PLL in this embodiment
The evaluation circuit of the circuit is the first P to which the reference signal CLK is input.
A LL circuit 50, a PLL circuit 60 to which a reference signal CLK ′ that is spectrum-modulated by a spectrum modulation clock generator (SSCG) 20 is input,
An analog-digital converter (ADC1) 21 that converts the oscillation control signal VCTRL1 that is the output of the low-pass filter 13 in the L circuit 50 into a digital value, and an oscillation that is the output of the low-pass filter 13 in the PLL circuit 60. An analog-digital converter (ADC2) 22 for converting the control signal VCTRL2 into a digital value, and a difference between the digital control oscillation signals VCTRL1-D and VCTRL2-D supplied from the analog-digital converters 21 and 22 are output. And a subtractor 23.

The operation of the PLL circuit having the above configuration will be described. It should be noted that each block having the same reference numeral as that of the evaluation circuit (see FIG. 1) of the PLL circuit according to the first embodiment has the same operation, and thus its description is omitted. First,
The input terminal 1 is connected to the phase frequency comparison circuit 11 of the PLL circuit 50.
When the reference signal CLK is input via the, the phase frequency comparison circuit 11 and the charge pump circuit 12 output arbitrary signals, and the low pass filter 13 generates the oscillation control signal VCTRL1 based on these signals. . The oscillation control signal VCTRL1 is digitally converted by the analog-digital converter 21 and supplied to the subtractor 23.

On the other hand, the phase frequency comparison circuit 11 of the PLL circuit 60 is supplied with a modulation reference signal CLK 'obtained by modulating the above-mentioned reference signal CLK with an arbitrary modulation frequency by the spectrum modulation clock generator SSCG (see FIG. 6). . The phase frequency comparison circuit 11 uses the modulation reference signal C
Feedback signal FB supplied from LK 'and feedback divider circuit 15
-Compare the phase and frequency with CLK and output the comparison signal UP or DN. The charge pump circuit CP outputs a charge pump signal PC based on the supplied comparison signal, and the low pass filter 13 generates an oscillation control signal VCTRL2 based on these signals. Oscillation control signal V
The CTRL 2 is converted into a digital value by the analog-digital converter 22 and supplied to the subtractor 23.

As a result, the subtractor 23 supplies the digital oscillation control signal VCT from the analog-digital converter 21.
RL1-D and the digital oscillation control signal VCTRL2-D from the analog-digital converter 22 are supplied. The subtractor 23 calculates the difference between the supplied two values and outputs it.

Here, the PLL circuit 60 causes the modulation reference signal C
If LK is followed, the digital oscillation control signal VCTRL2-D of the PLL circuit 60 has a value different from that of the digital oscillation control signal VCTRL1-D, so the subtractor 23
Output is not "zero".

However, when the spectrum clock modulation generator 20 modulates the reference signal CLK with a high modulation frequency λ and supplies it to the PLL circuit 60, the PLL circuit 60 cannot support the modulation reference signal CLK '. As a result, P
The oscillation signal PO of the LL circuit 60 has the same frequency as the oscillation signal PO of the PLL circuit 50, even though the modulated signal is input. In this case, PL
Since the oscillation control signal VCTRL1 in L50 and the oscillation control signal VCTRL2 in the PLL circuit 60 have the same value, the values of the digital oscillation control signal VCTRL1-D and the digital oscillation control signal VCTRL2-D obtained by digitally converting this value are naturally obtained. Becomes the same value, and the subtractor 23 outputs "zero" as the calculation result. Thus, when the detection result of the subtractor 23 becomes zero, it can be confirmed that the PLL circuit 60 cannot follow the modulation frequency λ at that time.

As described above, the calculation result of the subtractor 23
By evaluating the
The wave number λ can be obtained. In addition, in the evaluation circuit of the PLL circuit, the measurement is performed after the PLL circuit 50 is completely locked up. The modulation frequency λ of the spectrum modulation clock generator 20 is programmable and can be set arbitrarily. Modulation frequency λ
If it is configurable, the spectrum modulation clock generator
The modulation frequency λ set in the transmitter (SSCG) 20 is gradually increased.
, And confirm the calculation result of the subtractor 23 each time.
By doing so, the followability of the PLL circuit can be evaluated.
Can . Further, the subtractor 23 can mask the lower several bits in consideration of the error. At this time, the number of bits to be masked can be arbitrarily set according to the design target of the oscillation control voltage VCTRL. It is assumed that the PLL circuit evaluation circuits according to the first and second embodiments are all built in the same chip.

[0036]

[0037]

[0038]

[0039]

[0040]

[0041]

As described above, the PLL circuit of the present invention is used.
According to the path evaluation circuit , the first P
An LL circuit, a modulation circuit for modulating the frequency of the reference signal, a second PLL circuit to which the reference signal modulated by the modulation circuit is input, and an output signal of the low-pass filter of the first PLL circuit are digitally converted. First analog to do-
Digital conversion means, second analog-digital conversion means for converting the output signal of the low-pass filter of the second PLL circuit to digital, output of the first analog-digital conversion means, and second analog-digital conversion Means for subtracting the other from one of these outputs and outputting its value. This makes it possible to easily and accurately observe and evaluate the followability of the PLL circuit with respect to frequency modulation.

[Brief description of drawings]

FIG. 1 is a block diagram showing an evaluation circuit of a PLL circuit according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing an internal configuration of a lock detection circuit 17 of FIG.

FIG. 3 is a diagram for explaining a lockup time of a PLL circuit.

FIG. 4 is a diagram showing an output waveform of a comparator 19 in the lock detection circuit 17 in the same embodiment.

FIG. 5 is a block diagram showing an evaluation circuit of a PLL circuit according to a second embodiment of the present invention.

FIG. 6 is a diagram for explaining spectrum modulation.

[Explanation of symbols]

11 Phase Frequency Comparison Circuit 13 Low-Pass Filter 14 Voltage Controlled Oscillator 15 Feedback Frequency Dividing Circuits 16, 21, 22 Analog-Digital Converter (Analog-Digital Converter) 17 Lock Detection Circuit (Lock Detection Means) 18 Register (Latch) 19 Comparator (Comparison Means) 20 Spectral Modulation Clock Generator (Modulation Circuit) 23 Subtractor (Subtraction Means) 30 Logic Circuit (Determination Means) 50 PLL Circuit (First PLL Circuit) 60 PLL Circuit (Second PLL Circuit)

Claims (2)

(57) [Claims] 1. A first PLL circuit to which a reference signal is input, a modulation circuit to modulate the frequency of the reference signal, and a second PLL circuit to which the reference signal modulated by the modulation circuit is input. First analog-digital conversion means for converting the output signal of the low pass filter of the first PLL circuit into digital form, and second analog for converting the output signal of the low pass filter of the second PLL circuit into digital form. - a digital conversion means, said first analog - output of the digital conversion means and the previous SL second analog - output and a digital converting means is supplied, the other is subtracted from one of these outputs, outputs the value An evaluation circuit for a PLL circuit, comprising: 2. A reference signal is input to a first PLL circuit, the frequency of the reference signal is modulated, the modulated reference signal is input to a second PLL circuit, and the low frequency band of the first PLL circuit is input. The output signal of the pass filter is digitally converted, the output signal of the low pass filter of the second PLL circuit is digitally converted, and the digitally converted output signal of the first PLL circuit and the second PLL circuit are converted. Output signal from one to the other
The method for evaluating a PLL circuit is characterized by subtracting one of the two and outputting the calculation result.