JP2001237696A - Circuit and method for evaluating pll circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a circuit and a method for evaluating a PLL circuit, with which the characteristics of a PLL circuit can be easily and accurately measured. SOLUTION: A low-pass filter 13 generates an oscillation control signal VCTRL on the basis of an output from a charge pump circuit 12. An analog/ digital converter 16 converts the supplied oscillation control signal VCTRL to a digital oscillation control signal VCTRL-D and supplies it to a lock detecting means 17. The lock detecting means 17 compares the supplied digital oscillation control signal with a digital oscillation control signal supplied the last time and when these values match continuously (m) times, a lock detecting signal MATCH ALL is turned to 'H' and outputted. As a result, the time from the input start of a reference signal CLK to the time when the lock detecting signal MATCH ALL is turned to 'H', can be detected as lock-up time T.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL which simplifies the measurement of lock-up time and follow-up performance and improves the accuracy.
The present invention relates to a circuit evaluation circuit and an evaluation method thereof.

[0002]

2. Description of the Related Art In recent years, with the remarkable development of mobile radio communication terminals typified by mobile phones, the importance of high-quality, high-performance PLL circuits as a system clock oscillation source of electronic equipment has been increasing. In particular, in a device that is frequently turned on and off such as a communication device, a PLL circuit corresponding to a high speed in order to improve responsiveness to power-on, that is, a lock-up time, which is a time until the oscillation frequency is stabilized, is required. Short PLL circuits are required.

Also, in electronic equipment in which all devices operate in synchronization with the rise or fall of the system clock, large noise is generated when the system clock rises or falls, and this noise is generated by other electronic equipment. Phenomenon that prevents normal operation (EMI: Elec
tro-Magnetic Interference). One of the EMI measures is spectrum modulation.
The spectrum modulation is a method of changing the frequency of a system clock of a device at a constant cycle (called a modulation frequency). Specifically, by inputting the modulated reference signal to the PLL circuit, the output signal of the PLL circuit is modulated, and the operation timing of the device is shifted, thereby dispersing the frequency distribution of noise and dispersing the noise. Decrease peak value.

FIG. 6 shows a transition of the frequency of the spectrum modulation. In this figure, a reference system clock of 10 MHz is set to a modulation frequency λ between 9 MHz and 11 MHz.
Is modulated. Usually, this modulation frequency λ is several kHz.
To several tens of kHz, but recently, the case where the modulation frequency λ is set higher is increasing. When the modulation frequency λ is set high, it is necessary to check whether the oscillation frequency of the PLL circuit follows a reference signal that is modulated and input.

[0005]

As described above, a high-performance and high-quality PLL circuit has been demanded, and accordingly, the demand for measuring equipment for evaluating the characteristics of the PLL circuit has been increasing. Is growing. However, there are few measuring instruments for sufficiently evaluating the characteristics of the PLL circuit. For example, conventionally, the above-described measurement of the lock-up time T and the measurement of the follow-up property to the input signal are performed by connecting an external measurement device such as an oscilloscope or a spectrum analyzer to an arbitrary measurement point and observing a waveform. It was done. However, since the voltage value and frequency inside the PLL circuit change even with slight heat fluctuations and vibrations, stable measurement results cannot be obtained by measurement using an external measurement device, and the reliability of the measurement values is low. There is a problem that the performance of the PLL circuit cannot be sufficiently evaluated.

The present invention has been made in view of such circumstances, and an object of the present invention is to provide a PLL circuit evaluation circuit and an evaluation method capable of easily and accurately evaluating the characteristics of a PLL circuit. Specifically, there is provided a PLL circuit evaluation circuit and an evaluation method capable of easily and accurately measuring the lock-up time T and the followability of the output of the PLL circuit when spectrum modulation is performed without using an external measurement device. The purpose is to provide.

[0007]

In order to achieve the above object, the present invention provides a feedback frequency divider which divides an oscillation signal at an arbitrary frequency division ratio and supplies it to a phase comparison circuit; A phase comparison circuit that compares a phase with a feedback signal supplied from a frequency divider and outputs a phase difference signal; a low-pass filter that smoothes and outputs a signal from the phase comparison circuit; A voltage controlled oscillator for outputting the oscillation signal oscillating at a frequency corresponding to the signal output from the filter, analog-digital conversion means for converting the signal from the low-pass filter to a digital value, and the analog-digital conversion Lock detecting means for detecting a lock state based on output data of the means.

[0008] The invention described in claim 2 is the first invention.
Wherein the lock detecting means determines whether or not the output data of the analog-to-digital conversion means matches the previous output data, and sets the number of times that it is determined that the output data matches with the previous output data. The lock state is detected when the number of times has been continued.

[0009] The invention described in claim 3 is the first invention.
3. The PLL circuit evaluation circuit according to claim 2, wherein the lock detection unit includes a first-in first-out storage unit including a plurality of latches that operate based on the reference signal, and each of the latches except the first-stage latch. And comparing means for comparing the input and output values of the latch and outputting a coincidence signal when these values coincide with each other, and determining the locked state based on the output of the comparing means. Determining means.

[0010] The invention described in claim 4 is the invention according to claim 3.
In the evaluation circuit for a PLL circuit described in (1), the determination means outputs a logical product of outputs of the comparison means. Further, according to a fifth aspect of the present invention, in the PLL circuit evaluation circuit according to the third aspect, the determining means includes:
The comparison circuit detects a total number of coincidence signals.

According to a sixth aspect of the present invention, there is provided a feedback frequency divider for dividing an oscillation signal at an arbitrary frequency division ratio and supplying the divided signal to a phase comparator, a reference signal and a feedback signal supplied from the feedback frequency divider. A phase comparison circuit that compares a phase with a feedback signal to output a phase difference signal, a low-pass filter that smoothes and outputs a signal from the phase comparison circuit, and a signal that is output from the low-pass filter. And a voltage-controlled oscillator that outputs the oscillation signal oscillating at a frequency corresponding to the following: a signal from the low-pass filter is converted into a digital value, and the digital value matches the previous digital value. It is characterized in that the locked state is detected when the number of times that it is determined that these digital values match each other continues for a preset number of times.

Further, according to the present invention, a first PLL circuit to which a reference signal is inputted, a modulation circuit for modulating the frequency of the reference signal, and a reference signal modulated by the modulation circuit are inputted. A second PLL circuit, first analog-digital conversion means for converting the output signal of the low-pass filter of the first PLL circuit into a digital signal, and an output of the low-pass filter of the second PLL circuit. A second analog-to-digital converter for converting a signal into a digital signal, an output of the first analog-to-digital converter, and an output of the second analog-to-digital converter are supplied. And a subtraction means for outputting. The invention according to claim 8 is such that a reference signal is inputted to a first PLL circuit, a frequency of the reference signal is modulated, the modulated reference signal is inputted to a second PLL circuit, and the first PLL circuit is inputted to the first PLL circuit. Digitally converts the output signal of the low-pass filter of the PLL circuit, converts the output signal of the low-pass filter of the second PLL circuit into a digital signal, and converts the digitally converted first PL signal.
The output signal of the L circuit and the output signal of the second PLL circuit are subtracted, and the result of the operation is output.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a configuration of an evaluation circuit of a PLL circuit according to a first embodiment of the present invention. In the figure, a phase frequency comparison circuit (PFD: Phas
e Frequency Detection) 11 receives the supply of the reference signal CLK input via the input terminal 1 and the feedback signal FB-CLK obtained by dividing the oscillation signal PO by the feedback frequency divider 15, and these signals CLK and FB -Compare phase and frequency with CLK. The feedback signal FB-
When the phase of CLK is advanced or the frequency is high, a comparison signal DN having a pulse width proportional to the phase difference and the frequency difference is output. Conversely, when the phase of the feedback signal FB-CLK is delayed or the frequency is low Outputs a comparison signal UP having a pulse width proportional to the phase difference and the frequency difference.

The charge pump (CP) circuit 12 outputs a corresponding charge pump signal PC which is a DC signal in response to the supplied comparison signal UP / DN. The low-pass filter (LPF) 13 outputs the charge pump signal PC
And the loop response of the entire PLL circuit 10 is appropriately set to generate the oscillation control signal VCTRL.
The voltage controlled oscillator (VCO) 14 receives an oscillation control signal VCT
An oscillation signal PO having an oscillation frequency corresponding to the magnitude of RL is output. The feedback frequency dividing circuit (DIV) 15 divides the oscillation signal PO by a predetermined frequency dividing ratio N, generates a feedback signal FB-CLK, and supplies the feedback signal FB-CLK to the phase frequency comparing circuit 11.

On the other hand, an analog-digital converter (AD)
C) 16 converts the oscillation control signal VCTRL into a digital oscillation control signal VCTRL-D which is a digital value,
Output to the lock detection circuit 17. FIG. 2 shows the internal configuration of the lock detection circuit 17 described above. The lock detection circuit 17
This is an IFO (First-in First-out) format memory.
+1 registers 18 (m = 0, 1, 2, 3,...), M comparators 19 provided in a 1: 1 correspondence with the registers 18 in the first and subsequent stages, and a logic circuit 30 . Each register 18 outputs the digital oscillation control signal VCTRL-D held by itself to the register 18 at the next stage, and outputs the digital oscillation control signal VC
The zero-stage register 18 that has held TRL-D and emptied stores the digital oscillation control signal VCTRL-D supplied from the analog-digital converter 16.

As a result, the digital oscillation control signal VCTRL-D stored in each register 18 is stored one step down, and is newly supplied from the analog-digital converter 16 to the register 18 at the 0th stage. The stored digital oscillation control signal VCTRL-D is stored.

The comparator 19 compares the digital oscillation control signal VCTRL-D input to the register 18 of the stage in which the comparator 19 is provided with the output digital oscillation control signal VCTRL-D, and agrees with each other. In this case, the match signal MATCH is set to "H" and output. Logic circuit 3
0 is the match signal MATCH output from each comparator 19
And outputs the logical product of the outputs of the coincidence signals MATCH as the lock detection signal MATCH ALL.

Next, the operation of the evaluation circuit of the PLL circuit having the above configuration will be described with reference to FIG. FIG. 3 is a diagram showing a transition of the oscillation signal PO from the start of input of the reference signal CLK. In the figure, in a region A (time t0 to t1), the PLL circuit 10 operates to bring the oscillation signal PO closer to the target frequency. That is, since the feedback signal FB-CLK supplied to the phase frequency comparison circuit 11 has a lower frequency than the reference signal CLK input via the input terminal 1,
The phase frequency comparison circuit 11 outputs a comparison signal UP having a pulse width proportional to the phase difference and the frequency difference.

The charge pump circuit 12 outputs a charge pump signal PC of a voltage corresponding to the pulse width of the comparison signal UP supplied from the phase frequency comparison circuit 11, and the low-pass filter 13 outputs a charge pump signal PC or the like. , And generates and outputs an oscillation control signal VCTRL. The voltage control oscillator 14 outputs an oscillation signal PO having an oscillation frequency according to the magnitude of the oscillation control signal VCTRL. As a result, the oscillation signal PO approaches the target frequency.

On the other hand, the oscillation control signal VCTRL is also supplied to an analog-digital converter 16, where it is converted into a digital signal and supplied to a lock detection circuit 17 (see FIG. 2). The lock detection circuit 17 converts the supplied digital oscillation control signal VCTRL-D into a register 1 in a FIFO format.
8 is stored. At this point, the digital oscillation control signal VCTRL-D output from the register 18 at the preceding stage is different from the digital oscillation control signal VCTRL-D held by the register 18 at each point.
The match signal MATCH, which is the output of the comparator 19, remains at "L". As a result, the lock detection signal MA
The output of TCH ALL is also "L".

Next, by repeating the above operation,
When the oscillation signal PO approaches the target frequency, the reference signal CLK
And a feedback signal FB-C supplied from the feedback frequency dividing circuit 15.
The phase difference and the frequency difference from LK become small, and the output of the phase frequency comparison circuit 11 is stabilized (locked). Thereby, the oscillation control signal V, which is the output of the low-pass filter 13,
CTRL is almost constant. As a result, the digital oscillation control signal VCTR supplied to the lock detection circuit 17
L-D is a substantially constant value.

The operation of the lock detecting circuit 17 in this state will be described with reference to FIG. First, at time t10, the digital oscillation control signal VCTRL-
When D is supplied to the comparator 19 provided in the first stage from the register 18 in the 0th stage and the register 18 in the first stage, the comparator 19 determines that these values match, and the match signal MATCH Is set to “H” and output.

Similarly, at time t20, the digital oscillation control signal VCTRL having the same value as the value supplied last time is
When −D is continuously supplied to the lock detection circuit 17, these values are stored in the register 18 of each stage in order from the upper stage to the lower stage. As a result, the waveform of the match signal MATCH, which is the output of the comparator 19, becomes “H” in order from the comparator 19 provided in the first stage to the comparator 19 provided in the lower stage, and is output. The match signal MATCH is supplied to the logic circuit 30. The logic circuit 30 converts the logical product of the supplied match signals MATCH into a lock detection signal MA.
Output as TCH ALL.

In this way, when the digital oscillation control signal VCTRL-D having the same value as the previously supplied value is continuously supplied to the lock detecting circuit 17 m times, all the comparators 19 become "H". A certain match signal MATCH is output, and these signals are supplied to the logic circuit 30.
The logic circuit 30 outputs the lock detection signal MATCH AL
L is output as "H". As a result, the reference signal CLK
From the input start (t0 in FIG. 3).
Time until TCH ALL becomes "H" (t in FIG. 3)
1) can be detected as the lock-up time T.

In the PLL circuit evaluation circuit of the present embodiment, the number of registers 18 in the lock detection circuit 17 is determined according to the lock condition determination standard (for example, when the target frequency becomes ± 10% of the target frequency, the lock state is determined). The state can be arbitrarily determined. In addition, P of the present embodiment
In the evaluation circuit of the LL circuit, the above-described logic circuit 30
May be output as a voltage value corresponding to the total number of coincidence signals MATCH which is “H”. For example, if it is set to output 1 V for the match signal MATCH that is “H”, the match signal M that is “H” is output from the two comparators.
When ATCH is input, 2V is output as a detection result. As described above, by outputting a voltage corresponding to the number of coincidence signals MATCH which is “H”, it is possible to check the current lock state in more detail.

Further, in the configuration of the lock detection circuit 17 in the present embodiment, the register 18 and the comparator 19 in the second and subsequent stages are removed, and the output from the comparator 19 in the first stage is substituted for the logic circuit 30. Match signal MATC
A count circuit for counting the number of times H is continuously "H" is provided, and when the count value reaches a preset value, the lock detection signal MATCH ALL is output as "H". Good. The count value for determining the above-described locked state can be arbitrarily determined according to the lock-a state determination standard (for example, a locked state when ± 10% of the target frequency is reached).

It is also possible to remove the logic circuit 30 of the lock detection circuit 17 and provide m terminals externally to judge each coincidence signal MATCH externally. , The output of the analog-digital converter 16 may be managed by software.

Next, a second embodiment of the present invention will be described. The evaluation circuit of the PLL circuit according to the second embodiment is intended to measure the followability of the PLL circuit when spectrum modulation is performed. FIG. 5 shows a circuit configuration of an evaluation circuit of the PLL circuit according to the second embodiment. In this figure, the PL according to the first embodiment is shown.
Elements common to those of the evaluation circuit of the L circuit (see FIG. 1) are denoted by the same reference numerals.

Referring to FIG.
The evaluation circuit of the circuit receives the first P to which the reference signal CLK is input.
A PLL circuit 60 to which a reference signal CLK ′ subjected to spectrum modulation by an LL circuit 50 and a spectrum modulation clock generator (SSCG) 20 is input;
An analog-to-digital converter (ADC1) 21 for converting an oscillation control signal VCTRL1 output from the low-pass filter 13 in the L circuit 50 into a digital value, and an oscillation output from the low-pass filter 13 in the PLL circuit 60. An analog-to-digital converter (ADC2) 22 for converting the control signal VCTRL2 to a digital value, and a difference between the digitally-controlled oscillation signals VCTRL1-D and VCTRL2-D supplied from the analog-to-digital converters 21 and 22 are output. And a subtracter 23.

The operation of the PLL circuit having the above configuration will be described. Note that the blocks having the same reference numerals as those of the evaluation circuit (see FIG. 1) of the PLL circuit according to the first embodiment have the same operation, and thus the description thereof will be omitted. First,
The input terminal 1 is connected to the phase frequency comparison circuit 11 of the PLL circuit 50.
When the reference signal CLK is input through the phase control circuit 11, the phase frequency comparison circuit 11 and the charge pump circuit 12 output arbitrary signals, and the low-pass filter 13 generates the oscillation control signal VCTRL1 based on these signals. . The oscillation control signal VCTRL1 is digitally converted by the analog-digital converter 21 and supplied to the subtracter 23.

On the other hand, a modulation reference signal CLK 'obtained by modulating the above-mentioned reference signal CLK at an arbitrary modulation frequency by the spectrum modulation clock generator SSCG is input to the phase frequency comparison circuit 11 of the PLL circuit 60 (see FIG. 6). . The phase frequency comparison circuit 11 calculates the modulation reference signal C
LK ′ and the feedback signal FB supplied from the feedback frequency dividing circuit 15
-Compare the phase and frequency with CLK and output comparison signal UP or DN. The charge pump circuit CP outputs a charge pump signal PC based on the supplied comparison signal, and the low-pass filter 13 generates an oscillation control signal VCTRL2 based on these signals. Oscillation control signal V
The CTRL 2 is converted into a digital value by the analog-digital converter 22 and supplied to the subtracter 23.

As a result, the digital oscillation control signal VCT from the analog-digital converter 21 is supplied to the subtractor 23.
RL1-D and a digital oscillation control signal VCTRL2-D from the analog-digital converter 22 are supplied. The subtracter 23 calculates the difference between the supplied values and outputs the result.

Here, the PLL circuit 60 outputs the modulation reference signal C
If LK is followed, the digital oscillation control signal VCTRL2-D of the PLL circuit 60 has a different value from the digital oscillation control signal VCTRL1-D.
Is not "zero".

However, when the spectrum clock modulation generator 20 modulates the reference signal CLK at a high modulation frequency λ and supplies it to the PLL circuit 60, the PLL circuit 60 cannot fully cope with the modulation reference signal CLK '. As a result, P
The oscillation signal PO of the LL circuit 60 has the same frequency as the oscillation signal PO of the PLL circuit 50 even though the modulated signal is input. In this case, PL
Since the oscillation control signal VCTRL1 in L50 and the oscillation control signal VCTRL2 in the PLL circuit 60 have the same value, the values of the digital oscillation control signal VCTRL1-D and the digital oscillation control signal VCTRL2-D obtained by digitally converting this value are naturally obtained. Have the same value, and the subtractor 23 outputs “zero” as the operation result. Thus, when the detection result of the subtractor 23 becomes zero, it can be confirmed that the PLL circuit 60 cannot follow the modulation frequency λ at that time.

In the evaluation circuit of the PLL circuit, the measurement is performed after the PLL circuit 50 is completely locked up. Further, it is assumed that the modulation frequency λ of the spectrum modulation clock generator 20 is programmable and can be set arbitrarily. Further, the subtracter 23 can mask the lower several bits in consideration of the error. At this time,
The number of bits to be masked can be set arbitrarily according to the design target of the oscillation control voltage VCTRL. The first
It is assumed that all the configurations of the PLL circuit evaluation circuit according to the second embodiment are built in the same chip.

[0036]

As described above, according to the PLL circuit evaluation circuit of the present invention, the feedback divider that divides the oscillation signal at an arbitrary division ratio and supplies the divided signal to the phase comparison circuit, A phase comparison circuit that compares the phase of the feedback signal supplied from the feedback frequency divider and outputs a phase difference signal; a low-pass filter that smoothes and outputs the signal from the phase comparison circuit; A voltage-controlled oscillator that outputs an oscillation signal oscillating at a frequency corresponding to the signal output from the filter, an analog-to-digital converter that converts a signal from the low-pass filter into a digital value, and an output of the analog-to-digital converter Lock detecting means for detecting a lock state based on data.

As a result, the pin of the external measuring instrument is directly connected to P
Since it is not necessary to connect to the measurement point of the LL circuit, it is possible to obtain an accurate value which does not reflect an external influence as a measurement value. As a result, a highly reliable measurement value is obtained, and it is possible to evaluate the characteristics of the PLL circuit with high accuracy. Further, since the measured value can be obtained as a digital value, there is an advantage that it is effective for data processing and the like. Further, it is possible to easily detect the locked state only by observing the output of the lock detecting means.

According to the second aspect of the present invention, the lock detecting means determines whether or not the output data of the analog-to-digital conversion means matches the previous output data. Since the locked state is detected when a predetermined number of consecutive times have occurred, it is possible to detect the point in time when the locked state is completely established. Further, since the number of times can be set arbitrarily according to the design target, it is possible to detect the lock state with an accuracy corresponding to the design target.

According to the third aspect of the present invention, the lock detecting means includes a first-in first-out type storing means comprising a plurality of latches operating based on the reference signal, and a lock detecting means other than the first-stage latch. A comparing unit that is provided corresponding to the latch, compares input and output values of the latch, and outputs a coincidence signal when the values match, and determines a lock state based on an output of the comparing unit Since the determination unit is provided, the locked state can be accurately detected without relying on a large external device, and the size of the measurement device can be reduced.

According to the fourth aspect of the present invention, since the judging means outputs the logical product of the outputs of the comparing means, it is very simple and accurate to observe only the output of the judging means. The effect that the lockup time can be measured can be obtained. According to the fifth aspect of the present invention, since the determination means detects the total number of coincidence signals of the comparison circuit, an effect is obtained that the locked state can be observed in more detail.

According to the present invention, the first PLL circuit to which the reference signal is input, the modulation circuit for modulating the frequency of the reference signal, and the reference signal modulated by the modulation circuit are input. A second PLL circuit, a first analog-to-digital converter for digitally converting an output signal of the low-pass filter of the first PLL circuit,
Second analog-digital conversion means for digitally converting the output signal of the low-pass filter of the PLL circuit;
An output of the first analog-to-digital converter and an output of the second analog-to-digital converter are supplied, and there is provided subtraction means for outputting a value obtained by subtracting these outputs. This makes it possible to easily and accurately observe the followability of the PLL circuit with respect to frequency modulation.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an evaluation circuit of a PLL circuit according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing an internal configuration of a lock detection circuit 17 of FIG.

FIG. 3 is a diagram for explaining a lock-up time of a PLL circuit.

FIG. 4 is a diagram showing an output waveform of a comparator 19 in the lock detection circuit 17 according to the first embodiment.

FIG. 5 is a block diagram illustrating an evaluation circuit of a PLL circuit according to a second embodiment of the present invention.

FIG. 6 is a diagram for explaining spectrum modulation.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 11 Phase frequency comparison circuit 13 Low-pass filter 14 Voltage controlled oscillator 15 Feedback frequency divider 16, 21, 22 Analog-digital converter (analog-digital conversion means) 17 Lock detection circuit (lock detection means) 18 Register (latch) Reference Signs List 19 comparator (comparison means) 20 spectrum modulation clock generator (modulation circuit) 23 subtracter (subtraction means) 30 logic circuit (judgment means) 50 PLL circuit (first PLL circuit) 60 PLL circuit (second PLL circuit)

Claims (8)

[Claims] 1. A feedback frequency divider which divides an oscillation signal by an arbitrary frequency dividing ratio and supplies it to a phase comparison circuit, and compares a phase of a reference signal with a phase of a feedback signal supplied from the feedback frequency divider. A phase comparison circuit that outputs a phase difference signal, and a low-pass filter that smoothes and outputs a signal from the phase comparison circuit; and the oscillation that oscillates at a frequency corresponding to the signal output from the low-pass filter. A voltage-controlled oscillator that outputs a signal; an analog-to-digital converter that converts a signal output from the low-pass filter into a digital value; and a lock that detects a lock state based on output data of the analog-to-digital converter. An evaluation circuit for a PLL circuit, comprising: detection means. 2. The method according to claim 1, wherein the lock detecting means is configured to output the analog signal.
It is characterized in that it is determined whether or not the output data of the digital conversion means matches the previous output data, and a lock state is detected when the number of times determined to match is continuous for a preset number of times. An evaluation circuit for a PLL circuit according to claim 1. 3. The lock detecting means is provided in correspondence with a first-in first-out type storage means comprising a plurality of latches which operate based on the reference signal, and each latch except the first-stage latch.
Comparing means for comparing the input and output values of the latch and outputting a coincidence signal when the values match, and determining means for judging a lock state based on the output of the comparing means. 3. The PLL circuit evaluation circuit according to claim 1, wherein: 4. The P according to claim 3, wherein said determining means outputs a logical product of outputs of said comparing means.
Evaluation circuit for LL circuit. 5. The PLL circuit evaluation circuit according to claim 3, wherein said determination means detects a total number of coincidence signals of said comparison circuit. 6. A feedback frequency divider which divides an oscillation signal by an arbitrary frequency division ratio and supplies the same to a phase comparison circuit, and compares a phase of a reference signal with a phase of a feedback signal supplied from the feedback frequency divider. A phase comparison circuit for outputting a phase difference signal, a low-pass filter for smoothing and outputting the signal from the phase comparison circuit, and the oscillation for oscillating at a frequency corresponding to the signal output from the low-pass filter. A PLL circuit having a voltage-controlled oscillator that outputs a signal. The PLL circuit converts a signal output from the low-pass filter into a digital value, and determines whether the digital value matches a previous digital value. A lock state is detected when the number of times determined that the digital values are identical to each other continues for a preset number of times.
Evaluation method of LL circuit. 7. A first PLL circuit to which a reference signal is inputted, a modulation circuit for modulating the frequency of the reference signal, a second PLL circuit to which a reference signal modulated by the modulation circuit is inputted, First analog-to-digital conversion means for digitally converting the output signal of the low-pass filter of the first PLL circuit; and second analog for digitally converting the output signal of the low-pass filter of the second PLL circuit. Digital conversion means, and an output of the first analog-digital conversion means and an output of the second analog-digital conversion means are supplied, and a subtraction means for outputting a value obtained by subtracting these outputs is provided. An evaluation circuit for a PLL circuit. 8. A reference signal is input to a first PLL circuit, a frequency of the reference signal is modulated, the modulated reference signal is input to a second PLL circuit, and a low frequency band of the first PLL circuit is Digitally converting the output signal of the pass filter, digitally converting the output signal of the low-pass filter of the second PLL circuit, and outputting the digitally converted output signal of the first PLL circuit and the second PLL circuit And the output signal of
An evaluation method of a PLL circuit, which outputs the operation result.