CN112383498B - Low-frequency clock compensation method and device, storage medium and terminal - Google Patents
Low-frequency clock compensation method and device, storage medium and terminal Download PDFInfo
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Abstract
A method and a device for compensating a low-frequency clock, a storage medium and a terminal are provided, wherein the method comprises the following steps: for each time interval in a plurality of time intervals, acquiring a synchronous estimation value in the time interval, and counting the sleep time in the time interval; eliminating abnormal values in the synchronous estimated values of the plurality of time intervals, and averaging the synchronous estimated values after the abnormal values are eliminated; calculating the frequency deviation of the low-frequency clock according to the average value, and compensating the frequency deviation; the synchronization estimation value in each time interval is an accumulated value of synchronization deviation in the time interval, and the low-frequency clock is a clock used in the sleep time. Therefore, the low-frequency clock used by the terminal can be accurately compensated in the DRX state and other states, the deviation of the low-frequency clock is reduced, and the performance of the terminal is improved.
Description
Technical Field
The present invention relates to the field of communications technologies, and in particular, to a method and an apparatus for compensating a low frequency clock, a storage medium, and a terminal.
Background
When the terminal enters a Low Power (Low Power) state such as a sleep state, a Discontinuous Reception (DRX) state, or the like, the terminal may use a clock (Low frequency clock for short) with a lower frequency than that during normal operation to provide timing synchronization of the terminal instead of the system clock, so as to obtain lower Power consumption. The DRX state can be further divided into a Connection DRX (C-DRX) state and an Idle DRX (I-DRX) state.
A typical low frequency clock is 32 kilohertz (KHz, abbreviated as K) clock. There are two common ways of generating a 32K clock: mode 1, frequency division is performed by a system 26M clock; mode 2, provided by a single 32K crystal. In any way, because the 32K clock obtained by the method is affected by temperature and the like, the frequency of the 32K clock dynamically has a certain deviation from the nominal frequency thereof and the frequency of the serving cell base station, so that indexes such as synchronous frequency offset in the DRX state are affected. The influence has time accumulation effect, if the time accumulation effect is not corrected, the time identification range and the frequency identification range are exceeded, and the terminal is seriously disconnected.
Therefore, a compensation mechanism for a low frequency clock is needed to compensate the low frequency clock used by the terminal in the DRX state or the like, so as to reduce the deviation of the low frequency clock and improve the terminal performance.
Disclosure of Invention
The technical problem to be solved by the invention is how to provide a compensation mechanism of a low-frequency clock, so as to compensate the low-frequency clock in DRX state and other states, reduce the deviation of the low-frequency clock and improve the performance of a terminal.
In order to solve the above problem, an embodiment of the present invention provides a method for compensating a low frequency clock, where the method includes: for each time interval in a plurality of time intervals, acquiring a synchronous estimation value in the time interval, and counting the sleep time in the time interval; removing abnormal values in the synchronous estimated values of the plurality of time intervals, and averaging the synchronous estimated values after the abnormal values are removed; calculating the frequency deviation of the low-frequency clock according to the average value, and compensating the frequency deviation; the synchronization estimated value in each time interval is an accumulated value of synchronization deviation in the time interval, and the low-frequency clock is a clock used in the sleep time.
Optionally, each time interval includes one or more DRX cycles, and the counting, after the sleep time in the time interval, further includes: and converting the synchronous estimated value in each time interval into a standard time unit so as to update the synchronous estimated value.
Optionally, the standard time unit includes one or more DRX cycles.
Optionally, the removing abnormal values from the synchronous estimated values of the plurality of time intervals, and averaging the synchronous estimated values after removing the abnormal values includes: respectively judging whether the synchronous estimated value in each time interval meets the preset threshold; deleting the synchronous estimated value with the negative judgment result, and averaging the undeleted synchronous estimated values to obtain the average value.
Optionally, the removing abnormal values from the synchronous estimated values of the plurality of time intervals, and averaging the synchronous estimated values after removing the abnormal values includes: step A, obtaining a current estimated value, wherein an initial value of the current estimated value is a synchronous estimated value in a first time interval of a plurality of time intervals; b, calculating a difference value between the current estimation value and a preset value, recording the difference value as a first threshold, calculating a sum value between the current estimation value and the preset value, and recording the sum value as a second threshold; step C, respectively judging whether the synchronous estimated value in each time interval is positioned between the first threshold and the second threshold; if the judgment result is yes, executing the step D, calculating the sum of the synchronous estimation value and the total estimation value in the time interval, taking the sum as a new total estimation value, and adding one to a counter, wherein the initial value of the total estimation value is zero, and the initial value of the counter is zero; step E, recording the current value of the counter and the current value of the total estimation value; step F, acquiring a synchronous estimation value in a second time interval of a plurality of time intervals as the current estimation value, skipping to the step B, and continuing to execute the steps B to E until the current estimation value traverses the synchronous estimation values in all the time intervals; step G, acquiring the current value of the total estimation value corresponding to the counter with the maximum current value; and step H, dividing the current value of the obtained total estimation value by the current value of the corresponding counter to obtain the average value.
Optionally, after the step G, the method further includes: comparing whether the obtained current value of the counter is greater than a quantity threshold value; if the comparison result is yes, jumping to the step H, and continuing to execute the step H; if the comparison result is negative, the method is ended.
Optionally, the calculating, according to the average value, a frequency offset of the low-frequency clock includes: calculating the frequency offset of the low-frequency clock according to the following formula: x = T ÷ Y; wherein, X is the frequency offset of the low frequency clock, T is the average value, and Y is the sleep time in a single time interval.
The embodiment of the invention also provides a compensation device of the low-frequency clock, which comprises: the synchronous estimated value acquisition module is used for acquiring a synchronous estimated value in each time interval in a plurality of time intervals and counting the sleep time in the time interval; the abnormal value eliminating module is used for eliminating abnormal values in the synchronous estimated values of the plurality of time intervals and averaging the synchronous estimated values after the abnormal values are eliminated; the compensation module is used for calculating the frequency deviation of the low-frequency clock according to the average value and compensating the frequency deviation; the synchronization estimation value in each time interval is an accumulated value of synchronization deviation in the time interval, and the low-frequency clock is a clock used in the sleep time.
Embodiments of the present invention further provide a storage medium, on which a computer program is stored, where the computer program is executed by a processor to perform any of the steps of the method.
The embodiment of the present invention further provides a terminal, which includes a memory and a processor, where the memory stores a computer program that can be executed on the processor, and the processor executes any one of the steps of the method when executing the computer program.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
the embodiment of the invention provides a compensation method of a low-frequency clock, which comprises the following steps: for each time interval in a plurality of time intervals, acquiring a synchronous estimation value in the time interval, and counting the sleep time in the time interval; removing abnormal values in the synchronous estimated values of the plurality of time intervals, and averaging the synchronous estimated values after the abnormal values are removed; calculating the frequency deviation of the low-frequency clock according to the average value, and compensating the frequency deviation; the synchronization estimation value in each time interval is an accumulated value of synchronization deviation in the time interval, and the low-frequency clock is a clock used in the sleep time. Compared with the prior art, in the scheme of the embodiment of the invention, the UE uses a plurality of time intervals as an observation window, eliminates abnormal values in the observation window, and calculates an average value, so that the state in the whole sleep cycle can be reflected better, and the reliability of clock compensation is ensured. According to the scheme, a hardware calibration circuit does not need to work, the power consumption of the hardware calibration circuit is reduced, and the Doppler effect does not need to be eliminated. And the synchronous estimated value of the sleep state directly reflects the timing condition of the low-frequency clock circuit in the low-power consumption state, so that direct compensation can be realized, and the accuracy of low-frequency clock compensation is improved.
Further, the terminal establishes a plurality of thresholds (a first threshold and a second threshold) for abnormal value judgment according to the sum and the difference between the synchronous estimated value and a preset value in each time interval of a single observation window, and selects the threshold which can reflect the synchronous estimated value in the observation window most so as to remove the abnormal value. Therefore, according to the actual situation of each observation window, a consistent threshold can be established to eliminate abnormal values.
Drawings
Fig. 1 is a schematic diagram of an operating clock of a terminal in different states according to the prior art;
FIG. 2 is a flowchart illustrating a method for compensating a low frequency clock according to an embodiment of the present invention;
FIG. 3 is a flowchart illustrating one embodiment of step S201 in FIG. 2;
fig. 4 is a schematic structural diagram of a compensation apparatus for a low frequency clock according to an embodiment of the present invention.
Detailed Description
As a background, a low frequency clock (for example, 32K clock) obtained in the prior art may have a certain deviation from its nominal frequency and a serving cell base station frequency dynamically, which may affect indexes such as a synchronization frequency offset in the DRX state. To this problem, the conventional solutions mainly include two kinds:
scheme 1, a hardware circuit calibration compensation scheme. That is, the 32K clock is calibrated and compensated by using a hardware circuit. In this solution, in order to improve the calibration accuracy, the number of 32K clocks (counter) in a long calibration time needs to be counted. Then, the deviation amount of the 32K clock from the timing clock is calculated to compensate for the 32K clock. In order to obtain relatively high precision, the calibration time of the hardware circuit is usually relatively long, the calibration time is from tens of milliseconds to hundreds of milliseconds, and the calibration time is generally configured to be a plurality of 32KHz clock cycles.
The hardware circuit firstly counts the number X of 26M clocks in the calibration time, and counts the number Y of 32K clocks in the calibration time, the number Y of 32K clocks is converted into Y1 according to the coefficient of 26 (M) ÷ 32.768 (K), and the difference between X and Y1 is compared, namely the 32K clock deviation. The hardware circuit will compensate the 32K clock based on this deviation.
In order to maintain the accuracy of the 32K clock in the DRX state, the hardware circuit scheme is generally required to be calibrated at least once in a plurality of DRX cycles, and the calibration hardware circuit operation of the hardware circuit during calibration causes extra power consumption. That is, scheme 1 has the disadvantages of long hardware calibration time, high power consumption, and the like.
In the scheme 2, the estimated frequency offset is used for calibration compensation, and the main method comprises the following steps:
after each DRX wakeup, the frequency offset is estimated using the currently received data, the estimated frequency offset being in effect the frequency offset for the 26M crystal. In sleep mode, a 32K circuit count is used, with the aim of trying to achieve the same effect as a 26M crystal count. The 32K circuit may thus be compensated using the frequency offset estimated after each DRX wake-up. However, the accuracy of the calibration compensation performed by scheme 2 is not high due to several problems:
1. it is necessary to eliminate the frequency offset due to the doppler effect. In the modern society, expressways and highways are increasingly popular, and high-speed scenes are more frequently appeared in our lives. At high speed, the doppler effect brings about a large frequency offset. In the scheme, the doppler shift needs to be eliminated, and the doppler shift calculated after waking up cannot completely reflect the doppler shift in the sleep process, which may cause deviation of frequency offset compensation.
2. The accuracy of the frequency offset estimation compensation value is not high. In the DRX state, the less the reception time in the awake state is, the better for power consumption. For example, in the current I-DRX typical scheme, there is only 1-2 frame reception time after each I-DRX wakeup. In the scheme 2, the current temperature of the received data frame after the DRX wakeup determines the current frequency offset to a great extent, and the temperature change in the whole I-DRX state cannot be reflected by using the frequency offset compensation, so that the accuracy of a compensation value is influenced.
3. Non-homology of frequency offset estimation. (1) use of an external 32K crystal: the frequency offset estimated at this time of the received data is that of the inner 26M crystal and is not homologous to the circumscribed 32K crystal. (2) use a 32K clock scheme divided by 26M: in order to reduce Power consumption, 26M in the I-DRX state performs a Low Power (Low Power) operation mode, which is not consistent with the frequency in the normal operation state. Referring to fig. 1, fig. 1 is a schematic diagram of an operating clock of a terminal in different states in the prior art. When the data is received in the I-DRX awake state, the frequency offset estimated by using the received data corresponds to the frequency offset in the state of the normal operating mode (at this time, the operating frequency is freq 1) of the 26M crystal. And when the I-DRX sleep state timing synchronization is carried out, the 26M crystal enters a low-power consumption working mode (the working frequency is freq2 at the moment). Therefore, the 32K clock in the low power consumption operating mode can be compensated only by performing correlation conversion on the frequency offset estimated in the normal operating mode.
In summary, the low-frequency clock compensation method in the prior art has the problems of long calibration time, high power consumption, low accuracy and the like.
To solve the above problem, an embodiment of the present invention provides a method for compensating a low frequency clock, including: for each time interval in a plurality of time intervals, acquiring a synchronous estimation value in the time interval, and counting the sleep time in the time interval; eliminating abnormal values in the synchronous estimated values of the plurality of time intervals, and averaging the synchronous estimated values after the abnormal values are eliminated; calculating the frequency deviation of the low-frequency clock according to the average value, and compensating the frequency deviation; the synchronization estimation value in each time interval is an accumulated value of synchronization deviation in the time interval, and the low-frequency clock is a clock used in the sleep time.
By the scheme, the low-frequency clock used by the terminal can be accurately compensated in states such as a DRX state, the deviation of the low-frequency clock is reduced, and the performance of the terminal is improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Referring to fig. 2, fig. 2 is a method for compensating a low frequency clock according to an embodiment of the present invention, the method includes the following steps:
step S201, for each time interval in a plurality of time intervals, acquiring a synchronous estimation value in the time interval, and counting the sleep time in the time interval;
the synchronous estimated value in each time interval is an accumulated value of synchronous deviation in the time interval, the low-frequency clock is a clock used in the sleep time, and the frequency of the low-frequency clock is different from the frequency of the clock in a normal working state.
The time interval is a preset time period. And monitoring a plurality of time intervals, and reflecting the state of the terminal in the whole sleep cycle. Optionally, the plurality of time intervals are consecutive time intervals.
The method shown in fig. 2 may be executed by a User Equipment (UE), and the UE calculates a synchronization deviation between the UE and the network side according to downlink received data. And calculating the accumulated value of the synchronization deviation in each time interval as the synchronization estimation value of the time interval. And the UE counts the time to enter the sleep state, i.e. the sleep time, in the time interval.
Step S202, removing abnormal values in the synchronous estimated values of the plurality of time intervals, and averaging the synchronous estimated values after removing the abnormal values;
the abnormal value is a value with too high or too low synchronization estimation value, the respective synchronization estimation values of a plurality of time intervals can be clustered, and the free value after clustering can be regarded as the abnormal value. The cause of the abnormal value may be that the UE is constantly in signal search and frequently wakes up when the UE is in a scene with poor communication signals.
The average value of the synchronization estimation values of a plurality of time intervals can be fit with the deviation situation of the low-frequency clock.
Step S203, calculating the frequency offset of the low-frequency clock according to the average value, and compensating the frequency offset;
and converting the average value of the synchronous estimated value into the frequency offset of the low-frequency clock through frequency offset conversion so as to compensate. The frequency offset conversion method and the compensation method may adopt the conventional scheme in the prior art.
Optionally, the low frequency clock is a 32K clock, etc.
In this embodiment, the UE uses a plurality of time intervals as an observation window, eliminates abnormal values therein, and calculates an average value, which can better reflect the state in the whole sleep cycle, so as to ensure the reliability of clock compensation. According to the scheme, a hardware calibration circuit does not need to work, the power consumption of the hardware calibration circuit is reduced, and the Doppler effect does not need to be eliminated. And the synchronous estimated value of the sleep state directly reflects the timing condition of the low-frequency clock circuit in the low-power consumption state, so that direct compensation can be realized, and the accuracy of low-frequency clock compensation is improved.
In one embodiment, each time interval includes one or more DRX cycles, and with reference to fig. 2, the counting in step S201 after the sleep time in the time interval further includes: and converting the synchronous estimated value in each time interval into a standard time unit so as to update the synchronous estimated value.
When the time intervals are counted according to the DRX period, after a plurality of synchronous estimated values of a plurality of time intervals in an observation window are obtained, the synchronous estimated values are uniformly converted to a standard unit time. I.e. the sleep time in a plurality of DRX periods is uniformly converted into the DRX period so as to calculate the average value of the estimated synchronization values.
Optionally, the standard time unit includes one or more DRX cycles, for example, the period of I-DRX is configured by the network, typically 1.28 seconds(s).
Optionally, each time interval includes one DRX cycle, and correspondingly, the standard time unit is one DRX cycle.
In an embodiment, with continuing reference to fig. 2, the step S201 of removing abnormal values from the estimated synchronization values of the time intervals and averaging the estimated synchronization values after removing abnormal values may include: respectively judging whether the synchronous estimated value in each time interval meets the preset threshold; deleting the synchronous estimation value with the judged result of no, and averaging the undeleted synchronous estimation values to obtain the average value.
The preset threshold is used for indicating whether the synchronous estimation value in each time interval is abnormal or not, and is measured by the preset threshold experiment. Therefore, whether the obtained multiple synchronous estimated values are abnormal or not can be directly judged through a preset threshold measured through experiments.
In an embodiment, referring to fig. 3, fig. 3 is a flowchart illustrating an embodiment of step S201 in fig. 2, where the step S201 eliminates an abnormal value in the synchronization estimation values of the time intervals, and averages the synchronization estimation values after the abnormal value is eliminated, and the method may specifically include:
step A, obtaining a current estimated value (irt [ n ]), wherein an initial value of the current estimated value is a synchronous estimated value in a first time interval of a plurality of time intervals;
the method comprises the steps of obtaining synchronous estimated values of a plurality of time intervals in an observation window one by one as current estimated values, wherein the current estimated value irt [ n ] represents the synchronous estimated value of the nth time interval, and the value of n is 1, 2. The value of the first time interval n is 1.
Step B, calculating the difference value between the current estimation value (irt [ n ]) and a preset value (irt _ th), recording the difference value as a first threshold (irt [ n ] -irt _ th), calculating the sum value of the current estimation value and the preset value, and recording the sum value as a second threshold (irt [ n ] + irt _ th);
the predetermined values are determined experimentally.
Step C, respectively judging whether the synchronous estimated value (irt [ x ]) in each time interval is positioned between the first threshold (irt [ n ] -irt _ th) and the second threshold (irt [ n ] + irt _ th);
and acquiring synchronous estimated values in n time intervals one by one, and recording the synchronous estimated values as irt [ x ], wherein the value of x is 1,2. Judging whether the value of irt [ x ] satisfies (irt [ n ] -irt _ th, irt [ n ] + irt _ th), if yes, judging the result in the step C is yes; otherwise, the judgment result in the step C is negative.
If yes, executing step D, calculating the Sum of the synchronous estimated value (Irt [ x ]) and the total estimated value (Sum _ Irt) in the time interval, taking the Sum as a new total estimated value (Sum _ Irt), and adding one to the counter (IrtTh _ Num); wherein an initial value of the total estimate value (Sum _ Irt) is zero and an initial value of the counter (IrtTh _ Num) is zero;
optionally, if the determination result in step C is negative, it is continuously determined whether the synchronization estimation value in the next time interval is located between the first threshold (irt [ n ] -irt _ th) and the second threshold (irt [ n ] + irt _ th) (not shown in fig. 3). That is, the next irt [ x ] is acquired, and whether the value of irt [ x ] satisfies (irt [ n ] -irt _ th, irt [ n ] + irt _ th) is determined.
Step E, recording the current value of the counter (IrtTh _ Num) and the current value of the total estimation value (Sum _ Irt);
that is, the Sum of Irt [ x ] when the value of Irt [ x ] satisfies (Irt [ n ] -Irt _ th, irt [ n ] + Irt _ th), that is, the current value of the total estimated value (Sum _ Irt), is obtained; and counts the satisfied irt x, i.e., the current value of the counter (irth _ Num).
Step F, acquiring a synchronous estimation value in a second time interval of a plurality of time intervals as the current estimation value (irt [ n ], wherein the value of n is 2), skipping to the step B, and executing the steps B to E again until the current estimation value (irt [ n ]) traverses the synchronous estimation values in all the time intervals;
when the value of n in Irt [ n ] is 1,2 and once, the current values of n groups of total estimated values (Sum _ Irt) and the current value of a counter (IrtTh _ Num) are obtained.
Step G, obtaining the current value of the total estimation value (Sum _ Irt) corresponding to the counter (IrtTh _ Num) with the maximum current value;
and step H, dividing the current value of the obtained total estimation value by the current value of the corresponding counter (IrtTh _ Num) to obtain the average value.
That is, the current value (Sum _ Irt) of the total estimated value of one set of the counter (irth _ Num) having the largest current value is selected from the current values of the n sets of total estimated values and the current value of the counter (irth _ Num). The group of average values is obtained by averaging the synchronous estimation values after the abnormal values are removed in step S202 in fig. 2.
Optionally, after the step G, the method further includes: comparing whether the current value of the acquired counter (IrtTh _ Num) is greater than a number threshold (Num _ th); if the comparison result is yes, jumping to the step H, and continuing to execute the step H; if the comparison result is negative, the method is ended.
The number threshold (Num _ th) is a preset number, and if the current value of the obtained counter (irth _ Num) is less than or equal to the number threshold, it indicates that the set of irt [ x ] values satisfy (irt [ n ] -irt _ th, irt [ n ] + irt _ th) that the number is too small, that is, irt [ x ] is too dispersed, the fluctuation of the synchronous estimation value of the observation window is large, and frequency offset compensation of a low-frequency clock is not performed.
In this embodiment, the terminal establishes a plurality of thresholds (a first threshold and a second threshold) for abnormal value determination by using the sum and the difference between the synchronization estimation value and the preset value in each time interval of a single observation window, and selects a threshold which can most reflect the synchronization estimation value in the observation window to perform abnormal value elimination. Therefore, according to the actual situation of each observation window, a consistent threshold can be established to eliminate abnormal values.
In one embodiment, referring to fig. 2 again, the step S203 of calculating the frequency offset of the low frequency clock according to the average value may be performed according to the following formula (1):
X＝T÷Y (1)
wherein, X is the frequency offset of the low frequency clock, T is the average value, and Y is the sleep time in a single time interval.
Optionally, the sleep time in each of the time intervals is counted by step S201 in fig. 2, and the sum of the sleep times in the time intervals is divided by the number of the time intervals to obtain a mean value of the sleep time in each of the time intervals, and the mean value can be used as the value Y.
Taking a 32K clock as an example, assuming that the current 32K clock is shifted by X parts per million (denoted as Xppm) and is clocked by Y seconds(s) using 32K, the theoretical synchronization shift T (unit: seconds) during this time is expressed by the following equation (2):
T＝X×10 -6 ×Y (2)
the synchronization deviation is obtained according to the formula (2), and the current 32K clock deviation can be reversely deduced according to the formula (1).
In a specific example, the low frequency clock is 32K, and assuming that a single observation window includes 8 time intervals, each time interval is a DRX cycle (expressed as cycle 1, cycle 2, \8230;, cycle 8), the standard unit time is an I-DRX cycle (1.28 seconds (s)) as an example, the preset value irt _ th for establishing the first threshold and the second threshold is 50, and the number threshold num _ th is 4. Table 1 shows the sleep time and synchronization estimates for 8 DRX cycles in an observation window:
TABLE 1
The synchronization estimation value in table 1 is converted to the standard time unit of 1.28S, and the synchronization estimation value corresponding to each DRX cycle can be expressed as the synchronization estimation value (TS) of 1.28S in table 2. Where TS is a basic unit defined in Long Term Evolution (LTE), 1TS =1 ÷ (15000 × 2048) =1/30720000 (sec).
The number of cycles in the range is determined based on the values of each cycle in table 1 one by one. For example, the estimated synchronization value in the first cycle is 181, and the preset value irt _ th is 50, so it will be determined whether the estimated synchronization value irt [ x ] (i is 1-8) in each DRX cycle is in the range of [ (181-50), (181 + 50) ]. If within this range, the counter IrtTh _ Num increments by 1 and simultaneously increments the total estimate (Sum _ Irt) (unit: TS).
TABLE 2
From table 2 above, it can be seen that the counter max _ irth _ Num =6, whose current value is the largest, is greater than the number threshold Num _ th for 32K offsets. Therefore, the average value irt _ ave =998 ÷ 6=166 (TS) can be obtained, and the corresponding timing deviation (frequency offset) =166 ÷ 30720 ÷ 1280=4.2 × 10 can be calculated -6 ＝4.2(ppm)。
The frequency offset obtained by the calculation can be used for compensating and correcting the 32K clock.
Referring to fig. 4, fig. 4 is a schematic structural diagram of a compensation apparatus for a low frequency clock according to an embodiment of the present invention, where the compensation apparatus 40 for a low frequency clock specifically includes:
a synchronization estimation value obtaining module 401, configured to obtain, for each time interval in a plurality of time intervals, a synchronization estimation value in the time interval, and count sleep time in the time interval;
an abnormal value removing module 402, configured to remove abnormal values from the synchronous estimated values of the multiple time intervals, and calculate an average value of the synchronous estimated values after removing the abnormal values;
a compensation module 403, configured to calculate a frequency offset of the low-frequency clock according to the average value, and compensate the frequency offset;
the synchronization estimated value in each time interval is an accumulated value of synchronization deviation in the time interval, and the low-frequency clock is a clock used in the sleep time.
In one embodiment, each time interval includes one or more DRX cycles, and after the sleep time in the time interval is counted in the synchronization estimation value obtaining module 401, the apparatus 40 for compensating the low frequency clock further includes:
and the conversion module is used for converting the synchronous estimation value in each time interval to a standard time unit so as to update the synchronous estimation value.
Optionally, the standard time unit includes one or more DRX cycles.
In one embodiment, the outlier culling module 402 may include:
the first judging unit is used for respectively judging whether the synchronous estimated value in each time interval meets the preset threshold;
and the eliminating unit is used for deleting the synchronous estimation value with the negative judgment result and averaging the undeleted synchronous estimation values to obtain the average value.
In another embodiment, the outlier culling module 402 may further include:
a starting unit, configured to execute step a, obtain a current estimated value, where an initial value of the current estimated value is a synchronous estimated value in a first time interval of a plurality of time intervals;
a threshold establishing unit, configured to execute step B, calculate a difference between the current estimation value and a preset value, and record the difference as a first threshold, and calculate a sum of the current estimation value and the preset value, and record the sum as a second threshold;
a second judging unit, configured to execute step C, and respectively judge whether the synchronization estimation value in each time interval is located between the first threshold and the second threshold;
an accumulation unit, configured to execute step D if the determination result is yes, calculate a sum of the synchronization estimation value and the total estimation value in the time interval, use the sum as a new total estimation value, and add one to a counter, where an initial value of the total estimation value is zero and an initial value of the counter is zero;
a recording unit for executing step E, recording a current value of the counter and a current value of the total evaluation value;
a loop unit, configured to execute step F, obtain a synchronization estimation value in a second time interval of the multiple time intervals as the current estimation value, skip to step B, and continue to execute steps B to E until the current estimation value traverses synchronization estimation values in all time intervals;
a total estimated value obtaining unit, configured to perform step G, obtain a current value of a total estimated value corresponding to the counter with the largest current value;
and the average value calculating unit is used for executing the step H and dividing the current value of the obtained total estimated value by the current value of the corresponding counter to obtain the average value.
In one embodiment, after the total estimated value obtaining unit performs step G, the outlier rejection module 402 further includes:
a comparison unit for comparing whether the obtained current value of the counter is greater than a quantity threshold value;
a continuous execution unit, configured to jump to step H and continue to execute step H if the comparison result is yes;
and the exit unit is used for ending the method if the comparison result is negative.
In one embodiment, the compensation module is further configured to: calculating the frequency offset of the low-frequency clock according to the following formula: x = T ÷ Y; wherein, X is the frequency offset of the low frequency clock, T is the average value, and Y is the sleep time in a single time interval.
For more details of the operation principle and the operation mode of the compensation apparatus 40 for low frequency clocks, reference may be made to fig. 2 and fig. 3 for the description of the compensation method for low frequency clocks, and details are not repeated here.
Embodiments of the present invention also provide a storage medium having a computer program stored thereon, where the computer program is executed by a processor to perform the steps of the method in any one of fig. 2 and 3. The storage medium may be a computer-readable storage medium, and may include, for example, a non-volatile (non-volatile) or non-transitory (non-transitory) memory, and may further include an optical disc, a mechanical hard disk, a solid state hard disk, and the like.
The embodiment of the invention also provides a terminal, which can be UE. The terminal may comprise a memory having stored thereon a computer program operable on the processor, and a processor that, when executing the computer program, performs the steps of the methods of fig. 2 and 3.
Specifically, in the embodiment of the present invention, the processor may be a Central Processing Unit (CPU), and the processor may also be other general purpose processors, digital Signal Processors (DSPs), application Specific Integrated Circuits (ASICs), field Programmable Gate Arrays (FPGAs) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, and the like. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
It will also be appreciated that the memory in the embodiments of the subject application may be either volatile memory or nonvolatile memory, or may include both volatile and nonvolatile memory. The nonvolatile memory may be a read-only memory (ROM), a Programmable ROM (PROM), an Erasable PROM (EPROM), an Electrically Erasable PROM (EEPROM), or a flash memory. Volatile memory can be Random Access Memory (RAM), which acts as external cache memory. By way of example and not limitation, many forms of Random Access Memory (RAM) are available, such as Static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchlronous DRAM (SLDRAM), and direct bus RAM (DR RAM).
It should be understood that the term "and/or" herein is merely one type of association relationship that describes an associated object, meaning that three relationships may exist, e.g., a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" in this document indicates that the former and latter related objects are in an "or" relationship.
The "plurality" appearing in the embodiments of the present application means two or more.
The descriptions of the first, second, etc. appearing in the embodiments of the present application are only for illustrating and differentiating the objects, and do not represent the order or the particular limitation of the number of the devices in the embodiments of the present application, and do not constitute any limitation to the embodiments of the present application.
The term "connect" in the embodiments of the present application refers to various connection manners, such as direct connection or indirect connection, to implement communication between devices, which is not limited in this embodiment of the present application.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected by one skilled in the art without departing from the spirit and scope of the invention, as defined in the appended claims.
Claims (7)
1. A method of compensating for a low frequency clock, the method comprising:
for each time interval in a plurality of time intervals, acquiring a synchronous estimation value in the time interval, and counting the sleep time in the time interval;
eliminating abnormal values in the synchronous estimated values of the time intervals, and averaging the synchronous estimated values after the abnormal values are eliminated, wherein the method comprises the following steps: step A, obtaining a current estimation value, wherein an initial value of the current estimation value is a synchronous estimation value in a first time interval in a plurality of time intervals; b, calculating a difference value between the current estimation value and a preset value, recording the difference value as a first threshold, calculating a sum value between the current estimation value and the preset value, and recording the sum value as a second threshold; step C, respectively judging whether the synchronous estimated value in each time interval is positioned between the first threshold and the second threshold; if the judgment result is yes, executing the step D, calculating the sum of the synchronous estimation value and the total estimation value in the time interval, taking the sum as a new total estimation value, and adding one to the counter; wherein the initial value of the total estimation value is zero, and the initial value of the counter is zero; step E, recording the current value of the counter and the current value of the total estimation value; step F, acquiring a synchronous estimated value in a second time interval in a plurality of time intervals as the current estimated value, skipping to the step B, and continuing to execute the step B to the step E until the current estimated value traverses the synchronous estimated values in all the time intervals; step G, acquiring the current value of the total estimation value corresponding to the counter with the maximum current value; step H, dividing the current value of the obtained total estimation value by the current value of the corresponding counter to obtain the average value; after step G, further comprising: comparing whether the obtained current value of the counter is greater than a quantity threshold value; if the comparison result is yes, jumping to the step H, and continuing to execute the step H; if the comparison result is negative, ending;
calculating the frequency deviation of the low-frequency clock according to the average value, and compensating the frequency deviation; calculating the frequency offset of the low-frequency clock according to the average value, including: calculating the frequency offset of the low-frequency clock according to the following formula: x = T ÷ Y; wherein, X is the frequency offset of the low-frequency clock, T is the average value, and Y is the sleep time in a single time interval;
the synchronous estimated value in each time interval is an accumulated value of synchronous deviation in the time interval, and the low-frequency clock is a clock used in the sleep time; each time interval includes one or more DRX cycles.
2. The method of claim 1, wherein the counting is after a sleep time in the time interval, further comprising:
and converting the synchronous estimated value in each time interval into a standard time unit so as to update the synchronous estimated value.
3. The method of claim 2, wherein the standard unit of time comprises one or more DRX cycles.
4. The method according to any one of claims 1 to 3, wherein the removing abnormal values from the synchronous estimation values of the plurality of time intervals and averaging the synchronous estimation values after removing abnormal values comprises:
respectively judging whether the synchronous estimated value in each time interval meets a preset threshold;
deleting the synchronous estimation value with the judged result of no, and averaging the undeleted synchronous estimation values to obtain the average value.
5. An apparatus for compensating a low frequency clock, the apparatus comprising:
a synchronization estimation value acquisition module, configured to acquire a synchronization estimation value in each of a plurality of time intervals, and count sleep time in the time interval;
the abnormal value eliminating module is used for eliminating abnormal values in the synchronous estimated values of the time intervals and averaging the synchronous estimated values after the abnormal values are eliminated, and comprises the following steps: step A, obtaining a current estimation value, wherein an initial value of the current estimation value is a synchronous estimation value in a first time interval in a plurality of time intervals; step B, calculating the difference value between the current estimation value and a preset value, recording the difference value as a first threshold, calculating the sum value between the current estimation value and the preset value, and recording the sum value as a second threshold; step C, respectively judging whether the synchronous estimated value in each time interval is positioned between the first threshold and the second threshold; if the judgment result is yes, executing the step D, calculating the sum of the synchronous estimation value and the total estimation value in the time interval, taking the sum as a new total estimation value, and adding one to the counter; wherein the initial value of the total estimation value is zero, and the initial value of the counter is zero; step E, recording the current value of the counter and the current value of the total estimation value; step F, acquiring a synchronous estimated value in a second time interval in a plurality of time intervals as the current estimated value, skipping to the step B, and continuing to execute the step B to the step E until the current estimated value traverses the synchronous estimated values in all the time intervals; step G, obtaining the current value of the total estimation value corresponding to the counter with the maximum current value; step H, dividing the current value of the obtained total estimation value by the current value of the corresponding counter to obtain the average value; after step G, further comprising: comparing whether the obtained current value of the counter is greater than a quantity threshold value; if the comparison result is yes, jumping to the step H, and continuing to execute the step H; if the comparison result is negative, ending;
the compensation module is used for calculating the frequency deviation of the low-frequency clock according to the average value and compensating the frequency deviation; calculating the frequency offset of the low-frequency clock according to the average value, including: calculating the frequency offset of the low-frequency clock according to the following formula: x = T ÷ Y; wherein, X is the frequency offset of the low-frequency clock, T is the average value, and Y is the sleep time in a single time interval;
the synchronous estimated value in each time interval is an accumulated value of synchronous deviation in the time interval, and the low-frequency clock is a clock used in the sleep time; each time interval includes one or more DRX cycles.
6. A storage medium having a computer program stored thereon, the computer program, when being executed by a processor, performing the steps of the method according to any one of claims 1 to 4.
7. A terminal comprising a memory and a processor, the memory having stored thereon a computer program operable on the processor, wherein the processor, when executing the computer program, performs the steps of the method of any of claims 1 to 4.
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| CN102540868B (en) * | 2010-12-31 | 2016-05-04 | 重庆重邮信科通信技术有限公司 | A kind of slow clock crystal frequency compensation method of mobile communication terminal and device |
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