CN104300969A - A high-precision synchronous clock realization method based on an all-digital phase-locked loop - Google Patents

Abstract

The invention discloses a high-precision synchronization clock realization method based on a full digital phase-locked loop. The method comprises the following steps: a phase discriminator makes a comparison between the phases of an input satellite source clock signal and an output synchronization clock signal and a phase difference signal is generated through a digital filter; a clock source state monitor monitors the work state of a satellite clock online; when the satellite clock is in a normal working mode, a pulse increase and decrease controller generates frequency division control coefficients of a frequency divider according to the phase difference output by the digital filter; when the satellite clock is in an out-of-step working mode, a self-correction controller generates frequency division control coefficients by utilizing the frequency division control coefficients before the failure of the satellite clock, current environment temperature and noise parameters; and the frequency divider generates high-precision synchronization clock output signals according to the frequency division control coefficients. The synchronization clock signal produced with the method has the advantages of small random errors and small accumulative errors, and can still keep high time service precision for a period after the failure of the satellite clock, and can provide accurate time synchronization second pulse signals for an electric system.

Description

A high-precision synchronous clock realization method based on an all-digital phase-locked loop

technical field

The invention relates to a method for realizing a synchronous clock, in particular to a method for realizing a high-precision synchronous clock based on an all-digital phase-locked loop.

Background technique

Domestic Beidou satellite navigation system and American global positioning system and other satellite timing systems (hereinafter collectively referred to as satellite clocks) can provide all-weather timing signals with high timing accuracy, and have good wide-area time synchronization performance, and are not restricted by geographical and climatic conditions. With the advantages of simple application and other advantages, it has been more and more applied in the fields of power system wide-area measurement and fault traveling wave location. The precise time synchronization technology based on satellite clock has attracted extensive attention.

However, when the satellite is out of lock, the second pulse error can reach tens of microseconds or even hundreds of microseconds; at the same time, the satellite clock signal will be subject to various electromagnetic interference during the propagation process, which may cause signal interruption in severe cases; its accuracy and stability It is difficult to meet the time synchronization requirements in protection monitoring and other fields. Therefore, when using the satellite clock as a wide-area time synchronization source, the reliability of the satellite clock signal must be considered, especially the time synchronization accuracy after the satellite clock fails.

The crystal oscillator clock has a large cumulative error and a small random error, while the error characteristics of the satellite clock are just the opposite, and the timing error characteristics of the two clocks are complementary. In order to ensure the accuracy and stability of the time synchronization system, experts and scholars have proposed a variety of timing schemes based on the complementary errors of satellite clocks and crystal oscillator clocks, such as using satellite clock signals to correct the cumulative error of crystal oscillator second pulses online and using high-precision crystal oscillators to monitor and correct satellites. Clock random errors, etc., have effectively improved the accuracy and stability of satellite clocks, but all existing solutions have shortcomings: large sample data, ignoring the frequency drift of the crystal oscillator, and complex calculations for compensation schemes.

In recent years, the phase-locked loop technology has been developed rapidly. The output signal of the phase-locked loop can automatically track the phase of the input signal to realize the closed-loop automatic control of the system. Due to the advantages of high reliability, strong anti-interference ability, small size, low price, easy integration, and simple peripheral circuits, the all-digital phase-locked loop solves many fundamental problems that are difficult to solve for analog loops, such as DC zero drift, device Saturation, sensitivity to temperature, necessary initial calibration, etc. The all-digital phase-locked loop technology is mature in the phase frequency measurement of the power grid, and has been widely used in the field of power systems. the

Contents of the invention

In order to meet the high-precision time synchronization requirements in the field of power system protection and control, and to maintain high stability and synchronization under the condition of effective and out-of-synchronization satellite clocks, the present invention provides a high-precision time synchronization based on an all-digital phase-locked loop. New method for synchronizing clocks. The invention utilizes the phase tracking advantage of the all-digital phase-locked loop, and based on the characteristics of complementary errors between the satellite clock and the crystal oscillator clock, proposes a timing scheme after the satellite clock fails; the invention can effectively improve the stability of the output clock.

The technical scheme that the present invention solves the problems of the technologies described above comprises the following steps:

(1) When the satellite clock is working normally, the phase detector compares the phases of the input satellite clock signal and the output synchronous clock signal, and generates an output signal that can represent the phase lead and lag relationship between the two;

(2) The digital filter performs noise filtering on the output signal of the phase detector, and generates a phase difference output signal according to the phase lead and lag: when the phase of the satellite clock signal is ahead, the output phase difference signal is up, and when the phase of the satellite clock signal is lagging , output phase difference signal down;

(3) The clock source status monitor monitors the working status of the satellite clock online. When the reception is normal, select the normal working mode, otherwise, select the out-of-synchronization working mode;

(4) In normal working mode, the pulse increase and decrease controller generates the frequency division control coefficient N of the frequency divider according to the phase difference output by the digital filter;

(5) In the out-of-step working mode, the self-calibration controller uses the frequency division control coefficient before the satellite clock fails, the current ambient temperature and noise parameters to generate the frequency division control coefficient N;

(6) The frequency divider divides the frequency of the crystal oscillator signal according to the frequency division control coefficient N to generate a high-precision synchronous clock output signal.

In the above-mentioned all-digital phase-locked loop high-precision synchronous clock method, in step (4), the pulse increase and decrease controller generates the frequency division control coefficient N of the frequency divider according to the phase difference output by the digital filter. The specific method is:

The pulse increase/decrease controller modulates the phase difference signal up into an effective down pulse, and the phase difference signal down into an effective up pulse; when the up pulse is valid, if the previous frequency division coefficient N _i-1 ≤ N _clk (N _clk is the frequency division coefficient corresponding to the standard second clock, and its value is equal to the crystal oscillator frequency), then N _i =N _i-1 +1, and implements lag correction for the next output synchronous clock signal; if the previous frequency division coefficient N _i-1 > N _clk , then N _i ＝N _i-1 , no correction will be made to the next output synchronous clock signal; when the down pulse is valid, if the previous frequency division coefficient N _i-1 ≥ N _clk , then N _i ＝N _{i- 1} -1, implement advanced correction for the next output synchronous clock signal; if the previous frequency division coefficient N _i-1 <N _clk , then N _i =N _i-1 , do not correct the next output synchronous clock signal; The judgment result N _i is latched and output to the frequency divider as the frequency division control coefficient for the next second.

In the above-mentioned all-digital phase-locked loop high-precision synchronous clock method, in step (5), the frequency division coefficient is adjusted in real time according to temperature changes and time changes to eliminate the influence of accumulated errors on the output synchronous clock signal, and the self-adaptive prediction model algorithm is used to Prediction produces frequency division control coefficient N. The cumulative error of the crystal oscillator (μ(t)) represents the time error accumulated between the output synchronous clock signal and the input satellite clock signal from the start time to the measurement time. The cumulative error of the crystal oscillator at time t _k can be expressed as:

(1)

The aging time of the crystal oscillator, measurement noise and temperature will affect the frequency stability. Since the aging rate of the crystal oscillator has very little effect on the frequency stability, in order to simplify the model, its influence is incorporated into the noise effect. Use α to represent the temperature sensitivity of crystal frequency stability, u(k) represents the crystal temperature measured by the temperature sensor at time t _k , y(k) represents the correction signal at time t _k , and v(k) represents the noise at time t _k . Then the cumulative error increased at time t _k can be expressed as:

(2)

Substitute formula (2) into formula (1) to get:

(3)

Assuming μ(t ₀ )=0, the frequency division control coefficient N at time t _k after the satellite clock fails is:

(4)

The technical effect of the present invention is: according to the characteristics of small cumulative errors of satellite clocks and small random errors of crystal oscillator clocks, a new method for realizing high-precision synchronous clocks in power systems based on all-digital phase-locked loops is proposed. In this method, when the satellite clock is working normally, the full digital phase-locked loop is used to make the crystal oscillator clock track the phase fluctuation of the second pulse of the satellite clock, and the cumulative error of the crystal oscillator clock is eliminated in real time; when the satellite clock fails, the frequency division control before the satellite clock fails is used Coefficients, current ambient temperature, and noise parameters, predict and correct cumulative error of the crystal oscillator clock. Simulation results show that the synchronous clock generated by this method has the advantages of small random error and small cumulative error. It can still maintain high timing accuracy during a period of time when the satellite clock fails, and can provide accurate time synchronization second pulse signals for power systems. .

The present invention will be further described below in conjunction with the accompanying drawings.

Description of drawings

Fig. 1 is a functional block diagram of an all-digital phase-locked loop synchronous clock;

Figure 2 is the clock error when the satellite clock is normal;

Fig. 3 is the clock error after the satellite clock fails.

Detailed ways

Figure 1 is a functional block diagram of an all-digital phase-locked loop synchronous clock. Referring to Figure 1, when the satellite clock is working normally, a phase detector is used to compare the phases of the input satellite clock signal and the output synchronous clock feedback signal to generate an output signal that can represent the phase lead and lag relationship between the two; The output signal of the phase device is processed by noise filtering, and a phase difference output signal is generated; the clock source status monitor monitors the working status of the satellite clock online, and when the reception is normal, select the normal working mode; otherwise, select the out-of-step working mode; The device judges the phase difference output by the digital filter to generate the frequency division control coefficient N of the frequency divider; when the self-calibration controller is in the out-of-step working mode, it uses the frequency division control coefficient before the satellite clock fails, the current ambient temperature And the noise parameter generates a frequency division control coefficient N; the frequency divider divides the frequency of the crystal oscillator signal according to the control coefficient N to generate and output a high-precision synchronous clock signal.

In order to verify the feasibility of a high-precision synchronous clock implementation method based on an all-digital phase-locked loop described in the present invention, use MATLAB to carry out simulation experiment verification, in order to improve the accuracy of the experiment, the clock used in the simulation is consistent with the actual clock as far as possible , where the random error of the satellite clock obeys a normal distribution with a mean value of zero, σ=50ns; the crystal oscillator frequency is 500MHz, the frequency accuracy is 10 ^-9 , and the frequency stability is 10 ^-11 (in practical applications, a 25MHz high-precision crystal oscillator can be selected, and after FPGA multiplied to 500MHz), assuming that the crystal oscillator temperature is constant at 50°C, and using high-frequency pulse signals to simulate noise interference. Use this 500MHz crystal oscillator as the local clock, and the satellite clock as the input clock, and use the above steps to get an accurate and stable output clock.

At the beginning of the experiment, the satellite clock was working normally, and the output clock was generated by using the frequency division coefficient output by the pulse increase and decrease controller. Output clock, the result is shown in Figure 3.

In Figure 2, μ _t is the random error value of the satellite clock, and μ _t ^' is the output clock error generated by the self-calibration controller simulation. It can be seen from the figure that the error estimated value curve is close to the real value curve, and the estimation effect is good, which proves the correctness of the above mathematical model. It can be seen from Figure 3 that the errors of the output clock gradually accumulate and increase.

It can be seen from the simulation results that the method described in this patent can comprehensively utilize the advantages of satellite clocks and crystal oscillator clocks to generate high-precision synchronous clocks with small cumulative errors and small random errors. In practical applications, in order to improve the clock accuracy after the satellite clock fails, the ambient temperature should be kept constant as much as possible so that the high-precision crystal oscillator has sufficient long-term stability.

Claims (3)

1. A method for realizing a high-precision synchronous clock based on an all-digital phase-locked loop, comprising the steps of: (1) When the satellite clock is working normally, the phase detector compares the phases of the input satellite clock signal and the output synchronous clock signal, and generates an output signal that can represent the phase lead and lag relationship between the two; (2) The digital filter performs noise filtering on the output signal of the phase detector, and generates a phase difference output signal according to the phase lead and lag: when the phase of the satellite clock signal is ahead, the output phase difference signal is up, and when the phase of the satellite clock signal is lagging , output phase difference signal down; (3) The clock source status monitor monitors the working status of the satellite clock online. When the reception is normal, select the normal working mode, otherwise, select the out-of-synchronization working mode; (4) In normal working mode, the pulse increase and decrease controller generates the frequency division control coefficient N of the frequency divider according to the phase difference output by the digital filter; (5) In the out-of-step working mode, the self-calibration controller uses the frequency division control coefficient before the satellite clock fails, the current ambient temperature and noise parameters to generate the frequency division control coefficient N; (6) The frequency divider divides the frequency of the crystal oscillator signal according to the frequency division control coefficient N to generate a high-precision synchronous clock output signal. 2. According to the all-digital phase-locked loop high-precision synchronous clock method according to claim 1, in step (4), the pulse increase and decrease controller generates the frequency division control coefficient N of the frequency divider according to the phase difference output by the digital filter, specifically The method is: The pulse increase/decrease controller modulates the phase difference signal up into an effective down pulse, and the phase difference signal down into an effective up pulse; when the up pulse is valid, if the previous frequency division coefficient N _i-1 ≤ N _clk (N _clk is the frequency division coefficient corresponding to the standard second clock, and its value is equal to the crystal oscillator frequency), then N _i =N _i-1 +1, and implements lag correction for the next output synchronous clock signal; if the previous frequency division coefficient N _i-1 > N _clk , then N _i ＝N _i-1 , no correction will be made to the next output synchronous clock signal; when the down pulse is valid, if the previous frequency division coefficient N _i-1 ≥ N _clk , then N _i ＝N _{i- 1} -1, implement advanced correction for the next output synchronous clock signal; if the previous frequency division coefficient N _i-1 <N _clk , then N _i =N _i-1 , do not correct the next output synchronous clock signal; The judgment result N _i is latched and output to the frequency divider as the frequency division control coefficient for the next second. 3. The full digital phase-locked loop high-precision synchronous clock method according to claim 1, in step (5), the self-calibration controller uses the frequency division control coefficient before the satellite clock fails, the current ambient temperature and noise parameters to generate frequency division Control coefficient N; the specific method is: use α to represent the temperature sensitivity of crystal oscillator frequency stability, u(k) represents the crystal oscillator temperature measured by the temperature sensor at t _k , y(k) represents the correction signal at t _k , v(k ) represents the noise at time t _k ; the frequency division control coefficient N at time t _k after the satellite clock fails is: .