CN104300969A - High-precision synchronization clock realization method based on full digital phase-locked loop - Google Patents
High-precision synchronization clock realization method based on full digital phase-locked loop Download PDFInfo
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Abstract
The invention discloses a high-precision synchronization clock realization method based on a full digital phase-locked loop. The method comprises the following steps: a phase discriminator makes a comparison between the phases of an input satellite source clock signal and an output synchronization clock signal and a phase difference signal is generated through a digital filter; a clock source state monitor monitors the work state of a satellite clock online; when the satellite clock is in a normal working mode, a pulse increase and decrease controller generates frequency division control coefficients of a frequency divider according to the phase difference output by the digital filter; when the satellite clock is in an out-of-step working mode, a self-correction controller generates frequency division control coefficients by utilizing the frequency division control coefficients before the failure of the satellite clock, current environment temperature and noise parameters; and the frequency divider generates high-precision synchronization clock output signals according to the frequency division control coefficients. The synchronization clock signal produced with the method has the advantages of small random errors and small accumulative errors, and can still keep high time service precision for a period after the failure of the satellite clock, and can provide accurate time synchronization second pulse signals for an electric system.
Description
Technical field
The present invention relates to a kind of synchronised clock implementation method, particularly a kind of high-precise synchronization clock implementation method based on all-digital phase-locked loop.
Background technology
The multiple satellite time service systems (being hereafter referred to as satellite clock) such as domestic Beidou satellite navigation system and american global positioning system can provide round-the-clock time signal, time service precision is high, and have wide area time synchronized performance good, not by condition restrictions such as geographical and weathers, apply the advantages such as simple, obtain increasing application in directions such as electrical power system wide-area measurement, fault traveling wave location, the exact time synchronization technology based on satellite clock is subject to extensive concern.
But in the situations such as satellite losing lock, pulse per second (PPS) error can reach tens microseconds microsecond even up to a hundred; Satellite clock signal can be subject to various electromagnetic interference in communication process simultaneously, may cause signal interruption time serious; Its precision and stability are difficult to meet the time synchronized requirement protecting fields such as monitoring.So when utilizing satellite clock as wide area time synchronized source, the integrity problem of satellite clock signal considered, the timing tracking accuracy particularly after satellite clock inefficacy.
Crystal oscillator clock has larger accumulated error and less random error, and the error characteristics of satellite clock are then just in time contrary, and the time service error characteristics of two kinds of clocks are complementary.In order to ensure precision and the stability of clock synchronization system, experts and scholars propose the multiple time service scheme based on satellite clock and the complementation of crystal oscillator clock error, satellite clock random error etc. is revised as adopted the accumulated error of satellite clock signal on-line amending crystal oscillator pulse per second (PPS) and utilizing High Precision Crystal Oscillator to monitor, effectively improve the precision and stability of satellite clock, but the equal Shortcomings of existing each scheme: sample data amount is large, the frequency drift, compensation scheme calculation of complex etc. that have ignored crystal oscillator.
In recent years, PHASE-LOCKED LOOP PLL TECHNIQUE is developed rapidly, and the output signal of phase-locked loop from motion tracking input signal phase place, can realize the closed-loop automatic control of system.All-digital phase-locked loop is owing to having outside the advantages such as reliability is high, antijamming capability is strong, volume is little, price is low, be easy to integrated, peripheral circuit is simple, solve the insoluble essence difficult problem of a lot of analog loop, as saturated in direct current null offset, device, to responsive to temperature, must the difficult problems such as initialization of calibration be carried out.All-digital phase-locked loop technology applies maturation in grid phase frequency measurement, is widely applied in field of power.
Summary of the invention
For meeting the precise synchronization demand of protecting electrical power system control field; realize effectively and under step loss condition all keeping higher stability and synchronism at satellite clock, the invention provides a kind of high-precise synchronization clock based on all-digital phase-locked loop and realize new method.The present invention utilizes the Phase Tracking advantage of all-digital phase-locked loop, based on the feature of satellite clock and the complementation of crystal oscillator clock error, propose satellite clock lost efficacy after time service scheme; The present invention effectively can improve the stability of output clock.
The technical scheme that the present invention solves the problems of the technologies described above comprises the following steps:
(1) when satellite clock is working properly, phase discriminator is to input satellite clock signal and export the phase place of synchronizing clock signals and compare, and produces the output signal that can characterize the advanced and lagged relationship of both phase places;
(2) digital filter carries out filter to the output signal of phase discriminator and to make an uproar process, and according to phase place, advanced and lag situation produces phase difference output signal: when satellite clock signal phase place is advanced, phase difference output signal up, during satellite clock signal delayed phase, phase difference output signal down;
(3) operating state of clock source state monitor on-line monitoring satellite clock, when receiving normal, selects normal mode of operation, otherwise, select step-out mode of operation;
(4), during normal mode of operation, pulse increase and decrease controller produces the frequency dividing control coefficient N of frequency divider according to the phase difference that digital filter exports;
(5), during step-out mode of operation, frequency dividing control coefficient, current ambient temperature and noise parameter before self tuning controller utilizes satellite clock to lose efficacy produce frequency dividing control coefficient N;
(6) frequency divider carries out frequency division according to frequency dividing control coefficient N to crystal oscillation signal, produces high-precise synchronization clock output signal.
Above-mentioned all-digital phase-locked loop high-precise synchronization clock method, in step (4), pulse increase and decrease controller produces the frequency dividing control coefficient N of frequency divider according to the phase difference that digital filter exports, and concrete grammar is:
Phase signal up is modulated into effective subtract pulse by pulse increase and decrease controller, and phase signal down is modulated into and effectively increases pulse; When increasing pulse and being effective, if previous divide ratio N
i-1≤ N
clk(N
clkfor the divide ratio that standard second clock is corresponding, its numerical value equals crystal oscillator frequency), then N
i=N
i-1+ 1, synchronizing clock signals is exported to the next one and realizes correction or lag; If previous divide ratio N
i-1> N
clk, then N
i=N
i-1, synchronizing clock signals is exported to the next one and does not correct; When subtract pulse is effective, if previous divide ratio N
i-1>=N
clk, then N
i=N
i-1-1, synchronizing clock signals is exported to the next one and realizes anticipatory control; If previous divide ratio N
i-1< N
clk, then N
i=N
i-1, synchronizing clock signals is exported to the next one and does not correct; Result N will be differentiated
ilatch, and export to frequency divider as the frequency dividing control coefficient of next second.
Above-mentioned all-digital phase-locked loop high-precise synchronization clock method, step adjusts divide ratio in real time according to temperature variations and time variations in (5), to eliminate accumulated error to the impact exporting synchronizing clock signals, and adaptive prediction model algorithm is utilized to predict generation frequency dividing control coefficient N.Crystal oscillator accumulated error (μ (t)) represents that exporting synchronizing clock signals is carved into input satellite clock signal the time error measuring hours cumulative from the outset.T
kthe crystal oscillator accumulated error in moment can be expressed as:
（1）
The ageing time of crystal oscillator, measurement noises and temperature can have an impact to frequency stability, because the rate of ageing of crystal oscillator is very little on frequency stability impact, in order to simplified model, is affected and are incorporated in noise effect.The temperature susceplibility of crystal oscillator frequency stability is represented, u(k with α) represent t
kthe crystal oscillator temperature of moment temperature sensor measurement, y(k) represent t
kthe correction signal in moment, v(k) represent t
kthe noise in moment.Then t
kthe accumulated error that moment increases can be expressed as:
（2）
Formula (2) is substituted into formula (1) obtain:
（3）
Suppose μ (t
0)=0, then t after satellite clock inefficacy
kthe frequency dividing control coefficient N in moment is:
（4）
Technique effect of the present invention is: and feature that crystal oscillator clock random error little little according to satellite clock accumulated error, proposes a kind of electric power system high-precise synchronization clock based on all-digital phase-locked loop and realize new method.The method, when satellite clock is working properly, utilizes all-digital phase-locked loop to make the phase fluctuation of crystal oscillator clock tracking satellite clock pulse per second (PPS), eliminates the accumulated error of crystal oscillator clock in real time; When satellite clock lost efficacy, frequency dividing control coefficient, current ambient temperature and noise parameter before utilizing satellite clock to lose efficacy, the accumulated error of forecast value revision crystal oscillator clock.The simulation experiment result shows, the synchronised clock that the method produces has the little and advantage that accumulated error is little of random error simultaneously, in satellite clock loses efficacy a period of time, still can keep higher time service precision, can be electric power system and exact time synchronization pps pulse per second signal is provided.
Below in conjunction with accompanying drawing, the present invention is further illustrated.
Accompanying drawing explanation
Fig. 1 is all-digital phase-locked loop synchronised clock theory diagram;
Fig. 2 be satellite clock normal time clocking error;
Fig. 3 is the clocking error after satellite clock lost efficacy.
Embodiment
Fig. 1 is all-digital phase-locked loop synchronised clock theory diagram.See Fig. 1, when satellite clock is working properly, adopt phase discriminator to compare input satellite clock signal and the phase place that exports synchronised clock feedback signal, produce the output signal that can characterize the advanced and lagged relationship of both phase places; Digital filter carries out filter to phase detector output signal and to make an uproar process, and produces phase difference output signal; The operating state of clock source state monitor on-line monitoring satellite clock, when receiving normal, selects normal mode of operation, otherwise, select step-out mode of operation; Pulse increase and decrease controller differentiates the phase difference size that digital filter exports, and produces the frequency dividing control coefficient N of frequency divider; Self tuning controller is when step-out mode of operation, and frequency dividing control coefficient, current ambient temperature and noise parameter before utilizing satellite clock to lose efficacy produce frequency dividing control coefficient N; Frequency divider carries out frequency division according to control coefrficient N to crystal oscillation signal, produces and exports high-precise synchronization clock signal.
In order to verify the feasibility of a kind of high-precise synchronization clock implementation method based on all-digital phase-locked loop described in the invention, MATLAB is used to carry out Simulation experiments validate, for improving the accuracy of experiment, the clock adopted in emulation coincide with actual clock as far as possible, wherein the random error of satellite clock obeys average is the normal distribution of zero, σ=50ns; Crystal oscillator frequency is 500MHz, frequency accuracy 10
-9, frequency stability 10
-11(can select 25MHz High Precision Crystal Oscillator during practical application, through FPGA frequency multiplication to 500MHz), assuming that crystal oscillator temperature constant is 50 DEG C, and adopts high-frequency pulse signal analogue noise to disturb.Utilize the crystal oscillator of this 500MHz as local clock, satellite clock, as input clock, utilizes above-mentioned steps can obtain precise and stable output clock.
When experiment starts, satellite clock is working properly, and the divide ratio adopting pulse increase and decrease controller to export produces output clock, and result as shown in Figure 2; Two is constantly little, and satellite clock lost efficacy, and the divide ratio adopting self tuning controller to calculate produces output clock, and result as shown in Figure 3.
μ in Fig. 2
tfor satellite clock random error value, μ
t 'for the output clock error that self tuning controller simulation produces.As can be seen from the figure, error estimate curve approaching to reality value curve, estimation effect is good, demonstrates the correctness of above-mentioned Mathematical Modeling.As can be seen from Figure 3, the error of output clock builds up increase.
From simulation result, method described in this patent can fully utilize the advantage of satellite clock and crystal oscillator clock, produces accumulated error and all little high-precise synchronization clock of random error.In actual applications for improving the clock accuracy after satellite clock inefficacy, should ensure that ambient temperature is constant as far as possible, making High Precision Crystal Oscillator have enough long-term stabilities.
Claims (3)
1., based on a high-precise synchronization clock implementation method for all-digital phase-locked loop, comprise the steps:
(1) when satellite clock is working properly, phase discriminator is to input satellite clock signal and export the phase place of synchronizing clock signals and compare, and produces the output signal that can characterize the advanced and lagged relationship of both phase places;
(2) digital filter carries out filter to the output signal of phase discriminator and to make an uproar process, and according to phase place, advanced and lag situation produces phase difference output signal: when satellite clock signal phase place is advanced, phase difference output signal up, during satellite clock signal delayed phase, phase difference output signal down;
(3) operating state of clock source state monitor on-line monitoring satellite clock, when receiving normal, selects normal mode of operation, otherwise, select step-out mode of operation;
(4), during normal mode of operation, pulse increase and decrease controller produces the frequency dividing control coefficient N of frequency divider according to the phase difference that digital filter exports;
(5), during step-out mode of operation, frequency dividing control coefficient, current ambient temperature and noise parameter before self tuning controller utilizes satellite clock to lose efficacy produce frequency dividing control coefficient N;
(6) frequency divider carries out frequency division according to frequency dividing control coefficient N to crystal oscillation signal, produces high-precise synchronization clock output signal.
2. all-digital phase-locked loop high-precise synchronization clock method according to claim 1, in step (4), pulse increase and decrease controller produces the frequency dividing control coefficient N of frequency divider according to the phase difference that digital filter exports, and concrete grammar is:
Phase signal up is modulated into effective subtract pulse by pulse increase and decrease controller, and phase signal down is modulated into and effectively increases pulse; When increasing pulse and being effective, if previous divide ratio N
i-1≤ N
clk(N
clkfor the divide ratio that standard second clock is corresponding, its numerical value equals crystal oscillator frequency), then N
i=N
i-1+ 1, synchronizing clock signals is exported to the next one and realizes correction or lag; If previous divide ratio N
i-1> N
clk, then N
i=N
i-1, synchronizing clock signals is exported to the next one and does not correct; When subtract pulse is effective, if previous divide ratio N
i-1>=N
clk, then N
i=N
i-1-1, synchronizing clock signals is exported to the next one and realizes anticipatory control; If previous divide ratio N
i-1< N
clk, then N
i=N
i-1, synchronizing clock signals is exported to the next one and does not correct; Result N will be differentiated
ilatch, and export to frequency divider as the frequency dividing control coefficient of next second.
3. all-digital phase-locked loop high-precise synchronization clock method according to claim 1, frequency dividing control coefficient, current ambient temperature and noise parameter before in step (5), self tuning controller utilizes satellite clock to lose efficacy produce frequency dividing control coefficient N; Concrete grammar is: the temperature susceplibility representing crystal oscillator frequency stability with α, u(k) represent t
kthe crystal oscillator temperature of moment temperature sensor measurement, y(k) represent t
kthe correction signal in moment, v(k) represent t
kthe noise in moment; T after satellite clock lost efficacy
kthe frequency dividing control coefficient N in moment is:
.
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| CN110133998A (en) * | 2019-05-17 | 2019-08-16 | 长沙理工大学 | A kind of method of anti-duration synchronization attack |
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| CN110531380A (en) * | 2019-08-30 | 2019-12-03 | 长沙理工大学 | The device and method of satellite clock source low amplitude persistent anomaly for identification |
| CN111130538A (en) * | 2020-02-27 | 2020-05-08 | 北京和德宇航技术有限公司 | Frequency calibration system and frequency instrument |
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| CN109299496A (en) * | 2018-07-26 | 2019-02-01 | 国网湖南省电力有限公司 | A kind of high-precise synchronization clock generation method |
| CN110133998A (en) * | 2019-05-17 | 2019-08-16 | 长沙理工大学 | A kind of method of anti-duration synchronization attack |
| CN110262343A (en) * | 2019-06-21 | 2019-09-20 | 新里程医用加速器(无锡)有限公司 | Real-time communication network for clinac control system |
| CN110531380A (en) * | 2019-08-30 | 2019-12-03 | 长沙理工大学 | The device and method of satellite clock source low amplitude persistent anomaly for identification |
| CN111130538A (en) * | 2020-02-27 | 2020-05-08 | 北京和德宇航技术有限公司 | Frequency calibration system and frequency instrument |
| CN111562595A (en) * | 2020-05-19 | 2020-08-21 | 中国科学院微小卫星创新研究院 | Satellite autonomous positioning and time synchronization system and method |
| CN111665377A (en) * | 2020-06-05 | 2020-09-15 | 国网福建省电力有限公司 | Remote phase-locking synchronous standard source |
| CN111665377B (en) * | 2020-06-05 | 2023-05-05 | 国网福建省电力有限公司 | Remote phase-locked synchronous standard source |
| WO2022179309A1 (en) * | 2021-02-25 | 2022-09-01 | 乐鑫信息科技（上海）股份有限公司 | Clock management apparatus, clock frequency division module and system-on-chip |
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