CN111665377B - Remote phase-locked synchronous standard source - Google Patents
Remote phase-locked synchronous standard source Download PDFInfo
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- CN111665377B CN111665377B CN202010503967.7A CN202010503967A CN111665377B CN 111665377 B CN111665377 B CN 111665377B CN 202010503967 A CN202010503967 A CN 202010503967A CN 111665377 B CN111665377 B CN 111665377B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/28—Provision in measuring instruments for reference values, e.g. standard voltage, standard waveform
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R35/00—Testing or calibrating of apparatus covered by the other groups of this subclass
- G01R35/005—Calibrating; Standards or reference devices, e.g. voltage or resistance standards, "golden" references
- G01R35/007—Standards or reference devices, e.g. voltage or resistance standards, "golden references"
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- G—PHYSICS
- G04—HOROLOGY
- G04R—RADIO-CONTROLLED TIME-PIECES
- G04R20/00—Setting the time according to the time information carried or implied by the radio signal
- G04R20/02—Setting the time according to the time information carried or implied by the radio signal the radio signal being sent by a satellite, e.g. GPS
Abstract
The invention provides a remote phase-locked synchronous standard source, which comprises a BDS/GPS module, a signal generating module connected with the BDS/GPS module and a power amplifying unit connected with the signal generating module; the standard source outputs standard source voltage and standard source current through the power amplification unit; the power amplification unit is controlled by a cyclic pulse signal output by the signal generation module; when a plurality of standard sources perform phase-locking synchronization, the signal generation module receives an accurate clock signal of a positioning satellite by using the BDS/GPS module, and performs clock reference correction on the output cyclic pulse signal by using the clock signal, so that the cyclic pulse signal of the signal generation module of each standard source and the accurate clock signal of the positioning satellite are synchronously locked, and the phase locking of the standard source voltage and the standard source current output by each standard source is synchronous; the invention solves the technical problem of remote synchronous output of a plurality of standard sources by using the technical scheme of phase-locked synchronization of high-precision PPS signals of the satellite positioning module.
Description
Technical Field
The invention relates to the technical field of remote synchronization of standard sources, in particular to a remote phase-locked synchronization standard source.
Background
Standard sources are often used in power systems, and the standard sources are devices capable of providing accurate voltage and current output, and the output voltage and current program control of the standard sources are accurate and adjustable, and the standard sources generally comprise single-phase, three-phase and four-phase divisions, and each phase comprises one adjustable constant-voltage source and one adjustable constant-current source. Standard sources are often used to calibrate some test measurement instruments.
In the electric power test, a plurality of tested devices are required to be synchronously tested to verify the performance of the devices, but as no remote synchronous test device exists at present, the devices required to be synchronously tested can only be synchronously tested within a short distance, such as the same transformer substation, through the same standard source extension line, and the tested devices can only be put together in the test mode, so that the method cannot be used for a remote method.
There are additional test cases, such as when more channels of synchronization signals are required for testing, such as when up to 12 synchronous output signals are required in the case of dual buses, and a common standard source cannot provide the signals.
The disadvantages of the existing solutions are mainly manifested in two points:
1. the requirement of remote synchronous test cannot be met, the output line of the same standard source is pulled to be a distance of two hundred meters at most, and in practice, the distance between stations can be several kilometers or even tens of kilometers, and the synchronous test is very troublesome. Even if tested locally only, slightly lengthening the distance is cumbersome and inefficient.
2. The problem of synchronization of output signals of a plurality of standard sources cannot be solved, and the standard sources cannot cooperatively output.
Disclosure of Invention
The invention provides a remote phase-locked synchronous standard source, which utilizes the technical scheme of phase-locked synchronization of high-precision PPS signals of a satellite positioning module, and solves the technical problem of remote synchronous output of a plurality of standard sources.
The invention adopts the following technical scheme.
The remote phase-locked synchronous standard source comprises a BDS/GPS module, a signal generation module connected with the BDS/GPS module and a power amplification unit connected with the signal generation module; the standard source outputs standard source voltage and standard source current through the power amplification unit; the power amplification unit is controlled by a cyclic pulse signal output by the signal generation module; when the plurality of standard sources perform phase-locking synchronization, the signal generating module receives an accurate clock signal of the positioning satellite by the BDS/GPS module, and performs clock reference correction on the output cyclic pulse signal by the clock signal, so that the cyclic pulse signal of the signal generating module of each standard source and the accurate clock signal of the positioning satellite are synchronously locked, and the phase locking of the standard source voltage and the standard source current output by each standard source is synchronous.
The signal generation module comprises a DSP controller, a difference comparison unit and a signal generator; the signal generator comprises a DDS clock reference connected with the DSP controller through a data and control signal line; the DDS clock reference provides a reference clock signal required by the operation of the signal generator according to the instruction of the DSP controller; the DSP controller receives an external control instruction and controls the operation of a standard source; the power amplifier generates a standard source voltage and a standard source current by amplifying a waveform signal of a cycle wave generated by the signal generator; the signal generator generates a cyclic pulse signal corresponding to each cycle for comparison with a satellite clock signal in the period of the cycle.
The DDS clock reference is a digital frequency synthesizer for providing a high controllable precision clock reference for the signal generator; the frequency increasing and decreasing change of the frequency pulse signal of the signal generator is synchronous with the frequency increasing and decreasing change of the DDS clock reference.
The signal generator includes a DAC; the signal generator outputs the discretized digital waveform signal generated by the DSP controller to the power amplifier from the DAC according to a preset speed, so that the digital signal is converted into a continuous analog waveform signal which can be used by the power amplifier; the signal generator outputs a cycle pulse signal at the starting moment of each cycle of the analog waveform signal;
when a plurality of standard sources perform phase-locked synchronization, the BDS/GPS module firstly receives synchronization signals of positioning satellites, pairs the time according to satellite clock references, and then generates accurate second pulses according to the satellite synchronization signals and outputs the accurate second pulses to the difference comparison unit; the difference comparison unit extracts a cyclic pulse signal of the signal generator and calculates a time difference between the cyclic pulse signal and a second pulse, and the DSP controller controls a DDS clock reference of the signal generator according to the time difference.
When the difference comparing unit calculates the time difference, the time difference of arrival of the two pulses is calculated by comparing the rising edges of the second pulse and the cyclic pulse signal.
When the time difference indicates that the cyclic pulse signal is behind the second pulse signal, the DSP controller controls the DDS clock reference to increase the reference frequency value to increase the frequency of the cyclic wave of the signal generator to reduce the period of the signal generator, and accelerates the transmission frequency of the cyclic pulse signal to enable the cyclic pulse signal to catch up with the second pulse signal, so that the time difference between the cyclic pulse signal and the second pulse signal is reduced until the time difference is reduced to be within an error allowable range;
when the time difference indicates that the cyclic pulse signal leads the second pulse signal, the DSP controller controls the DDS clock reference to reduce the reference frequency value to reduce the frequency of the cyclic wave of the signal generator to increase the period of the signal generator, and reduces the transmission frequency of the cyclic pulse signal to enable the second pulse signal to catch up with the cyclic pulse signal, so that the time difference between the cyclic pulse signal and the second pulse signal is reduced until the time difference is reduced to be within an error allowable range.
The DSP controller can control the output clk of the DDS clock reference through a feedback algorithm so as to enable the phase of the cyclic pulse signal of the signal generator to be locked to the second pulse signal rapidly;
the feedback algorithm is formulated as clk=a+k×Δt;
wherein CLK: reference CLK value of DDS clock reference output;
a is the CLK value after assuming that the phase of the cyclic pulse signal output by the source is locked to the second pulse of the BDS/GPS module, and the CLK value is a known value;
k is an adjusting coefficient, the phase locking is faster as the K coefficient is larger, and K is a proper value obtained after actual measurement in order to prevent overshoot oscillation possibly caused by the excessively high sensitivity caused by the excessively large K coefficient;
delta T is the time difference between the rising edges of the source cyclic pulse and the second pulse obtained by the difference comparison unit.
The difference comparison unit comprises an FPGA; the FPGA is internally provided with a 32-bit counter, the counter counts at a preset frequency, the counter is cleared when a second pulse arrives, the value of the counter is latched into a latch at the rising edge of the cycle pulse, and the latched count value in the latch contains time difference information of the second pulse and the rising edge of the cycle pulse; let the value be C, determine in the subtractor that if the latched value is greater than half the maximum value of the counter, use C-2 32 As the output of the subtracter, otherwise C is directly the output value, the output of the subtracter is the output of the difference comparing unit.
And the standard source is internally provided with a power module.
The BDS/GPS module, the difference value comparison unit, the DSP controller, the DDS clock reference and the signal generator jointly form a phase-locked negative feedback loop; after the standard source completes phase-locking synchronization, the DSP controller sends out a signal for prompting successful phase-locking synchronization of the current standard source.
The invention provides a technical scheme for phase-locked synchronization by using high-precision PPS signals of a satellite positioning module, solves the technical problem of remote synchronous output of a plurality of standard sources, solves the problem of remote synchronous test of a power system, and improves the working efficiency.
Drawings
The invention is described in further detail below with reference to the attached drawings and detailed description:
FIG. 1 is a schematic diagram of the principles of the present invention;
FIG. 2 is a schematic diagram of a difference comparison unit;
FIG. 3 is a schematic circuit diagram of a DDS controller;
FIG. 4 is a schematic circuit diagram of a BDS/GPS module;
FIG. 5 is a schematic circuit diagram of the difference comparing unit FPGA;
FIG. 6 is a schematic circuit diagram of a DSP controller;
fig. 7 is a schematic circuit diagram of a signal generator.
Detailed Description
As shown in fig. 1-7, a remote phase-locked synchronization standard source comprises a BDS/GPS module, a signal generating module connected with the BDS/GPS module, and a power amplifying unit connected with the signal generating module; the standard source outputs standard source voltage and standard source current through the power amplification unit; the power amplification unit is controlled by a cyclic pulse signal output by the signal generation module; when the plurality of standard sources perform phase-locking synchronization, the signal generating module receives an accurate clock signal of the positioning satellite by the BDS/GPS module, and performs clock reference correction on the output cyclic pulse signal by the clock signal, so that the cyclic pulse signal of the signal generating module of each standard source and the accurate clock signal of the positioning satellite are synchronously locked, and the phase locking of the standard source voltage and the standard source current output by each standard source is synchronous.
The signal generation module comprises a DSP controller, a difference comparison unit and a signal generator; the signal generator comprises a DDS clock reference connected with the DSP controller through a data and control signal line; the DDS clock reference provides a reference clock signal required by the operation of the signal generator according to the instruction of the DSP controller; the DSP controller receives an external control instruction and controls the operation of a standard source; the power amplifier generates a standard source voltage and a standard source current by amplifying a waveform signal of a cycle wave generated by the signal generator; the signal generator generates a cyclic pulse signal corresponding to each cycle for comparison with a satellite clock signal in the period of the cycle.
The DDS clock reference is a digital frequency synthesizer for providing a high controllable precision clock reference for the signal generator; the frequency increasing and decreasing change of the frequency pulse signal of the signal generator is synchronous with the frequency increasing and decreasing change of the DDS clock reference.
The signal generator includes a DAC; the signal generator outputs the discretized digital waveform signal generated by the DSP controller to the power amplifier from the DAC according to a preset speed, so that the digital signal is converted into a continuous analog waveform signal which can be used by the power amplifier; the signal generator outputs a cycle pulse signal at the starting moment of each cycle of the analog waveform signal;
when a plurality of standard sources perform phase-locked synchronization, the BDS/GPS module firstly receives synchronization signals of positioning satellites, pairs the time according to satellite clock references, and then generates accurate second pulses according to the satellite synchronization signals and outputs the accurate second pulses to the difference comparison unit; the difference comparison unit extracts a cyclic pulse signal of the signal generator and calculates a time difference between the cyclic pulse signal and a second pulse, and the DSP controller controls a DDS clock reference of the signal generator according to the time difference.
When the difference comparing unit calculates the time difference, the time difference of arrival of the two pulses is calculated by comparing the rising edges of the second pulse and the cyclic pulse signal.
When the time difference indicates that the cyclic pulse signal is behind the second pulse signal, the DSP controller controls the DDS clock reference to increase the reference frequency value to increase the frequency of the cyclic wave of the signal generator to reduce the period of the signal generator, and accelerates the transmission frequency of the cyclic pulse signal to enable the cyclic pulse signal to catch up with the second pulse signal, so that the time difference between the cyclic pulse signal and the second pulse signal is reduced until the time difference is reduced to be within an error allowable range;
when the time difference indicates that the cyclic pulse signal leads the second pulse signal, the DSP controller controls the DDS clock reference to reduce the reference frequency value to reduce the frequency of the cyclic wave of the signal generator to increase the period of the signal generator, and reduces the transmission frequency of the cyclic pulse signal to enable the second pulse signal to catch up with the cyclic pulse signal, so that the time difference between the cyclic pulse signal and the second pulse signal is reduced until the time difference is reduced to be within an error allowable range.
The DSP controller can control the output clk of the DDS clock reference through a feedback algorithm so as to enable the phase of the cyclic pulse signal of the signal generator to be locked to the second pulse signal rapidly;
the feedback algorithm is formulated as clk=a+k×Δt;
wherein CLK: reference CLK value of DDS clock reference output;
a is the CLK value after assuming that the phase of the cyclic pulse signal output by the source is locked to the second pulse of the BDS/GPS module, and the CLK value is a known value;
k is an adjusting coefficient, the phase locking is faster as the K coefficient is larger, and K is a proper value obtained after actual measurement in order to prevent overshoot oscillation possibly caused by the excessively high sensitivity caused by the excessively large K coefficient;
delta T is the time difference between the rising edges of the source cyclic pulse and the second pulse obtained by the difference comparison unit.
The difference comparison unit comprises an FPGA; the FPGA is internally provided with a 32-bit counter, the counter counts at a preset frequency, the counter is cleared when a second pulse arrives, the value of the counter is latched into a latch at the rising edge of the cycle pulse, and the latched count value in the latch contains time difference information of the second pulse and the rising edge of the cycle pulse; let the value be C, determine in the subtractor that if the latched value is greater than half the maximum value of the counter, use C-2 32 As the output of the subtracter, otherwise C is directly the output value, the output of the subtracter is the output of the difference comparing unit.
And the standard source is internally provided with a power module.
The BDS/GPS module, the difference value comparison unit, the DSP controller, the DDS clock reference and the signal generator jointly form a phase-locked negative feedback loop; after the standard source completes phase-locking synchronization, the DSP controller sends out a signal for prompting successful phase-locking synchronization of the current standard source.
Examples:
when the remote test is carried out, the standard source equipment is firstly transported to each test point, then the standard source equipment is started, the BDS/GPS module firstly receives the synchronous signal of the positioning satellite and generates accurate second pulse according to the satellite clock reference time, the DSP controller controls the cycle frequency of the signal generator according to the second pulse to match the cycle frequency with the second pulse, after the cycle frequency of the signal generator of each standard source is matched with the second pulse, the phase locking synchronization of the remote test is finished by each standard source, and the phase of the power amplifier of each standard source is also synchronous by amplifying the standard source voltage and the standard source current generated by the waveform signal of the cycle of the signal generator.
After receiving the phase-locked synchronization success signals sent by all the standard source equipment DSP controllers, the testers can know that the phase synchronization of the standard source voltage and the standard source current output by all the standard sources is completed, and can start testing work.
Claims (4)
1. A remote phase-locked synchronization standard source, characterized by: the standard source comprises a BDS/GPS module, a signal generation module connected with the BDS/GPS module and a power amplification unit connected with the signal generation module; the standard source outputs standard source voltage and standard source current through the power amplification unit; the power amplification unit is controlled by a cyclic pulse signal output by the signal generation module; when a plurality of standard sources perform phase-locking synchronization, the signal generation module receives an accurate clock signal of a positioning satellite by using the BDS/GPS module, and performs clock reference correction on the output cyclic pulse signal by using the clock signal, so that the cyclic pulse signal of the signal generation module of each standard source and the accurate clock signal of the positioning satellite are synchronously locked, and the phase locking of the standard source voltage and the standard source current output by each standard source is synchronous;
the signal generation module comprises a DSP controller, a difference comparison unit and a signal generator; the signal generator comprises a DDS clock reference connected with the DSP controller through a data and control signal line; the DDS clock reference provides a reference clock signal required by the operation of the signal generator according to the instruction of the DSP controller; the DSP controller receives an external control instruction and controls the operation of a standard source; the power amplifier generates a standard source voltage and a standard source current by amplifying a waveform signal of a cycle wave generated by the signal generator; the signal generator generates a cyclic pulse signal corresponding to each cyclic wave in the period of the cyclic wave and used for comparing with a satellite clock signal;
the signal generator includes a DAC; the signal generator outputs the discretized digital waveform signal generated by the DSP controller to the power amplifier from the DAC according to a preset speed, so that the digital signal is converted into a continuous analog waveform signal which can be used by the power amplifier; the signal generator outputs a cycle pulse signal at the starting moment of each cycle of the analog waveform signal;
when a plurality of standard sources perform phase-locked synchronization, the BDS/GPS module firstly receives synchronization signals of positioning satellites, pairs the time according to satellite clock references, and then generates accurate second pulses according to the satellite synchronization signals and outputs the accurate second pulses to the difference comparison unit; the difference comparison unit extracts a cyclic pulse signal of the signal generator and calculates a time difference value between the cyclic pulse signal and a second pulse, and the DSP controller controls a DDS clock reference of the signal generator according to the time difference value;
the difference comparison unit comprises an FPGA; the FPGA is internally provided with a 32-bit counter, the counter counts at a preset frequency, the counter is cleared when a second pulse arrives, the value of the counter is latched into a latch at the rising edge of the cycle pulse, and the latched count value in the latch contains time difference information of the second pulse and the rising edge of the cycle pulse; assuming that the value is C, if the latched value is greater than half the maximum value of the counter, C-
As the output of the subtracter, or else, C is directly used as the output value, the output of the subtracter is the output of the difference value comparison unit;
when the time difference indicates that the cyclic pulse signal is behind the second pulse signal, the DSP controller controls the DDS clock reference to increase the reference frequency value to increase the frequency of the cyclic wave of the signal generator to reduce the period of the signal generator, and accelerates the transmission frequency of the cyclic pulse signal to enable the cyclic pulse signal to catch up with the second pulse signal, so that the time difference between the cyclic pulse signal and the second pulse signal is reduced until the time difference is reduced to be within an error allowable range;
when the time difference value indicates that the cyclic pulse signal leads the second pulse signal, the DSP controller controls the DDS clock reference to reduce the reference frequency value to reduce the frequency of the cyclic wave of the signal generator to increase the period of the signal generator, and reduces the transmission frequency of the cyclic pulse signal to enable the second pulse signal to catch up with the cyclic pulse signal, so that the time difference between the cyclic pulse signal and the second pulse signal is reduced until the time difference is reduced to be within an error allowable range;
the DSP controller can control the output clk of the DDS clock reference through a feedback algorithm so as to enable the phase of the cyclic pulse signal of the signal generator to be locked to the second pulse signal rapidly;
the feedback algorithm is formulated as
；
Wherein CLK: reference CLK value of DDS clock reference output;
a is the CLK value after assuming that the phase of the cyclic pulse signal output by the source is locked to the second pulse of the BDS/GPS module, and the CLK value is a known value;
k is an adjusting coefficient, the phase locking is faster as the K coefficient is larger, and K is a proper value obtained after actual measurement in order to prevent overshoot oscillation possibly caused by the excessively high sensitivity caused by the excessively large K coefficient;
the BDS/GPS module, the difference value comparison unit, the DSP controller, the DDS clock reference and the signal generator jointly form a phase-locked negative feedback loop; after the standard source finishes phase-locking synchronization, the DSP controller sends out a signal for prompting that the current standard source has successful phase-locking synchronization;
when remote testing is carried out, all standard source equipment is firstly transported to all test points, then the standard source equipment is started, a BDS/GPS module firstly receives a synchronous signal of a positioning satellite and generates accurate second pulse according to satellite clock reference time synchronization, a DSP controller controls the cycle frequency of a signal generator according to the second pulse to match the cycle frequency with the second pulse, after the cycle frequency of the signal generator of each standard source is matched with the second pulse, each standard source completes phase locking synchronization of the remote testing, and a power amplifier of each standard source realizes synchronization by amplifying standard source voltage and standard source current generated by waveform signals of the cycle of the signal generator;
after receiving the phase-locked synchronization success signals sent by all the standard source equipment DSP controllers, the testers can know that the phase synchronization of the standard source voltage and the standard source current output by all the standard sources is completed, and can start testing work.
2. A remote phase locked synchronization standard source according to claim 1, wherein: the DDS clock reference is a digital frequency synthesizer for providing a high controllable precision clock reference for the signal generator; the frequency increasing and decreasing change of the frequency pulse signal of the signal generator is synchronous with the frequency increasing and decreasing change of the DDS clock reference.
3. A remote phase locked synchronization standard source according to claim 1, wherein: when the difference comparing unit calculates the time difference, the time difference of arrival of the two pulses is calculated by comparing the rising edges of the second pulse and the cyclic pulse signal.
4. A remote phase locked synchronization standard source according to claim 1, wherein: and the standard source is internally provided with a power module.
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