CN111665377B - A remote phase-locked synchronization standard source - Google Patents

Abstract

The invention provides a remote phase-locked synchronous standard source, which comprises a BDS/GPS module, a signal generating module connected with the BDS/GPS module and a power amplifying unit connected with the signal generating module; the standard source outputs standard source voltage and standard source current through the power amplification unit; the power amplification unit is controlled by a cyclic pulse signal output by the signal generation module; when a plurality of standard sources perform phase-locking synchronization, the signal generation module receives an accurate clock signal of a positioning satellite by using the BDS/GPS module, and performs clock reference correction on the output cyclic pulse signal by using the clock signal, so that the cyclic pulse signal of the signal generation module of each standard source and the accurate clock signal of the positioning satellite are synchronously locked, and the phase locking of the standard source voltage and the standard source current output by each standard source is synchronous; the invention solves the technical problem of remote synchronous output of a plurality of standard sources by using the technical scheme of phase-locked synchronization of high-precision PPS signals of the satellite positioning module.

Description

A remote phase-locked synchronization standard source

technical field

The invention relates to the technical field of remote synchronization of standard sources, in particular to a remote phase-locked synchronization standard source.

Background technique

The standard source is often used in the power system. The standard source is a device that can provide accurate voltage and current output. The output voltage and current flow control is accurate and adjustable. Generally, there are single-phase, three-phase, and four-phase points. Each phase contains one circuit. An adjustable constant voltage source and an adjustable constant current source. Standard sources are often used to calibrate some test and measurement instruments.

In power testing, it is often necessary to perform synchronous testing on multiple tested devices to verify the performance of the equipment. However, since there is currently no equipment for long-distance synchronous testing, several equipment that need to be tested synchronously can only be performed within a short distance, such as the same Inside a substation, the same standard source is used to extend the line. This test method can only be carried out by putting the devices under test together, but this method is useless for long-distance.

There are other test situations, such as when more channels of synchronous signals are required for testing, such as the case of double busbars, up to 12 channels of synchronous output signals are required, which cannot be provided by general standard sources.

The shortcomings of the existing solutions are mainly manifested in two points:

1. It is impossible to solve the long-distance synchronous test requirements. The output line of the same standard source can be pulled at a distance of one or two hundred meters at most. In fact, the distance between stations may be several kilometers or even tens of kilometers. If synchronous testing is required, it will be It will be very troublesome. Even if it is only tested locally, it will be troublesome and inefficient to extend the distance a little bit.

2. The synchronization problem of the output signals of multiple standard sources cannot be solved, and multiple standard sources cannot output in coordination.

Contents of the invention

The invention proposes a remote phase-locked synchronization standard source, a technical solution for phase-locked synchronization using a high-precision PPS signal of a satellite positioning module, and solves the technical problem of long-distance synchronous output of multiple standard sources.

The present invention adopts the following technical solutions.

A remote phase-locked synchronization standard source, the standard source includes a BDS/GPS module, a signal generation module connected to the BDS/GPS module and a power amplification unit connected to the signal generation module; the standard source outputs a standard through the power amplification unit Source voltage and standard source current; the power amplifying unit is controlled by the cycle pulse signal output by the signal generation module; when multiple standard sources are phase-locked and synchronized, the signal generation module receives the precise clock signal of the positioning satellite with the BDS/GPS module, And use the clock signal to correct the clock reference of the output cycle pulse signal, so that the cycle pulse signal of the signal generation module of each standard source can be synchronously locked with the precise clock signal of the positioning satellite, so that the standard source voltage output by each standard source Phase-locked synchronization with standard source current.

Described signal generation module comprises DSP controller, difference comparison unit and signal generator; Described signal generator comprises the DDS clock reference that links to each other with DSP controller by data and control signal line; Described DDS clock reference presses DSP controller instructions to provide the signal generator with the reference clock signal required for its operation; the DSP controller receives external control instructions and controls the operation of the standard source; the power amplifier is generated by amplifying the cycle waveform signal generated by the signal generator Standard source voltage and standard source current; the signal generator generates a cycle pulse signal corresponding to the cycle for comparison with the satellite clock signal in each cycle period.

The DDS clock reference is a digital frequency synthesizer that provides a high controllable precision clock reference to the signal generator; the frequency increase and decrease of the cycle pulse signal of the signal generator is synchronized with the frequency increase and decrease of the DDS clock reference.

The signal generator includes a DAC; the signal generator outputs the discrete digital waveform signal generated by the DSP controller from the DAC to the power amplifier at a preset rate, so that the digital signal is converted into a continuous analog waveform signal available to the power amplifier ; The signal generator outputs a cycle pulse signal at the initial moment of each cycle of the analog waveform signal;

When multiple standard sources are phase-locked and synchronized, the BDS/GPS module first receives the synchronization signal of the positioning satellite and synchronizes the time according to the satellite clock reference, and then generates an accurate second pulse according to the satellite synchronization signal and outputs it to the difference comparison unit; The difference comparison unit extracts the periodic pulse signal of the signal generator and calculates the time difference between it and the second pulse, and the DSP controller controls the DDS clock reference of the signal generator according to the time difference.

When the difference comparison unit calculates the time difference, it calculates the time difference between the arrival of the two pulses by comparing the rising edges of the second pulse and the cycle pulse signal.

When the time difference shows that the cycle pulse signal lags behind the second pulse signal, the DSP controller controls the DDS clock reference to increase the reference frequency value to increase the frequency of the signal generator cycle to reduce its period, and speed up the sending frequency of the cycle pulse signal to make The cycle pulse signal can catch up with the second pulse signal, thereby reducing the time difference between the cycle pulse signal and the second pulse signal until the time difference is reduced to within the allowable range of error;

When the time difference shows that the cycle pulse signal is ahead of the second pulse signal, the DSP controller controls the DDS clock reference to reduce the base frequency value to reduce the frequency of the signal generator cycle to increase its cycle, and reduce the frequency of sending the cycle signal to make the second The pulse signal can catch up with the cycle pulse signal, thereby reducing the time difference between the cycle pulse signal and the second pulse signal until the time difference is reduced to within an error tolerance range.

The DSP controller can control the output clk of the DDS clock reference through a feedback algorithm, so that the phase of the cycle pulse signal of the signal generator is quickly locked to the second pulse signal;

The feedback algorithm is expressed in a formula as CLK=A+K×ΔT;

Among them, CLK: the reference CLK value of the DDS clock reference output;

A is the CLK value after the phase of the periodic pulse signal output by the assumption source has been locked to the second pulse of the BDS/GPS module, which is a known value;

K is the adjustment coefficient. The larger the K coefficient is, the faster the phase lock will be. In order to prevent the overshoot oscillation caused by the high sensitivity caused by the K coefficient being too large, K is an appropriate value after the actual measurement;

ΔT is the time difference between the source cycle pulse and the rising edge of the second pulse obtained by the difference comparison unit.

The difference comparison unit includes an FPGA; a 32-bit counter is built in the FPGA, and the counter counts at a preset frequency, and the counter is cleared when the second pulse arrives, and the value of the counter is latched to In the latch, the count value latched in the latch contains the time difference information of the rising edge of the second pulse and the cycle pulse; set this value as C, and judge in the subtractor if the latched value is greater than half of the maximum value of the counter Then use C-2 ³² as the output of the subtractor, otherwise C is directly used as the output value, and the output of the subtractor is the output of the difference comparison unit.

The standard source has a built-in power module.

The BDS/GPS module, the difference comparison unit, the DSP controller, the DDS clock reference, and the signal generator together form a phase-locked negative feedback loop; when the standard source completes the phase-locked synchronization, the DSP controller sends out a The signal used to prompt the successful phase-locked synchronization of the current standard source.

The invention proposes a technical solution for phase-locked synchronization using the high-precision PPS signal of the satellite positioning module, which solves the technical problem of long-distance synchronous output of multiple standard sources, solves the problem of long-distance synchronous testing of power systems, and also improves the work efficiency. efficiency.

Description of drawings

Below in conjunction with accompanying drawing and specific embodiment the present invention is described in further detail:

Accompanying drawing 1 is schematic diagram of principle of the present invention;

Accompanying drawing 2 is the schematic diagram of the principle of difference comparison unit;

Accompanying drawing 3 is the circuit schematic diagram of DDS controller;

Accompanying drawing 4 is the circuit schematic diagram of BDS/GPS module;

Accompanying drawing 5 is the schematic diagram of the circuit principle of difference comparison unit FPGA;

Accompanying drawing 6 is the circuit schematic diagram of DSP controller;

Accompanying drawing 7 is the schematic diagram of the circuit principle of the signal generator.

Detailed ways

As shown in Figure 1-7, a kind of remote phase-locked synchronization standard source, described standard source comprises BDS/GPS module, the signal generating module connected with BDS/GPS module and the power amplifying unit connected with signal generating module; The standard source outputs the standard source voltage and standard source current through the power amplification unit; the power amplification unit is controlled by the cycle pulse signal output by the signal generation module; when multiple standard sources are phase-locked and synchronized, the signal generation module uses the BDS/GPS module Receive the precise clock signal of the positioning satellite, and use the clock signal to correct the clock reference of the output cycle pulse signal, so that the cycle pulse signal of the signal generation module of each standard source can be synchronously locked with the precise clock signal of the positioning satellite, so that The phase-lock synchronization of the standard source voltage and the standard source current output by each standard source.

Described signal generation module comprises DSP controller, difference comparison unit and signal generator; Described signal generator comprises the DDS clock reference that links to each other with DSP controller by data and control signal line; Described DDS clock reference presses DSP controller instructions to provide the signal generator with the reference clock signal required for its operation; the DSP controller receives external control instructions and controls the operation of the standard source; the power amplifier is generated by amplifying the cycle waveform signal generated by the signal generator Standard source voltage and standard source current; the signal generator generates a cycle pulse signal corresponding to the cycle for comparison with the satellite clock signal in each cycle period.

The DDS clock reference is a digital frequency synthesizer that provides a high controllable precision clock reference to the signal generator; the frequency increase and decrease of the cycle pulse signal of the signal generator is synchronized with the frequency increase and decrease of the DDS clock reference.

The signal generator includes a DAC; the signal generator outputs the discrete digital waveform signal generated by the DSP controller from the DAC to the power amplifier at a preset rate, so that the digital signal is converted into a continuous analog waveform signal available to the power amplifier ; The signal generator outputs a cycle pulse signal at the initial moment of each cycle of the analog waveform signal;

When multiple standard sources are phase-locked and synchronized, the BDS/GPS module first receives the synchronization signal of the positioning satellite and synchronizes the time according to the satellite clock reference, and then generates an accurate second pulse according to the satellite synchronization signal and outputs it to the difference comparison unit; The difference comparison unit extracts the periodic pulse signal of the signal generator and calculates the time difference between it and the second pulse, and the DSP controller controls the DDS clock reference of the signal generator according to the time difference.

When the difference comparison unit calculates the time difference, it calculates the time difference between the arrival of the two pulses by comparing the rising edges of the second pulse and the cycle pulse signal.

When the time difference shows that the cycle pulse signal lags behind the second pulse signal, the DSP controller controls the DDS clock reference to increase the reference frequency value to increase the frequency of the signal generator cycle to reduce its period, and speed up the sending frequency of the cycle pulse signal to make The cycle pulse signal can catch up with the second pulse signal, thereby reducing the time difference between the cycle pulse signal and the second pulse signal until the time difference is reduced to within the allowable range of error;

When the time difference shows that the cycle pulse signal is ahead of the second pulse signal, the DSP controller controls the DDS clock reference to reduce the base frequency value to reduce the frequency of the signal generator cycle to increase its cycle, and reduce the frequency of sending the cycle signal to make the second The pulse signal can catch up with the cycle pulse signal, thereby reducing the time difference between the cycle pulse signal and the second pulse signal until the time difference is reduced to within an error tolerance range.

The DSP controller can control the output clk of the DDS clock reference through a feedback algorithm, so that the phase of the cycle pulse signal of the signal generator is quickly locked to the second pulse signal;

The feedback algorithm is expressed in a formula as CLK=A+K×ΔT;

Among them, CLK: the reference CLK value of the DDS clock reference output;

A is the CLK value after the phase of the periodic pulse signal output by the assumption source has been locked to the second pulse of the BDS/GPS module, which is a known value;

K is the adjustment coefficient. The larger the K coefficient is, the faster the phase lock will be. In order to prevent the overshoot oscillation caused by the high sensitivity caused by the K coefficient being too large, K is an appropriate value after the actual measurement;

ΔT is the time difference between the source cycle pulse and the rising edge of the second pulse obtained by the difference comparison unit.

The difference comparison unit includes an FPGA; a 32-bit counter is built in the FPGA, and the counter counts at a preset frequency, and the counter is cleared when the second pulse arrives, and the value of the counter is latched to In the latch, the count value latched in the latch contains the time difference information of the rising edge of the second pulse and the cycle pulse; set this value as C, and judge in the subtractor if the latched value is greater than half of the maximum value of the counter Then use C-2 ³² as the output of the subtractor, otherwise C is directly used as the output value, and the output of the subtractor is the output of the difference comparison unit.

The standard source has a built-in power module.

The BDS/GPS module, the difference comparison unit, the DSP controller, the DDS clock reference, and the signal generator together form a phase-locked negative feedback loop; when the standard source completes the phase-locked synchronization, the DSP controller sends out a The signal used to prompt the successful phase-locked synchronization of the current standard source.

Example:

When performing remote testing, first transport each standard source device to each test point, and then start the standard source device. The BDS/GPS module first receives the synchronization signal of the positioning satellite and synchronizes the time according to the satellite clock reference, and then generates an accurate signal according to the satellite synchronization signal. The DSP controller controls the cycle frequency of the signal generator to match the second pulse according to the second pulse. When the cycle frequency of the signal generator of each standard source matches the second pulse, each standard source is completed. The phase-locking synchronization of the remote test, the power amplifier of each standard source amplifies the standard source voltage and standard source current generated by the waveform signal of the signal generator cycle, and its phase is also synchronized.

After the tester receives the phase-locked synchronization success signal sent by the DSP controller of all standard source equipment, he can know that the phase synchronization of the standard source voltage and standard source current output by all standard sources has been completed, and the test work can be started.

Claims (4)

1. A remote phase-locked synchronization standard source, characterized by: the standard source comprises a BDS/GPS module, a signal generation module connected with the BDS/GPS module and a power amplification unit connected with the signal generation module; the standard source outputs standard source voltage and standard source current through the power amplification unit; the power amplification unit is controlled by a cyclic pulse signal output by the signal generation module; when a plurality of standard sources perform phase-locking synchronization, the signal generation module receives an accurate clock signal of a positioning satellite by using the BDS/GPS module, and performs clock reference correction on the output cyclic pulse signal by using the clock signal, so that the cyclic pulse signal of the signal generation module of each standard source and the accurate clock signal of the positioning satellite are synchronously locked, and the phase locking of the standard source voltage and the standard source current output by each standard source is synchronous;

the signal generation module comprises a DSP controller, a difference comparison unit and a signal generator; the signal generator comprises a DDS clock reference connected with the DSP controller through a data and control signal line; the DDS clock reference provides a reference clock signal required by the operation of the signal generator according to the instruction of the DSP controller; the DSP controller receives an external control instruction and controls the operation of a standard source; the power amplifier generates a standard source voltage and a standard source current by amplifying a waveform signal of a cycle wave generated by the signal generator; the signal generator generates a cyclic pulse signal corresponding to each cyclic wave in the period of the cyclic wave and used for comparing with a satellite clock signal;

the signal generator includes a DAC; the signal generator outputs the discretized digital waveform signal generated by the DSP controller to the power amplifier from the DAC according to a preset speed, so that the digital signal is converted into a continuous analog waveform signal which can be used by the power amplifier; the signal generator outputs a cycle pulse signal at the starting moment of each cycle of the analog waveform signal;

when a plurality of standard sources perform phase-locked synchronization, the BDS/GPS module firstly receives synchronization signals of positioning satellites, pairs the time according to satellite clock references, and then generates accurate second pulses according to the satellite synchronization signals and outputs the accurate second pulses to the difference comparison unit; the difference comparison unit extracts a cyclic pulse signal of the signal generator and calculates a time difference value between the cyclic pulse signal and a second pulse, and the DSP controller controls a DDS clock reference of the signal generator according to the time difference value;

the difference comparison unit comprises an FPGA; the FPGA is internally provided with a 32-bit counter, the counter counts at a preset frequency, the counter is cleared when a second pulse arrives, the value of the counter is latched into a latch at the rising edge of the cycle pulse, and the latched count value in the latch contains time difference information of the second pulse and the rising edge of the cycle pulse; assuming that the value is C, if the latched value is greater than half the maximum value of the counter, C-

As the output of the subtracter, or else, C is directly used as the output value, the output of the subtracter is the output of the difference value comparison unit;

when the time difference indicates that the cyclic pulse signal is behind the second pulse signal, the DSP controller controls the DDS clock reference to increase the reference frequency value to increase the frequency of the cyclic wave of the signal generator to reduce the period of the signal generator, and accelerates the transmission frequency of the cyclic pulse signal to enable the cyclic pulse signal to catch up with the second pulse signal, so that the time difference between the cyclic pulse signal and the second pulse signal is reduced until the time difference is reduced to be within an error allowable range;

when the time difference value indicates that the cyclic pulse signal leads the second pulse signal, the DSP controller controls the DDS clock reference to reduce the reference frequency value to reduce the frequency of the cyclic wave of the signal generator to increase the period of the signal generator, and reduces the transmission frequency of the cyclic pulse signal to enable the second pulse signal to catch up with the cyclic pulse signal, so that the time difference between the cyclic pulse signal and the second pulse signal is reduced until the time difference is reduced to be within an error allowable range;

the DSP controller can control the output clk of the DDS clock reference through a feedback algorithm so as to enable the phase of the cyclic pulse signal of the signal generator to be locked to the second pulse signal rapidly;

the feedback algorithm is formulated as

；

Wherein CLK: reference CLK value of DDS clock reference output;

a is the CLK value after assuming that the phase of the cyclic pulse signal output by the source is locked to the second pulse of the BDS/GPS module, and the CLK value is a known value;

k is an adjusting coefficient, the phase locking is faster as the K coefficient is larger, and K is a proper value obtained after actual measurement in order to prevent overshoot oscillation possibly caused by the excessively high sensitivity caused by the excessively large K coefficient;

the time difference of the rising edges of the source cyclic pulse and the second pulse is obtained by the difference comparison unit;

the BDS/GPS module, the difference value comparison unit, the DSP controller, the DDS clock reference and the signal generator jointly form a phase-locked negative feedback loop; after the standard source finishes phase-locking synchronization, the DSP controller sends out a signal for prompting that the current standard source has successful phase-locking synchronization;

when remote testing is carried out, all standard source equipment is firstly transported to all test points, then the standard source equipment is started, a BDS/GPS module firstly receives a synchronous signal of a positioning satellite and generates accurate second pulse according to satellite clock reference time synchronization, a DSP controller controls the cycle frequency of a signal generator according to the second pulse to match the cycle frequency with the second pulse, after the cycle frequency of the signal generator of each standard source is matched with the second pulse, each standard source completes phase locking synchronization of the remote testing, and a power amplifier of each standard source realizes synchronization by amplifying standard source voltage and standard source current generated by waveform signals of the cycle of the signal generator;

after receiving the phase-locked synchronization success signals sent by all the standard source equipment DSP controllers, the testers can know that the phase synchronization of the standard source voltage and the standard source current output by all the standard sources is completed, and can start testing work.

2. A remote phase locked synchronization standard source according to claim 1, wherein: the DDS clock reference is a digital frequency synthesizer for providing a high controllable precision clock reference for the signal generator; the frequency increasing and decreasing change of the frequency pulse signal of the signal generator is synchronous with the frequency increasing and decreasing change of the DDS clock reference.

3. A remote phase locked synchronization standard source according to claim 1, wherein: when the difference comparing unit calculates the time difference, the time difference of arrival of the two pulses is calculated by comparing the rising edges of the second pulse and the cyclic pulse signal.

4. A remote phase locked synchronization standard source according to claim 1, wherein: and the standard source is internally provided with a power module.

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