CN115685725A - Clock calibration device of measuring equipment and measuring equipment - Google Patents
Clock calibration device of measuring equipment and measuring equipment Download PDFInfo
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Abstract
A clock calibration device of a measuring device comprises a GPS receiver module, a programmable array logic device and a correction module, wherein the GPS receiver module generates a second pulse synchronous signal, the programmable array logic device delays and adjusts the rising edge of the second pulse synchronous signal to obtain a third synchronous signal, then a synchronous pulse signal is generated according to the second pulse synchronous signal and the third synchronous signal, the time difference between the rising edge of the synchronous pulse signal and the clock edge of a counting clock signal is calculated, the period of the second pulse synchronous signal is determined based on the time difference and the period of the third synchronous signal, finally a calibration control signal is output based on the difference value between the period of the second pulse synchronous signal and a target period, and the correction module calibrates the frequency of a working clock signal of the measuring device based on the calibration control signal so that the working clock signal of the measuring device has the same frequency as the clock of a satellite positioning system.
Description
Technical Field
The invention relates to the technical field of measurement, in particular to a clock calibration device of measurement equipment and the measurement equipment.
Background
People's daily life, business, production and scientific research all need accurate time, and unified time standard is more and more important to each industry of modern society. The current international time standards are: atomic Time (TAI), universal Time (UT), and coordinated Universal Time (UTC).
In view of the global satellite positioning system, such as GPS and Beidou satellite positioning system, the used atomic clock is very accurate in travel time. Currently, GPS Time signals are general Time signals used in wireless communication base stations, power systems, and geological exploration, and for example, the communication base stations mainly receive 1PPS (Pulses Per 1 Second) signals and TOD (Time Of Day) signals from GPS satellites.
The pulse per second (1 PPS) signal is sent out through a satellite atomic clock, the rising edge of which is called a punctual edge, and the edge precision is extremely high. However, since GPS communication contains other data packets, the 1PPS signal is not uniform in pulse width time, typically 20ms to 200ms, and fig. 1 shows a waveform diagram of the 1PPS signal.
The GPS satellite uses an atomic clock, the frequency is very high, and above 9GHz, the principle of synchronizing the local clock with 1PPS signals is used, in fact, the frequency of the local clock source such as OCXO, TCXO, VCXO is locked to the equivalent frequency of the GPS satellite by using clock synchronization frequency locking. For example, the 1PPS pulse time interval in the GPS satellite is 10^7 equal parts, the local 10MHz clock source is used for locking the 10MHz clock of the GPS satellite, the 10MHz clock of the 1PPS is high in precision because the 10MHz rising edge on the GPS satellite is completely equivalent to the 1PPS clock edge, and the clock frequency of the local clock sources such as OCXO, TCXO and VCXO is in error with the standard 10MHz clock frequency. The output frequency of the local clock source is modified, so that the 10MHz output by the local clock source is infinitely close to the 10MHz frequency separated from the 1PPS signal of the satellite, the error is reduced, and the synchronization of the local clock frequency and the clock frequency separated from the 1PPS of the satellite positioning system is achieved.
Clock synchronization is a support technology in many fields such as communication, address exploration, electric power and the like, and aims to align clocks distributed around the world so that the clocks in all the parts are synchronized with a standard clock. The current mainstream architecture mode is a mode of adopting a numerical control phase-locked loop, and second pulse edge capture and clock synchronization are executed through processor chips with high real-time performance such as a DSP (digital signal processor), an FPGA (field programmable gate array) and the like. The scheme is high in manufacturing cost and strong in technical closure, and the 1PPS clock synchronization modules of different manufacturers are different in implementation principle.
Measuring equipment, such as an oscilloscope, a frequency spectrograph, a network analyzer and the like, uses a local working clock, and under the condition of long-term use, clock frequency drift exists, so that an error exists between a measured signal frequency value and a true value, and the frequency accuracy of a factory-returned calibration instrument can increase the use cost; in addition, when the measuring equipment is used for testing signals of a base station, communication equipment and the like, the working clock frequency of most of the measuring equipment cannot be synchronized to the clock domain of the tested equipment at present, so that the testing difficulty is increased; finally, in the current technical method for taming the working clock based on the satellite positioning system, the synchronization precision of the frequency of the taminated working clock source and the clock frequency of the positioning satellite is not high enough, and a certain frequency difference exists.
Disclosure of Invention
The invention mainly solves the technical problem of how to enable the working clock signal of the measuring equipment to have the same frequency with the clock of the satellite positioning system.
According to a first aspect, an embodiment provides a clock calibration apparatus of a measurement device, including:
the GPS receiver module is used for generating a pulse per second synchronization signal according to the time service information of the satellite positioning system;
the programmable array logic device comprises a synchronous pulse expansion circuit, a digital TDC circuit and a control unit;
the synchronous pulse expansion circuit is used for acquiring the pulse per second synchronous signal and the counting clock signal, and carrying out delay adjustment on the rising edge of the pulse per second synchronous signal to obtain a third synchronous signal, wherein the rising edge of the third synchronous signal is synchronous with the clock edge of the counting clock signal; the synchronous pulse expanding circuit is further used for generating a synchronous pulse signal according to the rising edge of the pulse per second synchronous signal and the rising edge of the third synchronous signal, wherein the rising edge of the synchronous pulse signal is the rising edge of the pulse per second synchronous signal, and the falling edge of the synchronous pulse signal is the rising edge of the third synchronous signal;
the digital TDC circuit is used for acquiring the synchronous pulse signal, calculating the time difference between the rising edge of the synchronous pulse signal and the clock edge of the counting clock signal, and determining the period of the second pulse synchronous signal based on the period of the third synchronous signal and the time difference between the rising edge of the synchronous pulse signal and the clock edge of the counting clock signal;
the control unit is used for acquiring the period and the target period of the pulse per second synchronizing signal and outputting a calibration control signal based on the difference value of the period and the target period of the pulse per second synchronizing signal;
and the correcting module is used for correcting the frequency of the working clock signal of the measuring equipment based on the correcting control signal so as to synchronize the working clock of the measuring equipment with the pulse per second synchronizing signal.
According to a second aspect, there is provided in an embodiment a measurement device comprising:
the main measurement module is used for collecting and processing signals based on working clock signals of the measurement equipment;
the clock calibration device according to any one of the embodiments of the present invention is configured to calibrate an operating clock signal of the measurement device after receiving an externally input calibration instruction.
According to the clock calibration device of the measurement device and the measurement device of the embodiment, the clock calibration device comprises a GPS receiver module, a programmable array logic unit and a calibration module, wherein the GPS receiver module generates a second pulse synchronization signal, the programmable array logic unit performs delay adjustment on the rising edge of the second pulse synchronization signal to obtain a third synchronization signal, then a synchronization pulse signal is generated according to the second pulse synchronization signal and the third synchronization signal, the time difference between the rising edge of the synchronization pulse signal and the clock edge of a counting clock signal is calculated, the period of the second pulse synchronization signal is determined based on the time difference and the period of the third synchronization signal, finally, a calibration control signal is output based on the difference between the period of the second pulse synchronization signal and a target period, and the calibration module calibrates the frequency of the working clock signal of the measurement device based on the calibration control signal to enable the working clock signal of the measurement device to have the same frequency as the clock of the satellite positioning system.
Drawings
FIG. 1 is a schematic waveform of a 1PPS signal;
FIG. 2 is a schematic diagram of time interval measurement;
FIG. 3 is a schematic diagram of a digital phase shift count measurement;
FIG. 4 is a schematic diagram of a PID taming working clock signal;
FIG. 5 is a schematic structural diagram of a clock calibration apparatus of a measurement device according to an embodiment;
FIG. 6 is a timing diagram of the counting clock signal CLK, the pulse-per-second synchronizing signal W, the first synchronizing signal W1, the second synchronizing signal W2, the third synchronizing signal W3 and the synchronizing pulse signal P;
FIG. 7 is a schematic diagram of a digital TDC circuit according to an embodiment;
FIG. 8 is a schematic diagram illustrating the existence of metastability;
FIG. 9 is a schematic diagram of a digital TDC circuit according to another embodiment;
FIG. 10 is a decoding timing diagram;
FIG. 11 is a diagram of a count clock signal, signals for each delay tap, and a valid signal 1;
FIG. 12 is a diagram of a count clock signal, signals for each delay tap, and a valid signal valid 2;
FIG. 13 is a control block diagram of a PID controller;
FIG. 14 is a flow chart of an implementation of a PID controller;
FIG. 15 is a simulation of the error signal e (k) over time;
fig. 16 is a schematic structural diagram of a measurement apparatus according to an embodiment.
Detailed Description
The present invention will be described in further detail with reference to the following detailed description and accompanying drawings. Wherein like elements in different embodiments are numbered with like associated elements. In the following description, numerous details are set forth in order to provide a better understanding of the present application. However, those skilled in the art will readily recognize that some of the features may be omitted or replaced with other elements, materials, methods in different instances. In some instances, certain operations related to the present application have not been shown or described in this specification in order not to obscure the core of the present application with unnecessary detail, and it is not necessary for those skilled in the art to describe these operations in detail, so that they may be fully understood from the description in the specification and the general knowledge in the art.
Furthermore, the features, operations, or characteristics described in the specification may be combined in any suitable manner to form various embodiments. Also, the various steps or actions in the method descriptions may be transposed or transposed in order, as will be apparent to one of ordinary skill in the art. Thus, the various sequences in the specification and drawings are for the purpose of describing certain embodiments only and are not intended to imply a required sequence unless otherwise indicated where such sequence must be followed.
The numbering of the components as such, e.g., "first", "second", etc., is used herein only to distinguish the objects as described, and does not have any sequential or technical meaning. The term "connected" and "coupled" as used herein includes both direct and indirect connections (couplings), unless otherwise specified.
Referring to fig. 2, fig. 2 shows a schematic diagram of the time interval measurement principle, where the period of the pulse-per-second (1 PPS) synchronization signal is T in fig. 2, and T is obtained by adding the "coarse measurement" time to the "fine measurement" time, as shown in the following expression:
wherein the content of the first and second substances,
in order to roughly measure the time, the measurement method is carried out,
in order to measure the time finely,
to count clock signal CLK periods. Since the pulse per second (1 PPS) synchronous signal is asynchronous with the count clock signal CLK,
the measurement error caused by a non-integer number of counting clock signals CLK, therefore, the measurement error term exists due to the asynchronous counting clock signals CLK and the second pulse (1 PPS) synchronous signals
The maximum error term can be + -1 counting clock width, i.e., -Tc to + Tc.
In addition, the period of the clock signal CLK is counted
The minimum accuracy of the measurement of the method, i.e. the minimum time resolution, is determined. In a test mode of the time interval measurement principle, the higher the frequency of the count clock signal CLK, the more accurate the measurement. However, the frequency of the counting clock signal is increased to achieve higher measurement accuracy, the performance requirement on the chip is higher, and the feasibility is poor.
As can be seen from the above description, in order to reduce the measurement error and improve the measurement accuracy of the time interval, the influence needs to be reduced or even ignored, and the most direct way is to increase the frequency value of the counting clock signal, but is limited by the performance of the chip, and if it is inconvenient to increase the frequency of the counting clock signal, the measurement accuracy can also be improved by using digital phase shift counting.
As shown in fig. 3, the counting clock signals CLK1 to CLK4 are shifted at intervals of 90 ° using DCM modules on an FPGA (programmable array logic) chip, the frequency of each CLKx (x =1,2,3, 4) is the same, and the pulse widths of the time intervals are counted at both the rising edge and the falling edge of CLKx. After the pulse width is counted by using the equivalent counting clock, the counting period is equivalent to Tc/8 of the original clock, the frequency of the equivalent clock is increased by 8 times, and the counting error is changed into-1/8 Tc to +1/8Tc of the original clock. However, this approach depends on the frequency of the operating clock signal of the measurement device, the higher the frequency of the operating clock signal, the more accurate the measurement.
The present embodiment also provides a method for taming a working clock signal by PID, in which a PID controller is a linear regulator, and calculates a control quantity according to a functional relationship of P (proportional), integral (I), and differential (D) based on a deviation between a given input value and an actual output value, so as to output a good tracking input signal. The PID control algorithm has mature counting and simple structure, and is convenient to realize.
In fig. 4, X (S) is an input signal corresponding to a 1PPS signal; y (S) is an output signal corresponding to the local tamed clock source frequency; e (S) is an error signal and U (S) is a control signal. K is P The method is a proportional link, and can generate adjustment action proportional to the deviation in time to reduce the deviation. K is P /(T I S) is an integral link for eliminating static errors of the system and improving the zero-difference, T, of the system I To integrate the time constant, T I The larger the integral the stronger. K is P T D S is a differentiation link which is used for controlling the change of the deviation and is also helpful for reducing overshoot and overcoming oscillation, wherein T D Is the differential time constant.
The PID controller is a method for controlling based on negative feedback, is beneficial to improving the stability of the system, and is suitable for being used in a high-precision control system. In the current method for local clock disciplining by using a digital PID controller in the market, the test precision error is more than one period of a counting clock signal CLK.
Based on the above problems, in the embodiments of the present invention, the pulse-to-second synchronization signal is converted into the synchronization pulse signal by the synchronization pulse extension circuit, and the time difference between the rising edge of the synchronization pulse signal and the clock edge of the counting clock signal is calculated, so as to obtain the fine measurement time, and then the period of the pulse-to-second synchronization signal is determined in combination with the coarse measurement time, and the frequency of the working clock signal is calibrated based on the difference between the period of the pulse-to-second synchronization signal and the target period, so that the working clock signal of the measurement device and the clock of the satellite positioning system have the same frequency.
Referring to fig. 5, fig. 5 is a schematic structural diagram of a clock calibration apparatus of a measurement device according to an embodiment, which is hereinafter referred to as a clock calibration apparatus for short, the clock calibration apparatus includes: a GPS receiver module 101, a programmable array logic device 102 and a correction module 103, wherein the programmable array logic device 102 includes a synchronization pulse expansion circuit 1021, a digital TDC circuit 1022, a control unit 1023 and a frequency division module 1024, and the correction module 103 includes a digital-to-analog converter 1031, a voltage-controlled oscillator 1032 and a phase-locked loop 1033, which are described in detail below.
The GPS receiver module 101 is configured to generate a pulse-per-second synchronization signal, that is, a 1PPS synchronization signal, according to the time service information of the satellite positioning system.
The synchronization pulse expanding circuit 1021 in the programmable array logic device 102 is configured to obtain the pulse per second synchronization signal and the counting clock signal, and perform delay adjustment on a rising edge of the pulse per second synchronization signal to obtain a third synchronization signal, where the rising edge of the third synchronization signal is synchronized with the clock edge of the counting clock signal.
In an embodiment, the delay adjusting the rising edge of the pulse-per-second synchronization signal to obtain the third synchronization signal includes:
and acquiring the period of the counting clock signal at which the rising edge of the pulse-per-second synchronization signal is positioned, and taking the counting clock signal corresponding to the acquired period of the counting clock signal as the synchronous counting clock signal.
And generating a first synchronous signal based on the synchronous counting clock signal, wherein the rising edge of the first synchronous signal is synchronous with the clock edge of the synchronous counting clock signal.
And generating a second synchronization signal based on the first synchronization signal, wherein the rising edge of the second synchronization signal is delayed relative to the rising edge of the first synchronization signal by one cycle of the counting clock signal.
And generating a third synchronization signal based on the second synchronization signal, wherein a rising edge of the third synchronization signal is delayed by one cycle of the counting clock signal relative to a rising edge of the second synchronization signal.
Thus, the first synchronization signal, the second synchronization signal and the third synchronization signal have the same period, the second synchronization signal differs from the first synchronization signal by the period of one counting clock signal, and the third synchronization signal differs from the second synchronization signal by the period of one counting clock signal, so that the third synchronization signal differs from the first synchronization signal by the period of two counting clock signals.
It should be noted that the period of the first synchronization signal, the second synchronization signal or the third synchronization signal is the coarse measurement time
。
The synchronization pulse extension circuit 1021 is further configured to generate a synchronization pulse signal according to a rising edge of the pulse-per-second synchronization signal and a rising edge of the third synchronization signal, where the rising edge of the synchronization pulse signal is the rising edge of the pulse-per-second synchronization signal, and the falling edge of the synchronization pulse signal is the rising edge of the third synchronization signal.
It should be noted that the synchronization pulse expanding circuit 1021 in this embodiment can be implemented by a digital circuit, for example, by three D flip-flops, where the first synchronization signal is a signal output by one D flip-flop, the second synchronization signal is a signal output by two D flip-flops, and the third synchronization signal is a signal output by three D flip-flops.
The digital TDC circuit 1022 is configured to obtain the synchronization pulse signal, calculate a time difference between a rising edge of the synchronization pulse signal and a clock edge of the counting clock signal, and determine a period of the second pulse synchronization signal based on a period of the third synchronization signal and a time difference between the rising edge of the synchronization pulse signal and the clock edge of the counting clock signal.
Referring to fig. 6, fig. 6 is a timing diagram of the counting clock signal CLK, the pulse-per-second synchronization signal W, the first synchronization signal W1, the second synchronization signal W2, the third synchronization signal W3 and the synchronization pulse signal P. Since the pulse-per-second synchronization signal W and the counting clock signal CLK are asynchronous, in this embodiment, the pulse-per-second synchronization signal W is first asynchronous signal synchronized, and then the first synchronization signal W1, the second synchronization signal W2, and the third synchronization signal W3 are sequentially generated to synchronize the obtained third synchronization signal W3 with the clock edge of the clock signal, and then the rising edge of the pulse-per-second synchronization signal W is taken as the rising edge of the synchronization pulse signal P, and the rising edge of the third synchronization signal W3 is taken as the falling edge of the synchronization pulse signal P to form the synchronization pulse signal P, where the expression P = | < W3& W > of the synchronization pulse signal P indicates logical and |! Indicating that the logic is inverted.
In the present embodiment, the time difference between the rising edge of the synchronization pulse signal and the clock edge of the counting clock signal is calculated to calculate the time difference between two adjacent rising edges of the synchronization pulse signal and the clock edge of the counting clock signal respectively△t 1 And△ t 2 obtaining a fine measurement time
。
The control unit 1023 is configured to obtain the period of the pulse-per-second synchronization signal and the target period, and output a calibration control signal based on a difference between the period of the pulse-per-second synchronization signal and the target period. The control unit in this embodiment is a PID control unit, and the PID control unit determines the calibration control signal by a PID control method based on a difference between the period of the pulse-per-second synchronization signal and the target period.
The frequency dividing module 1024 is configured to receive a working clock signal of the measurement device, and divide the frequency of the working clock signal to obtain a counting clock signal.
In this embodiment, the pulse-per-second synchronization signal generated by the GPS receiver module 101 corresponds to an external triggerThe signal is subjected to coarse measurement of time interval by the synchronous pulse expansion circuit 1021 to obtain coarse measurement time
The coarse measurement time can be directly measured, and then a synchronization pulse signal P is generated and input into the digital TDC circuit 1022 to calculate the fine measurement time
. Obtaining the period of the pulse-per-second synchronous signal after the measurement
Period of time of re-handlingTInto the control unit 1023.
The calibration module 103 is configured to calibrate a frequency of an operating clock signal of the measurement device based on the calibration control signal, so that the operating clock of the measurement device is synchronized with the pulse-per-second synchronization signal.
In one embodiment, the correction module 103 includes: a digital-to-analog converter (D/a converter) 1031, a voltage controlled oscillator (VCXO) 1032, and a Phase Locked Loop (PLL) 1033. Wherein the digital-to-analog converter 1031 is configured to convert the calibration control signal into an analog control voltage; the voltage controlled oscillator 1032 is configured to generate a reference clock frequency value corresponding to the analog control voltage based on the analog control voltage, in this embodiment, the voltage controlled oscillator 1032 is a local clock reference source, and has good short-term stability, good phase noise index and jitter performance, and the voltage controlled oscillator 1032 adjusts the reference clock frequency value output by the voltage controlled oscillator 1032 according to the analog control voltage received by the input end of the voltage controlled oscillator; the phase locked loop 1033 is used to generate an operating clock signal of the measurement device that is several times higher than the reference clock frequency based on the reference clock frequency value output by the voltage controlled oscillator 1032.
In one embodiment, referring to fig. 7, the digital TDC circuit 1022 includes a delay chain 201, a plurality of D flip-flops 202, and a first thermometer code decoder 203, which will be described in detail below.
The input end of the delay chain 201 is connected to the output end of the sync pulse spreading circuit 1021, and is used for receiving the signal output by the sync pulse spreading circuit 1021.
The delay chain 201 includes a plurality of delay taps, the delay taps correspond to the D flip-flops 202 one by one, and each delay tap is connected to an input pin of the D flip-flop 202 corresponding to the delay tap; each delay tap is used for performing a delay operation with different delay times on a signal received by the delay chain 201, where:
the delay tap 1 is used for performing a delay operation of a delay time t on a signal received by the delay chain 201;
the delay tap 2 is used for performing delay operation of delay time 2t on the signal received by the delay chain 201;
…
the delay tap n is used for delaying the signal received by the delay chain 201 by a delay time nt.
Each D flip-flop 202 is configured to receive a signal output by a corresponding delay tap, and output an effective level signal when the signal received by the delay chain 201 is a synchronization pulse signal; otherwise, an invalid level signal is output. That is, when the delay chain 201 does not receive the synchronization pulse signal, all D flip-flops output the invalid level signal, and after the synchronization pulse signal of the delay chain 201, since the pulse width of the synchronization pulse signal is limited, there is a portion of the valid level signal of the D flip-flop 201.
The first thermometer code decoder 203 receives the level signals output by the D flip-flops and outputs corresponding first decoded value sequences, wherein the first decoded value sequences comprise a plurality of first decoded values, and the first decoded values correspond to the level signals output by the D flip-flops one by one; the first thermometer code decoding module is configured to, according to the number of valid decoded values in the first decoded value sequence, respectively calculate a time difference between two adjacent rising edges of the synchronization pulse signal and a clock edge of the counting clock signal, where the time difference is an initial time difference.
Referring to fig. 8, due to the existence of the metastable state, when the pulse-to-second synchronization signal falls within the retention time window of the clock edge, the synchronization trigger signal may be synchronized to be the synchronization signal 1 by the current clock edge or may be synchronized to be the synchronization signal 2 by the next clock edge, that is, when the synchronization pulse extension circuit 1021 performs the delay adjustment on the rising edge of the pulse-to-second synchronization signal, the obtained third synchronization signal may include two counting clock signal periods or three counting clock signal periods with the pulse-to-second synchronization signal. Therefore, in order to avoid the existence of the metastable state, the present embodiment improves the digital TDC circuit shown in fig. 7, please refer to fig. 9, the digital TDC circuit further includes: a second thermometer code decoder 204, and gate logic 205, and a counter 206.
The first thermometer code decoder 203 is further configured to receive signals output by the delay taps of the delay chain, and when detecting the first data other than 0, the valid signal valid1 is pulled high, and output the first decoded value. The second thermometer code decoder 204 is configured to receive an inverse code signal of the signals output by the delay taps of the delay chain, and when detecting the first data jumping from 0 to 1 in the inverse code signal, pull up the valid signal valid2, and output a second decoded value. Referring to fig. 10, fig. 10 shows a decoding timing sequence, wherein data1 is a primary code signal output by the delay chain, and data2 is an inverse code signal of the primary code signal.
The and logic circuit 205 is configured to obtain the inverse code values of the first decoded value and the second decoded value, and perform an and operation on the inverse code values of the first decoded value and the second decoded value to obtain a first signal.
The counter 206 is configured to receive the first signal and count the first signal to obtain a count value, where the count value is a number of cycles of the counting clock signal included in the pulse width of the synchronization pulse signal.
In this embodiment, the first signal is m, and the number m = | valid2&valid1, counting the first signal m, the count value is b, then:
，
wherein, in the process,T D1 andT D2 representing the initial time difference between two adjacent rising edges of the synchronous pulse signal and the clock edge of the counting clock signal respectively;△t 1 and△t 2 which represents the time difference between two adjacent rising edges of the synchronization pulse signal and the clock edge of the counting clock signal.
Referring to fig. 11, if the sync pulse signal is input to the delay chain, D (0), D (1) \8230; D (n-1) represents the signal of each delay tap, each clock signal samples the signal on the delay chain, and after a first value different from 0 is detected on the tap, the valid signal valid1 is pulled high, and the value is output, and detection is not continued any more thereafter.
Referring to fig. 12, if the sync pulse signal is input to the delay chain, D (0) ', D (1)' \8230; 'D (n-1)' indicates the anticode signal of each delay tap, each count clock signal samples the signal on the delay chain, and when the first data transition from 0 to 1 in the anticode signal is detected at the tap, the valid signal valid2 is pulled high, and the value is output and is not detected any more thereafter.
As can be seen from a comparison between fig. 11 and fig. 12, the code-reversal detection timing is detected by converting the falling edge of the synchronization pulse signal P into the rising edge. The original pulse-per-second synchronization signal W is metastable, the third synchronization signal W3 after three beats is a steady-state signal, and the logic relation can be obtained, at least 2 complete counting clock signal periods exist between the rising edge and the falling edge of the synchronization pulse signal P, and then the counting clock signal periods are obtained through a formula
，
The time difference from the rising edge of the pulse-per-second synchronization signal W to the clock edge of the count clock signal can be calculated.
The embodiment of the invention widens the edges of the pulse-per-second synchronous signals into pulses, and then performs subtraction calculation, so that the conversion calculation can eliminate the metastable state method, and avoids detecting which specific tap position of the edges of the pulse-per-second synchronous signals in a delay chain.
The period of the pulse-per-second synchronization signal is obtained through the coarse measurement and the fine measurement
And subtracting the actually measured period T from the target period T' to obtain a deviation value e (k) = Delta T, and outputting the Delta T to the control unit.
In an embodiment, the control unit uses a PID (proportional integral derivative) controller to implement disciplining of the reference clock of the voltage controlled oscillator, as shown in fig. 13, the control quantity of the PID controller is converted by some columns, and finally the voltage controlled oscillator is controlled. The model of the PID controller in this embodiment is K P +K L /S+ K D * S, wherein K P Is a proportionality coefficient, K L Is the integral coefficient, K D Are differential coefficients.
Discretization can yield the digital difference equation for PID as follows:
U(k)=K P e(k)+ K I ∑ k j=0 e(j)+K D [e(k)-e(k-1)]
and k is a sampling serial number, u (k) is a regulator output control quantity at the k-th sampling time, e (k) is an offset value at the k-th sampling time, and e (k-1) is an offset value at the k-1-th sampling time. K P The method is a proportional link, and can generate deviation proportional adjustment in time to reduce the deviation. K I Is an integral link for eliminating static error of the system and improving the zero-difference degree of the system, K D The differential link is used for controlling the change of the deviation, and is beneficial to reducing overshoot and overcoming oscillation.
The transfer function G (S) of the taming voltage-controlled oscillator of the pulse-per-second synchronization signal is calculated as follows:
Y(s)= (K P + K I /S+ K D *S)* K F * 1/S*( Y(s)- X(s))
G(S)= Y(s)/ X(s)
the embodiment considers that a proportionality coefficient K exists between the control quantity and the output frequency of the voltage-controlled oscillator F The frequency division module can be regarded as an integral link, recorded as 1/S, and selects a proper coefficient K in the PID controller P 、K I ，K D Therefore, the output frequency of the clock source voltage-controlled oscillator can be adjusted based on the input error signal e (k). The programmable array logic device judges the value of the error signal e (k), and when the value is smaller than a certain value, the calibration is considered to be passed, and the calibration is finished. As shown in fig. 14, fig. 14 shows a flow chart for implementing the PID controller.
Fig. 15 is a simulation diagram of the variation of the error signal e (k) of the input value programmable array logic device with time, as shown in fig. 15, and it can be seen that the error signal e (k) becomes smaller and smaller after calibration.
Referring to fig. 16, an embodiment of the present invention further provides a measurement apparatus, where the measurement apparatus includes a main measurement module 301 and a clock calibration device 302, and the main measurement module 301 is configured to collect and process a signal based on a working clock signal of the measurement apparatus; the clock calibration device 302 is configured to calibrate an operating clock signal of the measurement apparatus after receiving an externally input calibration instruction.
The measuring equipment provided by the embodiment of the invention has the advantages that firstly, the accuracy of the time interval of the second pulse synchronous signal is improved, the precision is better than that of a counting clock signal period, secondly, a local clock source is acclimatized by using a satellite positioning system on the measuring equipment, and the clock source frequency accuracy of the measuring equipment is improved, so that the accuracy of the measuring equipment is improved, secondly, the frequency calibration of the clock source can be carried out on site in real time for the measuring equipment which is delivered from a factory, the factory calibration is not needed to be carried out after a period of time, the calibration cost is reduced, and finally, when the measuring equipment is used for testing signals of a base station, communication equipment and the like, because the clock of a tested object and the clock source of the testing and measuring instrument are synchronized to the clock domain on the satellite positioning system, the testing difficulty is reduced.
The present invention has been described in terms of specific examples, which are provided to aid understanding of the invention and are not intended to be limiting. For a person skilled in the art to which the invention pertains, several simple deductions, modifications or substitutions may be made according to the idea of the invention.
Claims (10)
1. A clock calibration apparatus for a measurement device, comprising:
the GPS receiver module is used for generating a pulse-per-second synchronization signal according to the time service information of the satellite positioning system;
the programmable array logic device comprises a synchronous pulse expansion circuit, a digital TDC circuit and a control unit;
the synchronous pulse expansion circuit is used for acquiring the second pulse synchronous signal and the counting clock signal, and performing delay adjustment on the rising edge of the second pulse synchronous signal to obtain a third synchronous signal, wherein the rising edge of the third synchronous signal is synchronous with the clock edge of the counting clock signal; the synchronous pulse expanding circuit is further used for generating a synchronous pulse signal according to the rising edge of the pulse per second synchronous signal and the rising edge of the third synchronous signal, wherein the rising edge of the synchronous pulse signal is the rising edge of the pulse per second synchronous signal, and the falling edge of the synchronous pulse signal is the rising edge of the third synchronous signal;
the digital TDC circuit is used for acquiring the synchronous pulse signal, calculating the time difference between the rising edge of the synchronous pulse signal and the clock edge of the counting clock signal, and determining the period of the second pulse synchronous signal based on the period of the third synchronous signal and the time difference between the rising edge of the synchronous pulse signal and the clock edge of the counting clock signal;
the control unit is used for acquiring the period and the target period of the pulse per second synchronizing signal and outputting a calibration control signal based on the difference value of the period and the target period of the pulse per second synchronizing signal;
and the correcting module is used for correcting the frequency of the working clock signal of the measuring equipment based on the correcting control signal so as to synchronize the working clock of the measuring equipment with the pulse per second synchronizing signal.
2. The clock calibration apparatus of claim 1, wherein the delay adjusting the rising edge of the pulse-per-second synchronization signal to obtain a third synchronization signal comprises:
acquiring the period of the counting clock signal at which the rising edge of the pulse per second synchronization signal is positioned, and taking the counting clock signal corresponding to the acquired period of the counting clock signal as a synchronous counting clock signal;
generating a first synchronization signal based on the synchronous counting clock signal, wherein the rising edge of the first synchronization signal is synchronous with the clock edge of the synchronous counting clock signal;
generating a second synchronization signal based on the first synchronization signal, a rising edge of the second synchronization signal being delayed with respect to a rising edge of the first synchronization signal by a period of a counting clock signal;
and generating a third synchronous signal based on the second synchronous signal, wherein the rising edge of the third synchronous signal is delayed by one period of a counting clock signal relative to the rising edge of the second synchronous signal.
3. The clock calibration apparatus of claim 1, wherein the determining the period of the pulse-per-second synchronization signal based on the period of the third synchronization signal and the time difference between the rising edge of the synchronization pulse signal and the clock edge of the count clock signal comprises:
calculating the time difference between two adjacent rising edges of the synchronous pulse signal and the clock edge of the counting clock signal;
acquiring the period of the third synchronous signal;
calculating a period of the pulse-per-second synchronization signal according to the following expression:
wherein the content of the first and second substances,Tis the period of the pulse-per-second synchronization signal,Nfor counting the number of cycles of the clock signal contained in the period of the third synchronization signal，T C In order to count the period of the clock signal,△t 1 and△t 2 which represents the time difference between two adjacent rising edges of the synchronization pulse signal and the clock edge of the counting clock signal, respectively.
4. The clock calibration apparatus of claim 3, wherein the digital TDC circuit comprises: the system comprises a delay chain, a plurality of D triggers and a first thermometer code decoder;
the delay chain comprises a plurality of delay taps, the delay taps correspond to the D triggers one by one, and each delay tap is connected with an input pin of the corresponding D trigger; each delay tap is used for performing delay operation with different delay time on the signal received by the delay chain, wherein:
the delay tap 1 is used for carrying out delay operation of delay time t on the signal received by the delay chain;
the delay tap 2 is used for carrying out delay operation of delay time 2t on the signal received by the delay chain;
…
the delay tap n is used for carrying out delay operation of delay time nt on the signal received by the delay chain;
each D trigger is used for receiving a signal output by the corresponding delay tap and outputting an effective level signal when the received signal is the synchronous pulse signal; otherwise, outputting an invalid level signal;
the first thermometer code decoder is used for receiving the level signals output by the D triggers and outputting corresponding first decoding value sequences, the first decoding value sequences comprise a plurality of first decoding values, and the first decoding values correspond to the level signals output by the D triggers one to one; and the first thermometer code decoding module determines the initial time difference from two adjacent rising edges of the synchronous pulse signal to the clock edge of the counting clock signal respectively according to the number of effective decoding values in the first decoding value sequence.
5. The clock calibration apparatus of claim 4, wherein the digital TDC circuit further comprises: the second thermometer code decoder, the AND gate logic circuit and the counter;
the first thermometer code decoder is further used for receiving signals output by each delay tap of the delay chain and outputting a first decoded value when a first signal which is not 0 is detected;
the second thermometer code decoder is used for receiving the complement signal of the signal output by each delay tap of the delay chain and outputting a second decoded value when detecting the first data jumping from 0 to 1;
the AND gate logic circuit is used for acquiring the inverse code values of the first decoding value and the second decoding value and performing AND operation on the inverse code values of the first decoding value and the second decoding value to obtain a first signal;
the counter is used for receiving the first signal and counting the first signal to obtain a count value, wherein the count value is the number of the counting clock signal periods contained in the pulse width of the synchronous pulse signal.
6. The clock calibration apparatus of claim 5, wherein calculating the time difference between the rising edge of the synchronization pulse signal and the clock edge of the count clock signal comprises:
calculating the time difference between two adjacent rising edges of the synchronous pulse signal and the clock edge of the counting clock signal according to the following expression:
wherein the content of the first and second substances,△t 1 and△t 2 representing the time difference between two adjacent rising edges of the synchronization pulse signal and the clock edge of the counting clock signal respectively,T D1 andT D2 representing the initial time difference between two adjacent rising edges of the synchronization pulse signal and the clock edge of the counting clock signal respectively,brepresenting the number of periods of the counting clock signal contained in the pulse width of the synchronization pulse signal.
7. The clock calibration apparatus of claim 1, wherein the programmable array logic further comprises:
and the frequency division module is used for receiving the working clock signal of the measuring equipment and dividing the frequency of the working clock signal to obtain a counting clock signal.
8. The clock calibration apparatus of claim 1, wherein the control unit is a PID control unit for determining the calibration control signal using a PID control method based on a difference between a period of the pulse-per-second synchronization signal and a target period.
9. The clock calibration apparatus of claim 1, wherein the calibration module comprises:
the digital-to-analog converter is used for converting the calibration control signal into an analog control voltage;
a voltage controlled oscillator for generating a reference clock frequency value corresponding to the analog control voltage based on the analog control voltage;
and the phase-locked loop is used for generating a working clock signal of the measuring equipment based on the reference clock frequency value.
10. A measurement device, comprising:
the main measurement module is used for collecting and processing signals based on working clock signals of the measurement equipment;
the clock calibration device according to any one of claims 1 to 9, which is configured to calibrate an operating clock signal of the measurement device after receiving an externally input calibration instruction.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117240394A (en) * | 2023-11-16 | 2023-12-15 | 北京无线电测量研究所 | Synchronous calibrating device between transceiver chip channels |
| CN118100913A (en) * | 2024-04-17 | 2024-05-28 | 浙江大学 | Method and system for fractional frequency division of encoder |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117240394A (en) * | 2023-11-16 | 2023-12-15 | 北京无线电测量研究所 | Synchronous calibrating device between transceiver chip channels |
| CN117240394B (en) * | 2023-11-16 | 2024-01-19 | 北京无线电测量研究所 | Synchronous calibrating device between transceiver chip channels |
| CN118100913A (en) * | 2024-04-17 | 2024-05-28 | 浙江大学 | Method and system for fractional frequency division of encoder |
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