CN118100913A - Method and system for fractional frequency division of encoder - Google Patents
Method and system for fractional frequency division of encoder Download PDFInfo
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- CN118100913A CN118100913A CN202410461311.1A CN202410461311A CN118100913A CN 118100913 A CN118100913 A CN 118100913A CN 202410461311 A CN202410461311 A CN 202410461311A CN 118100913 A CN118100913 A CN 118100913A
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- 230000001186 cumulative effect Effects 0.000 claims description 13
- 238000007493 shaping process Methods 0.000 claims description 6
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- 230000008569 process Effects 0.000 claims description 2
- 238000001514 detection method Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 6
- 230000000630 rising effect Effects 0.000 description 3
- 230000007480 spreading Effects 0.000 description 3
- 238000003491 array Methods 0.000 description 1
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Abstract
The invention relates to the technical field of digital frequency division circuits, in particular to a method and a system for fractional frequency division of an encoder, which comprises the following steps that S1, a Schmitt trigger receives a pulse signal of the encoder; s2, the clock synchronization circuit performs clock synchronization on the pulse signal shaped by the Schmitt trigger according to the clock CLK signal; s3, the accumulated counting frequency dividing circuit obtains clock count values of adjacent periods of the pulse signals after clock synchronization according to the pulse width counter, the clock count values are multiplied by the frequency dividing coefficient to obtain pulse periods after frequency division, and counting is achieved through the accumulated counter, so that single clock period pulses after frequency division are obtained; s4, the pulse extension circuit extends the single clock period pulse output by the accumulated counting frequency division circuit into a designated width or dynamically adjusts according to the output of the pulse width counter to obtain an extended pulse signal output by frequency division. The frequency dividing error is continuously corrected, so that the aim of more accurate counting is fulfilled, and the frequency dividing accuracy can be effectively improved.
Description
Technical Field
The invention relates to the technical field of digital frequency dividing circuits, in particular to a method and a system for dividing fractional frequency of an encoder.
Background
In vehicle-mounted or motion control, an encoder is often mounted at the tail end of a motion shaft, and a common photoelectric encoder, a magnetic encoder and the like are used for outputting pulses with a fixed number of pulses per circle, and in some applications, such as ultrasonic detection, the encoder needs to be subjected to fractional frequency division, such as triggering or counting every few millimeters according to a physical distance in ultrasonic detection, and the encoder needs to be subjected to fractional frequency division to meet the requirement of generating a triggering pulse with a length of 1 mm.
In ultrasonic detection, triggering is performed every time at a fixed physical distance (e.g., 1 mm), which is a common configuration. However, since the encoder at the end of the scanning axis has N fixed pulses per turn (for example 1024 pulses/turn), the physical distance corresponding to each pulse is very difficult to be an integer, and often is a fractional frequency division coefficient greater than 1. The common fractional frequency division method is a dual-mode pre-frequency division method, which is realized based on variable frequency division and multiple average, for example, frequency division with a frequency division coefficient of 5.4 is realized by dividing the frequency of 10 periodic pulses by 54 clock cycles, and the frequency division can be performed for 6 times and 5 times and 6 times within 54 clock cycles. However, this method has disadvantages: in the low-speed state, the frequency dividing method has larger error or has overlarge error and discontinuous pulse interval in the case of strict frequency division.
In view of the above, the present invention provides a method and system for fractional frequency division of an encoder.
Disclosure of Invention
Aiming at the defects of the prior art, the invention provides a fractional frequency division method and a fractional frequency division system of an encoder, which can achieve the aim of more accurate counting by continuously correcting frequency division errors, can effectively improve the accuracy of frequency division, and can not accumulate errors by utilizing software control.
In order to solve the technical problems, the following technical scheme is adopted:
the method for dividing the fractional frequency of the encoder is characterized by comprising the following steps:
s1, a Schmitt trigger receives a pulse signal of an encoder and shapes the pulse signal;
S2, the clock synchronization circuit performs clock synchronization on the pulse signal shaped by the Schmitt trigger according to a clock CLK signal;
s3, the accumulated count frequency dividing circuit obtains clock count values of adjacent periods of the pulse signals after clock synchronization according to the pulse width counter, the clock count values are utilized to multiply the frequency dividing coefficients to obtain pulse periods after frequency division, and counting is achieved through the accumulated counter, so that single clock period pulses after frequency division are obtained;
S4, the pulse extension circuit extends the single clock period pulse output by the accumulated counting frequency division circuit into a designated width or dynamically adjusts according to the output of the pulse width counter to obtain an extended pulse signal output by frequency division.
On the basis of the technical scheme, the process of expanding the single clock period pulse to the designated width or dynamically adjusting according to the output of the pulse width counter is further improved as follows, and the accumulated count frequency dividing reference number is utilized, and is subtracted when the count time is up, so that the count time is up to each time as a frequency dividing output signal.
Based on the technical scheme, the schmitt trigger is integrated inside a complex programmable logic device or realized by a discrete chip device.
On the basis of the technical scheme, the clock synchronization circuit is arranged in a complex programmable logic device or a field programmable gate array.
On the basis of the technical scheme, the clock synchronization circuit is realized through two or more stages of latches or built by using discrete logic devices.
Based on the technical scheme, the accumulated count frequency dividing circuit is realized in a field programmable gate array or a complex programmable logic device through a code generating hardware circuit.
On the basis of the technical scheme, the pulse extension circuit is realized in a field programmable gate array or a complex programmable logic device through a code generation hardware circuit.
On the basis of the technical scheme, the pulse width counter is realized in a field programmable gate array or a complex programmable logic device through a code generation hardware circuit.
The invention provides another technical scheme: a system for fractional frequency division of an encoder, comprising:
Schmitt trigger: the device is used for receiving the pulse signal of the encoder and shaping the pulse signal;
Clock synchronization circuit: according to a clock CLK signal, carrying out clock synchronization on the pulse signal after shaping the Schmitt trigger;
An accumulated count frequency dividing circuit: the pulse width counter is used for obtaining a clock count value of an adjacent period of the pulse signal after clock synchronization, multiplying the clock count value by a frequency division coefficient to obtain a pulse period after frequency division, and realizing counting through the accumulation counter to obtain a single clock period pulse after frequency division;
And the pulse extension circuit is used for extending the single clock period pulse output by the cumulative count frequency division circuit into a designated width or dynamically adjusting according to the output of the pulse width counter to obtain an extended pulse signal output by frequency division.
On the basis of the technical scheme, the pulse width counter is further improved and is used for calculating the number of clock cycles between two pulse signals.
Due to the adoption of the technical scheme, the method has the following beneficial effects:
The invention provides a novel method and a system for fractional frequency division of an encoder in sound wave detection, which can realize arbitrary fractional frequency division larger than 1. The method is particularly suitable for occasions such as frequency division of the encoder signal and using the frequency-divided signal as an acquisition trigger signal. Compared with the conventional dual-mode prepositive frequency division method, the method has the advantages in frequency division accuracy and continuity, and particularly in dynamic occasions with faster speed, the method can smoothly carry out pulse counting frequency division, so that the frequency division pulse interval continuously changes along with the speed.
Drawings
The invention is further described below with reference to the accompanying drawings:
Fig. 1 is a schematic diagram of an apparatus for fractional frequency division of an encoder in ultrasonic detection according to an embodiment of the present invention.
Fig. 2 is a schematic diagram of a clock synchronization circuit according to an embodiment of the invention.
Fig. 3 is a schematic diagram of a state counter used in the pulse width counter according to the embodiment of the present invention.
Fig. 4 is a schematic diagram of a state machine function of a pulse width counter according to an embodiment of the present invention.
Detailed Description
The present invention will be further described in detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the detailed description and specific examples, while indicating the invention, are intended for purposes of illustration only and are not intended to limit the scope of the invention. In addition, in the following description, descriptions of well-known structures and techniques are omitted so as not to unnecessarily obscure the present invention.
Referring to fig. 1, a method for encoder fractional frequency division in ultrasonic detection, comprising the steps of:
s1, a Schmitt trigger 101 receives a pulse signal of an encoder and shapes the pulse signal;
s2, the clock synchronization circuit 102 performs clock synchronization on the pulse signal shaped by the Schmitt trigger according to a clock CLK signal;
s3, the accumulated count frequency dividing circuit 103 obtains clock count values of adjacent periods of the pulse signals after clock synchronization according to the pulse width counter 105, multiplies the clock count values by a frequency dividing coefficient to obtain pulse periods after frequency division, and realizes counting through the accumulated counter to obtain single clock period pulses after frequency division;
S4, the pulse extension circuit 104 extends the single clock period pulse output by the cumulative count frequency division circuit 103 into a designated width or dynamically adjusts according to the output of the pulse width counter 105 to obtain an extended pulse signal output by frequency division.
As a further explanation of the present embodiment, the procedure for developing a specified width or dynamically adjusting the pulse width counter 105 output is as follows: the cumulative count frequency division reference number is subtracted every time a count time arrives to count the time as a frequency division output signal.
As a further illustration of this embodiment, the schmitt trigger 101 is integrated within a complex programmable logic device or implemented by a discrete chip device. In this embodiment, the schmitt trigger 101 may be SN74LVC1G17.
As a further illustration of this embodiment, the clock synchronization circuit 102 is disposed within a complex programmable logic device or within a field programmable gate array.
As a further illustration of this embodiment, the clock synchronization circuit 102 is implemented by two or more stages of latches or built with discrete logic devices.
As a further explanation of the present embodiment, the cumulative count frequency divider circuit 103 is implemented in a field programmable gate array or in a complex programmable logic device by a code generation hardware circuit.
As a further illustration of this embodiment, the pulse stretcher 104 is implemented within a field programmable gate array or within a complex programmable logic device by code generation hardware circuitry. The pulse extension circuit 104 described above may also be implemented using a dedicated chip, such as the SN74LS123 chip.
As a further illustration of this embodiment, the pulse width counter is implemented within a field programmable gate array or within a complex programmable logic device by code generation hardware circuitry.
As a further illustration of this embodiment, the complex programmable logic device described above may be replaced with an FPGA chip.
The embodiment is applied to the encoder, but the invention of the method is not limited to encoder signals, and also comprises the application fields of sound wave detection, motion control, robots and the like, and can be applied to any field in which the frequency division coefficient is larger than 1 to carry out fractional frequency division. The method is particularly suitable for occasions such as frequency division of the encoder signal and using the frequency-divided signal as an acquisition trigger signal. Compared with the conventional dual-mode prepositive frequency division method, the method has the advantages in frequency division accuracy and continuity, and particularly in dynamic occasions with faster speed, the method can smoothly carry out pulse counting frequency division, so that the frequency division pulse interval continuously changes along with the speed.
The method has the following advantages:
(1) The pulse width counter 105 is used to dynamically count and measure the signal interval time, and the pulse width is multiplied by the frequency division coefficient to be used as a reference of accumulated count frequency division.
(2) With the cumulative count division reference number, every time the count time arrives, the cumulative count division reference number is subtracted to count the time each time as the divided output signal.
(3) By using the accumulated counting mode, the pulse interval after frequency division is stable and smooth, and especially in the occasion of rapid speed change, the frequency division is more accurate.
The invention provides another technical scheme: an apparatus for fractional frequency division of an encoder in ultrasonic detection, comprising:
Schmitt trigger 101: for receiving the pulse signal of the encoder and shaping said pulse signal.
Clock synchronization circuit 102: according to a clock CLK signal, carrying out clock synchronization on the pulse signal after shaping the Schmitt trigger; accurate time difference sampling and delay control of the CLK signal and the pulse signal are achieved. The schematic diagram of the clock synchronization circuit 102 is shown in fig. 2, and a 2-stage flip-flop is used. It should be noted that for situations where latency requirements are not high, 3 or more stages of flip-flops may be used for synchronization.
Cumulative count frequency dividing circuit 103: the pulse width and the frequency division coefficient for the single clock period are obtained by the pulse width counter 105, the pulse period after frequency division is obtained, and the counting is realized by the accumulation counter, so that the pulse with the single clock period after frequency division is obtained.
The cumulative count frequency dividing pseudo code of the cumulative count frequency dividing circuit 103 is as follows, assuming that the clock signal is CLK. Let the pulse width counter output be N, representing N clock cycles. Let acc_counter be the accumulation counter. Let C be the counter value required for frequency division.
Cumulative count divide pseudocode:
3.1 IF (reset or | en) acc_counter=0, ELSE continues;
3.2 Calculating a C=N×frequency division coefficient D, wherein N is the clock period output by the pulse width counter, and the clock period is calculated by 105;
3.3 Rising edge for each CLK clock cycle
IF counter acc_counter is greater than or equal to C
acc_counter = acc_counter– C
ELSE
acc_counter = acc_counter + 1
IF acc_counter is greater than or equal to C, a single clock cycle pulse is output and ELSE continues.
The pulse spreading circuit 104 is used for spreading the single clock cycle pulse output by the cumulative count frequency division circuit 103 into a designated width or dynamically adjusting according to the output of the pulse width counter 105 to obtain a frequency-division output eye spreading pulse signal.
The pulse width extension circuit can be realized by an application specific integrated circuit such as SN74LS123, and can also be realized by a code generation hardware circuit, the specific code realization can be realized by a counter, and the counting period can be set to a fixed pulse width or set according to 1/2 of the pulse width counting output of the pulse width counter.
On the basis of the technical scheme, the pulse width counter is further improved and is used for calculating the number of clock cycles between two pulse signals. I.e., pulse cycles, are typically implemented in complex programmable logic devices or field programmable gate arrays by code generation hardware circuitry.
The principle of the state counter used for the pulse width counter is referred to fig. 3, and the state machine function of the pulse width counter 105 is referred to fig. 4.
In fig. 3, the state machine is divided into 3 states, corresponding to IDLE (IDLE), S0 and S1 states, en is a state machine enable signal, sig_di is a rising edge (single clock period) pulse signal of 102 output encoder signal, period_time pulse width latch value, period_counter is a pulse width counter value, and its functional diagram is shown in fig. 4.
The pseudo code of the pulse width counter 105 is as follows:
6.1 IF (reset or | en) period_counter=0, period_time=0, else continues;
For each CLK clock cycle rising edge:
6.2 IF IDLE state, period_counter=0, ELSE continues
6.3 IF sig_di occurs
period_time = period_counter
period_counter = 0
ELSE
period_counter = period_counter + 1
The above is only a specific embodiment of the present invention, but the technical features of the present invention are not limited thereto. Any simple changes, equivalent substitutions or modifications made on the basis of the present invention to solve the substantially same technical problems and achieve the substantially same technical effects are encompassed within the scope of the present invention.
Claims (10)
1. The method for dividing the fractional frequency of the encoder is characterized by comprising the following steps:
s1, a Schmitt trigger receives a pulse signal of an encoder and shapes the pulse signal;
S2, the clock synchronization circuit performs clock synchronization on the pulse signal shaped by the Schmitt trigger according to a clock CLK signal;
s3, the accumulated count frequency dividing circuit obtains clock count values of adjacent periods of the pulse signals after clock synchronization according to the pulse width counter, the clock count values are utilized to multiply the frequency dividing coefficients to obtain pulse periods after frequency division, and counting is achieved through the accumulated counter, so that single clock period pulses after frequency division are obtained;
S4, the pulse extension circuit extends the single clock period pulse output by the accumulated counting frequency division circuit into a designated width or dynamically adjusts according to the output of the pulse width counter to obtain an extended pulse signal output by frequency division.
2. The method of encoder fractional frequency division of claim 1, wherein: the process of expanding the single clock cycle pulse to a specified width or dynamically adjusting according to the output of the pulse width counter is as follows, and the accumulated count frequency dividing reference number is used, and the accumulated count frequency dividing reference number is subtracted every time the count time arrives, so that every time the count time arrives as a frequency dividing output signal.
3. The method of encoder fractional frequency division of claim 1, wherein: the schmitt trigger is integrated inside a complex programmable logic device or implemented by a discrete chip device.
4. The method of encoder fractional frequency division of claim 1, wherein: the clock synchronization circuit is disposed within a complex programmable logic device or within a field programmable gate array.
5. The method of encoder fractional frequency division of claim 1, wherein: the clock synchronization circuit is realized by two or more stages of latches or is built by discrete logic devices.
6. The method of encoder fractional frequency division of claim 1, wherein: the cumulative count frequency dividing circuit is realized in a field programmable gate array or a complex programmable logic device through a code generating hardware circuit.
7. The method of encoder fractional frequency division of claim 1, wherein: the pulse extension circuit is realized in a field programmable gate array or a complex programmable logic device through a code generation hardware circuit.
8. The method of encoder fractional frequency division of claim 1, wherein: the pulse width counter is realized in a field programmable gate array or a complex programmable logic device through a code generation hardware circuit.
9. A system for fractional frequency division of an encoder, comprising:
Schmitt trigger: the device is used for receiving the pulse signal of the encoder and shaping the pulse signal;
Clock synchronization circuit: according to a clock CLK signal, carrying out clock synchronization on the pulse signal after shaping the Schmitt trigger;
An accumulated count frequency dividing circuit: the pulse width counter is used for obtaining a clock count value of an adjacent period of the pulse signal after clock synchronization, multiplying the clock count value by a frequency division coefficient to obtain a pulse period after frequency division, and realizing counting through the accumulation counter to obtain a single clock period pulse after frequency division;
And the pulse extension circuit is used for extending the single clock period pulse output by the cumulative count frequency division circuit into a designated width or dynamically adjusting according to the output of the pulse width counter to obtain an extended pulse signal output by frequency division.
10. The system for fractional frequency division of an encoder of claim 9 wherein: the pulse width counter is used for counting the number of clock cycles between two pulse signals.
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| CN202410461311.1A CN118100913A (en) | 2024-04-17 | 2024-04-17 | Method and system for fractional frequency division of encoder |
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