CN117579044A - System and method for dynamically inserting clock period to output PWM signal - Google Patents
System and method for dynamically inserting clock period to output PWM signal Download PDFInfo
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Abstract
The invention discloses a system and a method for dynamically inserting clock cycles to output PWM signals, and relates to the technical field of digital pulse width modulation. Acquiring a delay signal and a frequency division factor; the frequency division factor is the frequency division factor of the low-resolution pulse width modulation signal; obtaining delay precision according to the reference clock period, the delay requirement and the frequency division factor; judging whether the phase shift counter crosses the boundary; if not, accumulating the phase shift counter by a delay precision and then continuously executing the step of judging whether the phase shift counter is out of range; if yes, inserting a reference clock period into the low-resolution pulse width modulation signal according to the delay signal to form a high-resolution pulse width modulation signal, resetting the initial value of the phase shift counter and continuously executing the step of judging whether the phase shift counter is out of range. The invention realizes the non-periodic insertion of the reference clock period under the condition of not changing the working mode of the CPU, and improves the precision of PWM signals.
Description
Technical Field
The invention relates to the technical field of digital pulse width modulation, in particular to a system and a method for dynamically inserting clock cycles to output PWM signals.
Background
Digital pulse width modulation technology is very popular in modern electronic technology application, and is increasingly valued in the industry, and is widely applied to the fields of measurement, communication, industrial control and the like. However, as the precision required by the frequency change is higher and higher, the traditional digital pulse width modulation technology is difficult to meet the requirement of complex application scenes, and the pure improvement of the working frequency of the central processing unit (central processing unit, CPU for short) not only brings about the side effect of power consumption improvement, but also can not meet the design requirement.
How to improve the precision of digital pulse width modulation without changing the working mode of the CPU is a task to be solved.
Disclosure of Invention
The embodiment of the invention aims to provide a system and a method for dynamically inserting clock cycles to output PWM signals, which can be used for inserting reference clock cycles aperiodically under the condition of not changing the working mode of a CPU so as to improve the precision of the PWM signals.
In order to achieve the above object, the embodiment of the present invention provides the following solutions:
a method of dynamically inserting clock cycles to output PWM signals, a system for outputting PWM signals based on dynamically inserting clock cycles, the system outputting high resolution pulse width modulated signals after inputting low resolution pulse width modulated signals, the method comprising:
acquiring a delay signal and a frequency division factor; the frequency division factor is the frequency division factor of the low-resolution pulse width modulation signal;
according to the reference clock period, the delay requirement and the frequency division factor, obtaining delay precision;
judging whether the phase shift counter crosses the boundary;
if not, after accumulating the phase shift counter for one delay precision, continuing to execute the step of judging whether the phase shift counter is out of range;
if yes, inserting a reference clock period into the low-resolution pulse width modulation signal according to the delay signal to form a high-resolution pulse width modulation signal, resetting the initial value of the phase shift counter and continuously executing the step of judging whether the phase shift counter is out of range;
the high resolution pulse width modulation signal outputs a PWM signal for the dynamic insertion clock period.
Optionally, the frequency division factor is obtained by adopting an attempt-approach method, which specifically includes:
phase comparing the delay signal with the low-resolution pulse width modulation signal to obtain a phase difference;
when the phase difference is determined to be smaller than a phase difference threshold value, acquiring the number of minimum cycle granularity activated by the delay signal;
the minimum cycle granularity is the minimum granularity of the reference clock cycle subdivision.
Optionally, the calculation formula of the delay precision is:
wherein T represents the reference clock period, y represents the division factor, T represents the delay precision, M represents the delay requirement, and N represents the minimum period granularity.
Optionally, the determining whether the phase shift counter crosses the boundary specifically includes:
acquiring an accumulated value of delay precision;
performing difference calculation on the accumulated value and the reference clock period to obtain a difference value;
judging whether the absolute value of the difference value is smaller than a delay requirement;
if yes, judging that the phase shift counter is out of range;
if not, judging that the phase shift counter does not cross the boundary.
Optionally, inserting a reference clock period in the low resolution pulse width modulation signal according to the delay signal specifically includes:
acquiring the reference clock period and the delay requirement;
dividing the reference clock period by the delay requirement to obtain a quotient;
judging whether the quotient is a positive integer or not;
if yes, directly inserting a reference clock period;
if not, obtaining the numerical value of the modulus, superposing the numerical value of the modulus on a reference clock period to form a superposition reference clock period, and then inserting the superposition reference clock period.
In order to achieve the above purpose, the embodiment of the present invention further provides the following solutions:
a system for dynamically inserting clock cycles to output PWM signals, comprising:
the HRCAL module is used for acquiring a delay signal;
the frequency division factor register is used for acquiring a frequency division factor; the frequency division factor is the frequency division factor of the low-resolution pulse width modulation signal;
the delay precision register is connected with the frequency division factor register and is used for obtaining delay precision according to the reference clock period, the delay requirement and the frequency division factor;
the comparator is used for judging whether the phase shift counter crosses the boundary;
if not, after accumulating the phase shift counter for one delay precision, continuing to execute the step of judging whether the phase shift counter is out of range;
if yes, inserting a reference clock period into the low-resolution pulse width modulation signal according to the delay signal to form a high-resolution pulse width modulation signal, resetting the initial value of the phase shift counter and continuously executing the step of judging whether the phase shift counter is out of range;
the high resolution pulse width modulation signal outputs a PWM signal for the dynamic insertion clock period.
Optionally, the frequency division factor register acquires the frequency division factor by adopting an attempt-approach method, which specifically includes:
the phase comparison module is used for comparing the phase of the delay signal with the low-resolution pulse width modulation signal to obtain a phase difference;
the first comparator module is used for acquiring the number of minimum cycle granularity activated by the delay signal when the phase difference is smaller than a phase difference threshold value;
the minimum cycle granularity is the minimum granularity of the reference clock cycle subdivision.
Optionally, the calculation formula of the delay precision is:
wherein T represents the reference clock period, y represents the division factor, T represents the delay precision, M represents the delay requirement, and N represents the minimum period granularity.
Optionally, the comparator is specifically configured to:
acquiring an accumulated value of delay precision;
performing difference calculation on the accumulated value and the reference clock period to obtain a difference value;
judging whether the absolute value of the difference value is smaller than a delay requirement;
if yes, judging that the phase shift counter is out of range;
if not, judging that the phase shift counter does not cross the boundary.
Optionally, inserting a reference clock period in the low resolution pulse width modulation signal according to the delay signal specifically includes:
acquiring the reference clock period and the delay requirement;
dividing the reference clock period by the delay requirement to obtain a quotient;
judging whether the quotient is a positive integer or not;
if yes, directly inserting a reference clock period;
if not, obtaining the numerical value of the modulus, superposing the numerical value of the modulus on a reference clock period to form a superposition reference clock period, and then inserting the superposition reference clock period.
In the embodiment of the invention, a delay signal is acquired and a frequency division factor is acquired; obtaining delay precision according to the reference clock period, the delay requirement and the frequency division factor; judging whether the phase shift counter crosses the boundary; if not, after accumulating the phase shift counter for a delay precision, continuing to execute the step of judging whether the phase shift counter is out of range; if yes, inserting a reference clock period into the low-resolution pulse width modulation signal according to the delay signal to form a high-resolution pulse width modulation signal; the high resolution pulse width modulated signal outputs a PWM signal for the dynamic insertion clock period.
Because a reference clock period is inserted into the low-resolution pulse width modulation signal according to the delay signal, the low-resolution pulse width modulation signal is unchanged, and the reference clock period is unchanged, the working frequency of the CPU is unchanged, namely the working mode of the CPU is not changed. Judging whether the phase shift counter crosses the boundary or not, accumulating a delay precision by the phase shift counter when the phase shift counter does not cross the boundary, and inserting a reference clock period in the low-resolution pulse width modulation signal according to the delay signal when the phase shift counter crosses the boundary, so that the reference clock period is inserted aperiodically. The high-resolution pulse width modulation signal outputs a PWM signal for dynamically inserting a clock period, so that the precision of the PWM signal is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions of the prior art, the drawings that are needed in the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a flowchart of a method for dynamically inserting clock cycles to output PWM signals according to an embodiment of the present invention;
FIG. 2 is a detailed step diagram of a method for dynamically inserting clock cycles to output PWM signals according to an embodiment of the present invention;
fig. 3 is a schematic diagram of a system structure for dynamically inserting clock cycles to output PWM signals according to an embodiment of the present invention;
fig. 4 is a schematic waveform diagram of a low-resolution pwm signal, a reference clock period, and a high-resolution pwm signal according to an embodiment of the present invention.
Symbol description:
HRCAL module-1, frequency division factor register-2, delay precision register-3, comparator-4, phase shift counter-5.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The invention aims to provide a system and a method for dynamically inserting clock cycles to output PWM signals, so as to solve the problem of how to improve the precision of digital pulse width modulation under the condition that the working mode of a CPU is not changed.
In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention will be rendered by reference to the appended drawings and appended detailed description.
Fig. 1 illustrates an exemplary flow of the method for dynamically inserting clock cycles to output PWM signals described above, and a system for dynamically inserting clock cycles to output PWM signals based on the system outputs high-resolution PWM signals after low-resolution PWM signals are input. The steps are described in detail below.
Step 1: acquiring a delay signal and a frequency division factor; the division factor is the division factor of the low resolution pulse width modulated signal.
Step 1 may be specifically performed by HRCAL module 1 and division factor register 2. HRCAL module 1 (high precision calibration module) acquires the delay signal. The division factor register 2 acquires a division factor. The division factor is the smallest granularity at which the reference clock cycle can be subdivided.
Step 2: and obtaining the delay precision according to the reference clock period, the delay requirement and the frequency division factor.
Step 2 may be performed by the delay precision register 3 in particular. The process by which the delay accuracy register 3 calculates the delay accuracy will be described in detail below.
In one example, the reference clock period is 10ns and the division factor is 50, then the minimum granularity is the ratio of the reference clock period to the division factor, which is 0.2ns. In other embodiments of the present invention, where the delay requirement is 0.4ns, the delay accuracy is the ratio of the delay requirement to the minimum granularity, which is 2.
Furthermore, the delay period is an integer multiple of the minimum granularity. The delay accuracy is the target value that the application circuit needs to reach. According to the method, a delay signal is acquired after the HRCAL module 1 in the SoC chip is monitored intermittently, the frequency division factor register 2 acquires the frequency division factor, the frequency division factor is written into the frequency division factor register 2 through a CPU, and the subsequent delay precision register 3 is controlled through the frequency division factor register 2.
The value of the division factor register 2 is a reference data, i.e. the smallest granularity of the delay, for the delay precision register 3.
Step 3: it is determined whether the phase shift counter is out of range.
If not, after accumulating the phase shift counter for a delay precision, continuing to execute the step of judging whether the phase shift counter is out of range.
If yes, inserting a reference clock period into the low-resolution pulse width modulation signal according to the delay signal to form a high-resolution pulse width modulation signal, resetting the initial value of the phase shift counter and continuously executing the step of judging whether the phase shift counter is out of range.
The high resolution pulse width modulated signal outputs a PWM signal for the dynamic insertion clock period.
Step 3 may be performed in particular by the execution comparator 4 and the phase shift counter 5.
In one example, the comparator 4 is used to determine whether the phase shift counter 5 is out of range.
If the phase shift counter 5 does not cross the boundary, the accumulated value is obtained by accumulating the phase shift counter 5 for one delay precision, and then the step of judging whether the phase shift counter 5 crosses the boundary is continued.
If the phase shift counter 5 is out of range, inserting a reference clock period into the low-resolution pulse width modulation signal according to the delay signal to form a high-resolution pulse width modulation signal, resetting the initial value of the phase shift counter 5, namely resetting the accumulated value, and continuously executing the step of judging whether the phase shift counter 5 is out of range.
The high resolution pulse width modulated signal outputs a PWM signal for the dynamic insertion clock period.
In summary, the delay signal is obtained and the frequency division factor is obtained; obtaining delay precision according to the reference clock period, the delay requirement and the frequency division factor; judging whether the phase shift counter crosses the boundary; if not, after accumulating the phase shift counter for a delay precision, continuing to execute the step of judging whether the phase shift counter is out of range; if yes, inserting a reference clock period into the low-resolution pulse width modulation signal according to the delay signal to form a high-resolution pulse width modulation signal; the high resolution pulse width modulated signal outputs a PWM signal for the dynamic insertion clock period.
Because a reference clock period is inserted into the low-resolution pulse width modulation signal according to the delay signal, the low-resolution pulse width modulation signal is unchanged, and the reference clock period is unchanged, the working frequency of the CPU is unchanged, namely the working mode of the CPU is not changed. Judging whether the phase shift counter crosses the boundary or not, accumulating a delay precision by the phase shift counter when the phase shift counter does not cross the boundary, and inserting a reference clock period in the low-resolution pulse width modulation signal according to the delay signal when the phase shift counter crosses the boundary, so that the reference clock period is inserted aperiodically. The high-resolution pulse width modulation signal outputs a PWM signal for dynamically inserting clock cycles, so that the precision of the PWM signal is improved, and the precision of the whole circuit can be ensured when the delay period is an integer multiple of the minimum granularity due to the fact that the inserted high-precision delay is an integer multiple of the frequency division factor of the reference clock cycle.
In addition, reusability of the implementation circuit is increased, all steps can be realized through the register, so that the register can be preconfigured before the implementation, the circuit can be reused according to different application scenes, and custom development is not needed.
Referring to fig. 2, in other embodiments of the present invention, the division factor is obtained by adopting a trial-and-error method, which specifically includes:
and comparing the phase of the delay signal with the phase of the low-resolution pulse width modulation signal to obtain a phase difference.
And when the phase difference is smaller than the phase difference threshold value, acquiring the number of minimum cycle granularity activated by the delay signal.
The minimum cycle granularity is the minimum granularity of the reference clock cycle subdivision.
In one example, the delay signal is shown in fig. 3, the phase difference is shown in fig. 3, and the phase difference threshold is a value corresponding to the reference clock period. And comparing the phase of the delay signal with that of the low-resolution pulse width modulation signal to obtain a phase difference, and when the phase difference is smaller than the reference clock period, covering or adjusting the phase of the delay signal to be the phase corresponding to the number of the activated minimum period granularity. The minimum cycle granularity is the minimum granularity of the reference clock cycle subdivision.
In other embodiments of the present invention, the calculation formula of the delay precision is:
wherein T represents a reference clock period, y represents a division factor, T represents delay accuracy, M represents delay requirement, and N represents minimum period granularity.
In one example, the reference clock period is 10ns and the division factor is 50, then the minimum granularity is the ratio of the reference clock period to the division factor, which is 0.2ns. The delay requirement is 0.4ns, then the delay accuracy is the ratio of the delay requirement to the minimum granularity, which is 2.
In other embodiments of the present invention, determining whether the phase shift counter 5 crosses the boundary specifically includes:
acquiring an accumulated value of delay precision;
performing difference calculation on the accumulated value and the reference clock period to obtain a difference value;
judging whether the absolute value of the difference value is smaller than the delay requirement;
if yes, judging that the phase shift counter is out of range;
if not, the phase shift counter is judged not to cross the boundary.
In one example, the accumulated value of the delay precision is obtained first and then multiplied by the value of the minimum granularity, and then the accumulated value is recorded as an accumulated value, and then the difference value is calculated with the reference clock period, so as to obtain the absolute value of the difference value. If the absolute value of the difference is smaller than the delay requirement, the phase shift counter is judged to be out of range. If the absolute value of the difference is not less than the delay requirement, the phase shift counter is judged to be not out of range.
In other embodiments of the present invention, inserting a reference clock period in a low resolution pulse width modulated signal based on a delay signal specifically includes:
acquiring a reference clock period and a delay requirement;
dividing the reference clock period by the delay requirement to obtain a quotient;
judging whether the quotient is a positive integer or not;
if yes, directly inserting a reference clock period;
if not, obtaining the numerical value of the modulus, superposing the numerical value of the modulus on a reference clock period to form a superposition reference clock period, and then inserting the superposition reference clock period.
Referring to fig. 4, the delay accuracy and the minimum granularity of 0.2ns obtained above are superimposed, and the accumulated value slowly approaches to one reference clock cycle, for example, 0.2ns is added each time, then 10ns is generated after 50 times, and at this time, it is determined that the delay accuracy approaches to one reference clock cycle, and one reference clock cycle needs to be inserted immediately.
If the quotient value is not a positive integer, the numerical value of the modulus is also required to be configured, the numerical value of the modulus is superimposed on the reference clock period to form a superimposed reference clock period, and the superimposed reference clock period is inserted to complete clock period insertion.
The quotient value is a positive integer, the modulus value is 0, the quotient value is not a positive integer, and the modulus value is not 0, but the modulus value which is not 0 needs to be accumulated to the reference clock period and cannot be discarded. For example, a reference clock period of 100ns is required, the minimum granularity is 30ns, then a phase difference of 10ns remains after 3 delays, the phase difference of 10ns being the modulus value, and then the next reference clock period is actually calculated from 110ns, i.e. 100ns plus the phase difference of 10 ns. The reference clock period becomes 120ns at the third cycle, which is then divisible. The numerical value of the modulus is also dynamically changing.
In order to achieve the above purpose, the embodiment of the present invention further provides the following solutions:
a system for dynamically inserting clock cycles to output PWM signals, as shown in fig. 3, at least comprises: HRCAL module 1, division factor register 2, delay precision register 3, comparator 4, phase shift counter 5.
HRCAL module 1 is used to acquire the delay signal.
In an example, please refer to the above for the detailed description of HRCAL module 1, and the detailed description is omitted here.
The frequency division factor register 2 is used for acquiring a frequency division factor; the division factor is the division factor of the low resolution pulse width modulated signal.
In one example, please refer to the above for the detailed description of the division factor register 2, and the detailed description is omitted here.
The delay precision register 3 is connected with the frequency division factor register 2, and the delay precision register 3 is used for obtaining delay precision according to the reference clock period, the delay requirement and the frequency division factor.
In one example, please refer to the above for detailed description of the delay precision register 3, and a detailed description is omitted here.
The comparator 4 is used for judging whether the phase shift counter 5 crosses the boundary;
if not, after accumulating the phase shift counter 5 for a delay precision, continuing to execute the step of judging whether the phase shift counter 5 is out of range;
if yes, inserting a reference clock period into the low-resolution pulse width modulation signal according to the delay signal to form a high-resolution pulse width modulation signal, resetting an initial value of the phase shift counter and continuously executing the step of judging whether the phase shift counter crosses the boundary;
the high resolution pulse width modulated signal outputs a PWM signal for the dynamic insertion clock period.
In one example, the low resolution pwm signal is based on a reference clock count, the period of the low resolution pwm signal can only be an integer multiple of the reference clock period, and to achieve a high resolution pwm signal, a minimum granularity, such as one eighth of the reference clock period, requires that the minimum granularity (one eighth of the reference clock period) be inserted on an integer multiple count of each reference clock period. After eight accurate delays, a reference clock period is inserted, and a reference clock period is also required to be dynamically inserted into the low-resolution pulse width modulation signal at the moment, so that the phase difference caused by the accurate delays is compensated, and the normal generation of the next high-resolution pulse width modulation signal is ensured.
The division factor register 2 obtains the division factor by adopting an attempt-approach method, and specifically comprises the following steps: the phase comparison module is used for comparing the phase of the first signal.
The phase comparison module is used for comparing the phase of the delay signal with the phase of the low-resolution pulse width modulation signal to obtain a phase difference.
The first comparator module is used for acquiring the number of minimum cycle granularity activated by the delay signal when the phase difference is smaller than the phase difference threshold value.
The minimum cycle granularity is the minimum granularity of the reference clock cycle subdivision.
In an example, please refer to the above for description of the minimum period granularity, and the description is omitted here.
The calculation formula of the delay precision is as follows:
wherein T represents a reference clock period, y represents a division factor, T represents delay accuracy, M represents delay requirement, and N represents minimum period granularity.
In an example, please refer to the above for the calculation process of the delay precision, which is not described herein.
The comparator 4 is specifically configured to:
acquiring an accumulated value of delay precision;
performing difference calculation on the accumulated value and the reference clock period to obtain a difference value;
judging whether the absolute value of the difference value is smaller than the delay requirement;
if yes, judging that the phase shift counter is out of range;
if not, the phase shift counter is judged not to cross the boundary.
In an example, please refer to the above for a description of determining whether the phase shift counter 5 is out of range, and a description thereof is omitted herein.
Inserting a reference clock period in the low resolution pulse width modulated signal based on the delay signal specifically includes:
acquiring a reference clock period and a delay requirement;
dividing the reference clock period by the delay requirement to obtain a quotient;
judging whether the quotient is a positive integer or not;
if yes, directly inserting a reference clock period;
if not, obtaining the numerical value of the modulus, superposing the numerical value of the modulus on a reference clock period to form a superposition reference clock period, and then inserting the superposition reference clock period.
In one example, please refer to the above for the description of inserting one reference clock period in the low resolution pwm signal according to the delay signal, and the description is omitted here.
In the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other. For the system disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant points refer to the description of the method section.
The principles and implementations of the embodiments of the present invention have been described herein with reference to specific examples, the description of the above examples being only for the purpose of aiding in the understanding of the methods of the embodiments of the present invention and the core ideas thereof; also, it is within the spirit of the embodiments of the present invention for those skilled in the art to vary from one implementation to another and from application to another. In view of the foregoing, this description should not be construed as limiting the embodiments of the invention.
Claims (10)
1. A method of dynamically inserting clock cycles to output PWM signals, the method comprising:
acquiring a delay signal and a frequency division factor; the frequency division factor is the frequency division factor of the low-resolution pulse width modulation signal;
according to the reference clock period, the delay requirement and the frequency division factor, obtaining delay precision;
judging whether the phase shift counter crosses the boundary;
if not, after accumulating the phase shift counter for one delay precision, continuing to execute the step of judging whether the phase shift counter is out of range;
if yes, inserting a reference clock period into the low-resolution pulse width modulation signal according to the delay signal to form a high-resolution pulse width modulation signal, resetting the initial value of the phase shift counter and continuously executing the step of judging whether the phase shift counter is out of range;
the high resolution pulse width modulation signal outputs a PWM signal for the dynamic insertion clock period.
2. The method for dynamically inserting clock cycles to output PWM signals according to claim 1, wherein the division factor is obtained by an approach-try method, comprising:
phase comparing the delay signal with the low-resolution pulse width modulation signal to obtain a phase difference;
when the phase difference is determined to be smaller than a phase difference threshold value, acquiring the number of minimum cycle granularity activated by the delay signal;
the minimum cycle granularity is the minimum granularity of the reference clock cycle subdivision.
3. The method for dynamically inserting clock cycles to output PWM signals according to claim 2, wherein the calculation formula of the delay accuracy is:
wherein T represents the reference clock period, y represents the division factor, T represents the delay precision, M represents the delay requirement, and N represents the minimum period granularity.
4. The method for dynamically inserting clock cycles to output PWM signals according to claim 1, wherein determining whether the phase shift counter is out of range comprises:
acquiring an accumulated value of delay precision;
performing difference calculation on the accumulated value and the reference clock period to obtain a difference value;
judging whether the absolute value of the difference value is smaller than a delay requirement;
if yes, judging that the phase shift counter is out of range;
if not, judging that the phase shift counter does not cross the boundary.
5. The method of dynamically inserting clock cycles to output a PWM signal according to claim 1, wherein inserting a reference clock cycle in the low resolution pulse width modulated signal based on the delay signal comprises:
acquiring the reference clock period and the delay requirement;
dividing the reference clock period by the delay requirement to obtain a quotient;
judging whether the quotient is a positive integer or not;
if yes, directly inserting a reference clock period;
if not, obtaining the numerical value of the modulus, superposing the numerical value of the modulus on a reference clock period to form a superposition reference clock period, and then inserting the superposition reference clock period.
6. A system for dynamically inserting clock cycles to output PWM signals, comprising:
the HRCAL module is used for acquiring a delay signal;
the frequency division factor register is used for acquiring a frequency division factor; the frequency division factor is the frequency division factor of the low-resolution pulse width modulation signal;
the delay precision register is connected with the frequency division factor register and is used for obtaining delay precision according to the reference clock period, the delay requirement and the frequency division factor;
the comparator is used for judging whether the phase shift counter crosses the boundary;
if not, after accumulating the phase shift counter for one delay precision, continuing to execute the step of judging whether the phase shift counter is out of range;
if yes, inserting a reference clock period into the low-resolution pulse width modulation signal according to the delay signal to form a high-resolution pulse width modulation signal, resetting the initial value of the phase shift counter and continuously executing the step of judging whether the phase shift counter is out of range;
the high resolution pulse width modulation signal outputs a PWM signal for the dynamic insertion clock period.
7. The system for dynamically inserting clock cycles to output a PWM signal according to claim 6, wherein the division factor register obtains the division factor using a trial-and-error approach method, comprising:
the phase comparison module is used for comparing the phase of the delay signal with the low-resolution pulse width modulation signal to obtain a phase difference;
the first comparator module is used for acquiring the number of minimum cycle granularity activated by the delay signal when the phase difference is smaller than a phase difference threshold value;
the minimum cycle granularity is the minimum granularity of the reference clock cycle subdivision.
8. The system for dynamically inserting clock cycles to output a PWM signal according to claim 7, wherein the delay accuracy is calculated by the formula:
wherein T represents the reference clock period, y represents the division factor, T represents the delay precision, M represents the delay requirement, and N represents the minimum period granularity.
9. The system for dynamically inserting clock cycles to output a PWM signal according to claim 6, wherein the comparator is specifically configured to:
acquiring an accumulated value of delay precision;
performing difference calculation on the accumulated value and the reference clock period to obtain a difference value;
judging whether the absolute value of the difference value is smaller than a delay requirement;
if yes, judging that the phase shift counter is out of range;
if not, judging that the phase shift counter does not cross the boundary.
10. The system for dynamically inserting clock cycles to output a PWM signal according to claim 6, wherein inserting a reference clock cycle in the low resolution pulse width modulated signal based on the delay signal comprises:
acquiring the reference clock period and the delay requirement;
dividing the reference clock period by the delay requirement to obtain a quotient;
judging whether the quotient is a positive integer or not;
if yes, directly inserting a reference clock period;
if not, obtaining the numerical value of the modulus, superposing the numerical value of the modulus on a reference clock period to form a superposition reference clock period, and then inserting the superposition reference clock period.
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| CN202310286592.7A CN117579044A (en) | 2023-03-23 | 2023-03-23 | System and method for dynamically inserting clock period to output PWM signal |
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| CN202310286592.7A CN117579044A (en) | 2023-03-23 | 2023-03-23 | System and method for dynamically inserting clock period to output PWM signal |
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