CN116482959A - Segmented time-to-digital converter, control method, medium, equipment and terminal - Google Patents

Segmented time-to-digital converter, control method, medium, equipment and terminal Download PDF

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CN116482959A
CN116482959A CN202310499001.4A CN202310499001A CN116482959A CN 116482959 A CN116482959 A CN 116482959A CN 202310499001 A CN202310499001 A CN 202310499001A CN 116482959 A CN116482959 A CN 116482959A
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chain
time
delay
digital converter
measured
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蔡超
汪飞
周嘉雯
谢庆国
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Huazhong University of Science and Technology
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Huazhong University of Science and Technology
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    • G—PHYSICS
    • G04—HOROLOGY
    • G04F—TIME-INTERVAL MEASURING
    • G04F10/00—Apparatus for measuring unknown time intervals by electric means
    • G04F10/005—Time-to-digital converters [TDC]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
    • Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

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Abstract

The invention belongs to the technical field of time interval measurement, and discloses a sectional time-to-digital converter, a control method, a medium, equipment and a terminal, wherein the structure of a delay chain is changed, and a plurality of short parallel chains are utilized to measure the 'thin' time of a signal to be measured in a TDL TDC; different fixed delay treatments are introduced before each short chain, so that each short chain essentially performs parallel measurement on different areas of a signal to be measured, wherein the number of chain lengths is determined according to clock conditions and measurement areas of each chain. The control method of the sectional time-digital converter has good linearity, and the whole long chain skillfully puts all delay units in one logic block in a folding way, so that the problem of nonlinearity caused by inconsistent wire lengths which are led across a plurality of resource blocks is completely avoided; the sectional time-digital converter has the advantages of simple structure, high resource utilization rate, good robustness, insensitivity to the change of devices and channels and capability of correcting the drift introduced by temperature on line.

Description

Segmented time-to-digital converter, control method, medium, equipment and terminal
Technical Field
The invention belongs to the technical field of time interval measurement, and particularly relates to a sectional time-to-digital converter, a control method, a medium, equipment and a terminal.
Background
Currently, a time-to-digital converter (Time to Digital Converter, TDC) is a high-precision (picosecond-level) time interval measurement unit, and is widely used in a variety of industrial application fields including nuclear physics, automotive vehicles, medical imaging, and the like. Simple TDCs can roughly characterize the time interval by counting the number of clocks that go through using a high frequency clock signal, however the resolution of this approach is limited by the clock frequency, typically in the nanosecond range.
Existing TDC schemes can be divided into analog schemes and digital schemes. Analog schemes, including time stretching or time-to-amplitude conversion. On the one hand, the analog schemes need to use analog quantity in the implementation, and the analog quantity is easily influenced by signal fluctuation; on the other hand, the single measurement time of these schemes is often much longer than the time interval to be measured, i.e. the longer conversion rate, which results in too long dead time to perform high frequency measurements. Thus, although they can achieve considerable Integrated Non-linear (INL) performance, even sub-picosecond time resolution, they are less common. In contrast, digital schemes are more popular because they can be deployed and iterated (on FPGA) faster, have a more compact hardware architecture, are flexible, and are more tolerant of noise interference. Thus, digital TDC solutions are more popular.
The first digital solution is an interpolation method, also called Nutt method. Interpolation methods utilize multiple delay cells (typically carry modules in FPGAs) to interpolate the system clock. In this method, a series of delay cell stages are connected in series to form a long chain (also called a tapped delay line, tapped Delay Line, TDL), the measurement of which is often referred to as "fine" time. In the Nutt method, a system clock is used to perform rough measurement on a time interval to be measured, and the time to be measured is divided into an integer number of clock components and a fraction number of clock components. The integer clock component is obtained by counting, while the fractional clock component is obtained by the number of triggered delay elements in the TDL chain. In the method, the delay time caused by each delay unit in the TDL chain can be obtained in advance through code density measurement, and the triggering quantity of the units can be obtained through measurement, so that the value of the 'thin' time can be obtained, and the final time interval can be obtained by matching with the value of the 'thick' time obtained by the system clock.
The precondition of this method is that each delay unit has the same delay, which also determines the time resolution of the measurement. However, the characteristics of these delay cells are susceptible to device inherent defects, power and temperature dynamics, etc., resulting in serious non-linearity problems. At the same time, the inherent delay of each cell is determined by its manufacturing process and cannot be modified. Thus, once the hardware platform is determined, the time resolution of the TDC has been determined. To solve these problems, vernier methods, multi-chain averaging topologies, waveUnion architecture, and bin-to-bin calibration have been proposed.
While these approaches can improve performance in some aspects of TDC, they tend to introduce other problems. For example, the vernier method can greatly alleviate nonlinear defects existing in the device, improve time resolution, and even exceed the inherent time delay of the delay unit, but the vernier method requires more logic resources and longer conversion rate. The multi-chain average topology does not increase dead time, but occupies more resources than the vernier method. The WaveUnion approach, while saving resources, requires a complex ring oscillator design whose performance depends on non-uniformity among delay cells. However, as semiconductor manufacturing processes are advanced, such non-uniformities have not been serious. The bin-to-bin calibration method only alleviates the nonlinear problem of the delay unit, has poor expansibility, and needs to be reprocessed when changing the channel position or replacing the hardware platform.
The above-described problems can be significantly solved using a TDC design with Application-specific integrated circuits (ASICs). While these ASIC-oriented solutions generally achieve satisfactory performance, they require, on the one hand, higher manufacturing costs and longer design cycles, and therefore the technology is slow to iterate, with a significant limitation on the development speed; on the other hand, they cannot be reused, resulting in poor flexibility. Thus, only experienced and resource-rich communities have a strong choice of ASIC-based solutions. This phenomenon may inhibit innovation to some extent, so many TDC designs tend to first be verified using FPGA and then batch-stream with ASCI.
Conventional TDCs tend to string delay cells together in a straight line. For example, the TDC based on the FPGA is formed by taking a carry unit of the FPGA as a delay unit in a string. To ensure that the resources on the TDC chain are able to fully "interpolate" the system clock, the requirement that the overall delay chain produce an inherent delay greater than the clock period of the counter is often referred to as a clock condition. The delay generated by the whole delay chain is determined by the inherent delay of each delay unit and the total number of delay units, so when the precision of the delay units is high under the condition of fixed counter clock, the number of delay units needs to be ensured to be large, and the traditional single-chain TDC is also caused to be long in series on the FPGA, which also causes the following technical problems:
(1) The linearity is poor. Ideal TDCs require the same transfer delay between each delay element to ensure high linearity. However, only delay units in the same resource block can guarantee good consistency in practice; delay cells between different resource blocks cause serious non-linearity problems due to the large variability of the wiring resources.
(2) The error is large. When the TDC chain length is too long, this can lead to the problem of "bubbles", i.e. when a signal passes through one chain, all delay elements it has experienced are theoretically triggered, i.e. the output should be all "1" (or conversely "0"), whereas when the chain length is long, there may be many "0" s in the trigger segment of all "1", which will seriously disturb the measurement result of the TDC.
(3) The robustness is poor. The inherent delay time of the delay unit is greatly influenced by temperature, and when the temperature change is large, the linearity of the delay unit in the chain is influenced, the integral inherent delay is offset, and errors are caused to measurement.
Through the above analysis, the problems and defects existing in the prior art are as follows:
(1) The existing TDC simulation scheme needs to use analog quantity in the implementation, and the analog quantity is easily influenced by signal fluctuation; meanwhile, the single measurement time of the existing TDC simulation scheme is often far higher than the time interval to be measured, namely, the longer conversion rate, which leads to overlong dead time and incapability of measuring high frequency.
(2) The existing vernier method needs more logic resources and longer conversion rate, and the multi-chain average topology occupies more resources; the WaveUnion approach requires a complex ring oscillator design, the performance of which depends on the non-uniformity between delay cells; the bin-to-bin calibration method can only alleviate the nonlinear problem of the delay unit, has poor expansibility, and needs to be reprocessed when changing the channel position or replacing the hardware platform.
(3) In the existing TDC digital scheme, the characteristics of a delay unit are easily influenced by inherent defects of a device, dynamic changes of power and temperature and the like, so that serious nonlinear problems are caused; meanwhile, the inherent delay of each delay cell is determined by its manufacturing process and cannot be modified.
(4) The existing ASIC-oriented solution requires higher manufacturing cost and longer design period, has slow technical iteration and greatly limits the development speed; the device cannot be reused, so that the flexibility is poor, and innovation steps are restrained; however, the conventional TDC has problems of poor linearity, large error and poor robustness.
Disclosure of Invention
Aiming at the problems existing in the prior art, the invention provides a sectional type time-to-digital converter, a control method, a medium, equipment and a terminal.
The invention is realized in such a way that a control method of a sectional type time-to-digital converter comprises the following steps: changing the structure of a delay chain, and measuring the thin time of a signal to be measured in the TDL TDC by utilizing a plurality of short parallel chains; different fixed delay treatments are introduced before each short chain, so that each short chain essentially performs the purpose of parallel measurement on different areas of the signal to be measured.
Further, the number of chain lengths is determined by the clock conditions and the measurement intervals of each chain.
Further, the control method of the segmented time-to-digital converter further includes:
in the 'fine' time measurement of a signal to be measured by utilizing a plurality of parallel short chains, a chain 1 is connected with the signal to be measured, and the front sides of the chain 1 and the chain 2 are both connected with delay units for generating fixed delay time, wherein the delay time delta t configured by the delay units before the chain 2 d2 Longer than the delay time deltat caused by the delay cells in chain 1 d1 ，Δt d2 ＞Δt d1 。
Further, the delay cells in front of the chain are two different logical resources than the delay cells in the chain;
the delay units before the chain are single or multiple delay units configured by software, and are IDELAY resources in the Xilinx FPGA; while the delay elements in the chain use the CARRY4/8 resources.
Further, the measurement range Mτ of chain 1 and the delay time generated by the two pre-chain delay units satisfy the condition Mτ > Δt d2 -Δt d1 Where M is the number of delay cells and τ is the delay time fixed for each delay cell. The measurement range of the chain 2 is the same as that of the chain 1, the total measurement time of the chain 1 and the chain 2 is 2Mτ, and the clock condition 2Mτ > T is satisfied.
Further, when the signal with the time interval Δt is input, if Δt is smaller than mτ, any one chain can finish measuring the signal to be measured, the number of delay units triggered on the chain is counted, and when the number is N, the signal to be measured is Δt=nτ; if the time interval T > Δt > =mτ, the measurement process is completed by two chains, where T is the system clock. The Mτ fraction is measured from the first strand and the other strand is measured as Mτ', the final measurement is (M+Mτ) - (Mτ - (Δt) d2 -Δt d1 ))＝M'τ+(Δt d2 -Δt d1 ) The method comprises the steps of carrying out a first treatment on the surface of the When delta T is more than T, the system clock is divided into two parts for measurement, wherein one part is an integer part of the system clock, and the other part is a decimal part of the system clock; the integer part is implemented by a counting function, while the fractional part is measured using a plurality of parallel short chains.
Another object of the present invention is to provide a segmented time-to-digital converter using the control method of the segmented time-to-digital converter, where the segmented time-to-digital converter includes a plurality of short chains and delay units connected before the short chains, and the delay units are used to generate a fixed delay time; measuring the thin time of a signal to be measured in the TDL TDC by using a plurality of short chains; different fixed delay treatments are introduced before each short chain, so that each short chain essentially performs the purpose of parallel measurement on different areas of the signal to be measured.
It is a further object of the invention to provide a computer device comprising a memory and a processor, the memory storing a computer program which, when executed by the processor, causes the processor to perform the steps of the method of controlling a segmented time-to-digital converter.
Another object of the present invention is to provide a computer-readable storage medium storing a computer program which, when executed by a processor, causes the processor to perform the steps of the method for controlling a segmented time-to-digital converter.
Another object of the present invention is to provide an information data processing terminal for implementing the segmented time-to-digital converter.
In combination with the technical scheme and the technical problems to be solved, the technical scheme to be protected has the following advantages and positive effects:
first, aiming at the technical problems in the prior art and the difficulty of solving the problems, the technical problems solved by the technical proposal of the invention are analyzed in detail and deeply by tightly combining the technical proposal to be protected, the results and data in the research and development process, and the like, and some technical effects brought after the problems are solved have creative technical effects. The specific description is as follows:
1. the linearity is good. The control method of the sectional time-digital converter provided by the invention skillfully places all delay units in one logic block in a folding mode, thereby completely avoiding the problem of nonlinearity caused by inconsistent line length introduced by crossing a plurality of resource blocks.
2. Simple structure and high resource utilization rate. The sectional time-to-digital converter has a simple structure, and only needs a fixed delay unit and a plurality of short chains arranged in one logic resource block, wherein the fixed delay unit can be compacter in layout due to a shorter chain length, and the waste layout space is less. In contrast, long chain resources are inherently scarce, and when long chains are laid out in a limited space, the unused portion may not be able to re-distribute the next long chain. This is similar to memory allocation in a computer system, long chains are equivalent to empty regions with contiguous large block addresses, while short chains are equivalent to small segments of memory distributed in different spaces. The continuous memory with large block addresses is a well-known scarce resource, which is very limited, while the free memory of small pieces is more, and if the small pieces of memory can be utilized to form the free memory of large blocks, the resource utilization rate is necessarily higher.
3. The robustness is good, the device and the channel are insensitive to the change of the device and the channel, and the drift introduced by the temperature can be corrected on line. In the manufacturing process of the device, the resources with similar spatial positions have better similarity, namely better consistency, and the property still holds when the device is changed or the channel is changed. Therefore, the TDC established based on the resources with similar spatial positions has better consistency of time delay of each delay unit, and the consistency of the delay units is not destroyed when the device or the channel is changed, so that the TDC provided by the invention has better robustness. In addition, logic resources with configurable delay time, such as IDELAY in Xilinx FPGA, are not sensitive to temperature change, and a differential measurement unit can be formed by utilizing the insensitive resources and matching with a plurality of short chains; the number of the delay units triggered under different temperature conditions can be measured by matching with pulse signals with known time (the pulse signals can be easily provided in the FPGA through a PLL), so that the inherent delay time of a single delay unit under different temperature conditions can be obtained, and the influence of the temperature is compensated.
Secondly, the technical scheme is regarded as a whole or from the perspective of products, and the technical scheme to be protected has the following technical effects and advantages:
(1) The technical effects are as follows: as can be known from the experimental effect of TDC in code density test, the INL and DNL of the segmented time-to-digital converter structure provided by the invention are obviously superior to the traditional structure; and both INL and DNL are lower than 0.5LSB, but traditional schemes are as high as 1.5LSB; the smaller the INL and DNL, the better the linearity and the better the performance.
(2) The technical advantages are that: the TDC is used as a time measuring tool, the accuracy of measurement needs to be ensured, and factors influencing the accuracy mainly comprise the resolution and linearity of the TDC.
Thirdly, as inventive supplementary evidence of the claims of the present invention, the following important aspects are also presented:
(1) The technical scheme of the invention fills the technical blank in the domestic and foreign industries: the traditional time-to-digital converter has poor linearity, poor robustness, complex structure and low resource utilization rate. In order to solve the problem of linearity and time resolution, more resources are needed to be introduced, so that the utilization rate of the resources is low, and the complexity of the structure is also improved; or require a lot of effort to calibrate, making robustness very poor. Although there is an improvement in performance, these additional costs tend to be forgotten and can be difficult to popularize, especially in a multi-channel scenario. The segmented time-to-digital converter provided by the invention fills the blank of the prior art.
(2) The technical scheme of the invention solves the technical problems that people are always desirous of solving but are not successful all the time: the prior method always aims to solve the nonlinear problem in the TDC, however, excessive time cost or resource cost is introduced to solve the nonlinear problem, and the TDC structure provided by the invention can perfectly solve the nonlinear problem without calibrating (i.e. without additional time cost and calculation cost) under the condition of not consuming more resources.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments of the present invention will be briefly described below, and it is obvious that the drawings described below are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of a control method of a segmented time-to-digital converter according to an embodiment of the present invention;
FIG. 2 is a basic schematic diagram of a "fine" time measurement of a signal to be measured using a plurality of parallel short chains provided by an embodiment of the present invention;
FIG. 3 is a schematic diagram of a "fine" time measurement section provided by an embodiment of the present invention;
fig. 4A is a graph of experimental effects of a TDC according to an embodiment of the present invention in a code density test;
fig. 4B is a graph of experimental results of the TDC according to the embodiment of the present invention in the DNL test;
fig. 4C is a graph showing experimental results of the TDC according to the embodiment of the present invention in the INL test.
Detailed Description
The present invention will be described in further detail with reference to the following examples in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
Aiming at the problems existing in the prior art, the invention provides a sectional type time-to-digital converter, a control method, a medium, equipment and a terminal, and the invention is described in detail below with reference to the accompanying drawings.
As shown in fig. 1, the control method of the segmented time-to-digital converter provided by the embodiment of the invention includes the following steps:
s101, changing the structure of a delay chain, and measuring the thin time of a signal to be measured in a TDL TDC by using a plurality of short parallel chains;
s102, different fixed delay treatments are introduced before each short chain, so that each short chain essentially performs parallel measurement on different areas of the signal to be measured.
The core idea of the invention is to change the structure of the delay chain, measure the 'thin' time in the TDL TDC by using a plurality of short parallel chains, and the delay time caused by the short chains is short, so that the clock condition cannot be met by a single short chain. Therefore, different fixed delay treatments are introduced before each short chain, so that each short chain essentially performs the purpose of parallel measurement on different areas of the signal to be measured. The basic measurement process is described by taking two short chains as models, and in an actual implementation process, more than two short chains may be required, and how many specific chain lengths are required is determined according to clock conditions and how large each chain can measure.
As shown in fig. 2, a basic schematic diagram of the present invention for performing "fine" time measurement on a signal to be measured using a plurality of parallel short chains is shown. In FIG. 2, chain 1 is directly connected to the signal under test, wherein a delay unit is connected in front of each of chains 1 and 2 for generating a fixed delay time, wherein the delay units are configured to delay at in front of chain 2 d2 Longer than the delay time Deltat caused by the delay cells in chain 1 d1 I.e. Δt d2 ＞Δt d1 . Note that here the delay cells in front of the chain are two different logical resources than the delay cells in the chain. The delay unit before the chain is a single or a plurality of delay units which can be configured by software, taking an Xilinx FPGA as an example, and can be an IDELAY resource; while delay elements in the chain often use CARRY4/8 resources.
At the same time, the measurement range Mτ of chain 1 and the delay time generated by the two pre-chain delay units should satisfy Mτ > Δt d2 -Δt d1 Where M is the number of delay cells and τ is the delay time fixed for each cell. The measurement range of chain 2 may be the same as in chain 1 for simplicity of processing. The measured time for chain 1 and chain 2 to join together, i.e., 2mτ, should satisfy the clock condition, i.e., 2mτ > T.
When a signal with a time interval of Δt is input, if Δt is less than mτ, any one chain can complete measurement of the signal to be measured, at this time, only the number of delay units triggered on the chain needs to be counted, and assuming N, the signal to be measured is Δt=nτ. If the time interval T > Δt > =mτ, then the measurement process requires two chains to be completed, where T is the system clock.
Wherein the Mτ fraction is measured by the first strand and the other strand assumes a measurement of M 'τ, then the final measurement is (M+M') τ - (Mτ - (Δt) d2 -Δt d1 ))＝M'τ+(Δt d2 -Δt d1 ). When Δt > T, it can be divided into two parts, one part being an integer part of the system clock and one part being a fractional part of the system clock when measured. The integer part can be realized by a counting function, while the fractional part can be measured by a plurality of parallel short chains.
The sectional time-to-digital converter provided by the embodiment of the invention comprises a plurality of short chains and delay units connected before the short chains, wherein the delay units are used for generating fixed delay time; measuring the thin time of a signal to be measured in the TDL TDC by using a plurality of short chains; different fixed delay treatments are introduced before each short chain, so that each short chain essentially performs the purpose of parallel measurement on different areas of the signal to be measured.
The invention can be applied in a number of different fields, such as nuclear physics, automotive vehicles, medical imaging, etc. In nuclear physics, if high-energy particle tracking needs to accurately measure the flight time of particles, the high linearity of the invention can obviously improve the measurement accuracy in application; the radar is required to be used for detecting vehicle information in the automobile, and the detection precision can be improved by applying the method and the device; in medical imaging, for example, the PET detector is required to accurately measure the flight time of gamma photons, the high linearity of the invention can obviously improve the accuracy of gamma photon flight time measurement, and the PET detector is provided with dozens of signal reading channels, so that dozens of TDCs are required to be integrated, and the high resource utilization rate and the high robustness of the invention can obviously reduce the difficulty of multi-channel TDC integration.
The embodiment of the invention has a great advantage in the research and development or use process, and has the following description in combination with data, charts and the like of the test process.
A specific implementation procedure of the embodiment of the present invention is described by taking Xilinx Ultrascale FPGA as an example. The TDC of the invention has the same measuring principle as TDL TDC, namely, when the system clock measures coarse time, the delay chain resource measures fine time, and the invention innovatively updates the measuring structure of fine time, so that only the measuring process of fine time is described.
A schematic diagram of a system implementation is shown in fig. 3. The whole system comprises a parallel short chain consisting of 6 IDELAY units and 120 CARRY8 units. Where IDELAY employs a clustered hierarchical structure, the latency of each cluster is marked in the graph. 120 CARRY8 constitute 4 short chains, each CARRY8 having a delay time of only about 30ps, so that each short chain has a measurement range of only 900ps. The above settings satisfy the clock condition: 600-0<900，1200-600<900，1800-1200<900，120*30＝3600ps>T=2.5 ns, i.e. 400MHz system clock. In operation, the time interval to be measured can be obtained by detecting the trigger state on each chain. Let the delay units before each chain be: delta T 1 ,ΔT 2 ,ΔT 3 ,ΔT 4 The inherent delay of the delay element on each short chain is τ and the number of delay elements on each chain is M, then the "fine" time is measured as follows:
(1) Detecting the positions of the '01' jump edge, namely the rising edge and the tail part of the signal, the '10' jump edge, namely the falling edge and the beginning of the signal, on each short chain, wherein the positions are respectively P 01 ,P 10 The positions of the two signals on the chain are C respectively 01 ,C 10 Wherein is less than or equal to 1P 01 ,P 10 ≤30，1≤C 01 ,C 10 ≤4。
(2) Determining the number of system clocks experienced between the '01' jump edge and the '10' jump edge as N respectively 01 ,N 10 。
(3) If N 01 ＝N 10 Two scenarios are discussed: when C 01 ＝C 10 At the time Δt= (P 10 -P 01 ) τ; when C 01 ≠C 10 ，
(4) If N 01 ≠N 10 Then
The experimental effect of the TDC in the code density test provided by the embodiment of the present invention is shown in fig. 4A to 4B, where the light gray portion is the code density test result of the TDC provided by the present invention, and the dark gray portion is the test result of the conventional structure. As can be seen from fig. 4A to 4B, the INL and DNL of the proposed structure are significantly superior to the conventional structure. Under the structure proposed by the invention, INL and DNL are both lower than 0.5LSB, but the traditional scheme is as high as 1.5LSB; the smaller the INL and DNL, the better the linearity and the better the performance.
In fig. 3, input represents an Input signal; IODELAY unit represents a delay unit that introduces a fixed delay, where IODELAY is the name of the resource employed at instantiation; similarly, the CARRY8 unit is a delay unit for making subdivision measurements, and CARRY8 is the name of the resource used in instantiation.
It should be noted that the embodiments of the present invention can be realized in hardware, software, or a combination of software and hardware. The hardware portion may be implemented using dedicated logic; the software portions may be stored in a memory and executed by a suitable instruction execution system, such as a microprocessor or special purpose design hardware. Those of ordinary skill in the art will appreciate that the apparatus and methods described above may be implemented using computer executable instructions and/or embodied in processor control code, such as provided on a carrier medium such as a magnetic disk, CD or DVD-ROM, a programmable memory such as read only memory (firmware), or a data carrier such as an optical or electronic signal carrier. The device of the present invention and its modules may be implemented by hardware circuitry, such as very large scale integrated circuits or gate arrays, semiconductors such as logic chips, transistors, etc., or programmable hardware devices such as field programmable gate arrays, programmable logic devices, etc., as well as software executed by various types of processors, or by a combination of the above hardware circuitry and software, such as firmware.
The foregoing is merely illustrative of specific embodiments of the present invention, and the scope of the invention is not limited thereto, but any modifications, equivalents, improvements and alternatives falling within the spirit and principles of the present invention will be apparent to those skilled in the art within the scope of the present invention.

Claims (10)

1. A control method of a segmented time-to-digital converter, characterized in that the control method of the segmented time-to-digital converter comprises: changing the structure of a delay chain, and measuring the thin time of a signal to be measured in the TDL TDC by utilizing a plurality of short parallel chains; different fixed delay treatments are introduced before each short chain, so that each short chain essentially performs the purpose of parallel measurement on different areas of the signal to be measured.
2. The control method of a segmented time to digital converter according to claim 1, wherein the number of chain lengths is determined according to a clock condition and a measurement interval of each chain.
3. The control method of a segmented time-to-digital converter according to claim 1, wherein the control method of a segmented time-to-digital converter further comprises:
in the 'fine' time measurement of a signal to be measured by utilizing a plurality of parallel short chains, a chain 1 is connected with the signal to be measured, and the front sides of the chain 1 and the chain 2 are both connected with delay units for generating fixed delay time, wherein the delay time delta t configured by the delay units before the chain 2 d2 Longer than the delay time deltat caused by the delay cells in chain 1 d1 ，Δt d2 ＞Δt d1 。
4. The control method of a segmented time-to-digital converter according to claim 1, wherein the delay unit before the chain and the delay unit in the chain are two different logic resources;
the delay units before the chain are single or multiple delay units configured by software, and are IDELAY resources in the Xilinx FPGA; while the delay elements in the chain use the CARRY4/8 resources.
5. A method of controlling a segmented time-to-digital converter according to claim 3, wherein the measurement range mτ of chain 1 and the delay time generated by the two pre-chain delay units satisfy the condition mτ > Δt d2 -Δt d1 Where M is the number of delay units, τ is the delay time fixed for each delay unit; the measurement range of the chain 2 is the same as that of the chain 1, the total measurement time of the chain 1 and the chain 2 is 2Mτ, and the clock condition 2Mτ > T is satisfied.
6. The control method of a segmented time-to-digital converter according to claim 5, wherein when a signal with a time interval Δt is input, if Δt < mτ, any one chain can complete measurement of a signal to be measured, and only the number of delay units triggered on the chain is counted; when the number is N, the signal to be measured is Δt=nτ; if the time interval T > delta T > =Mτ to be measured, the measurement process is completed by utilizing the matching of two chains, wherein T is the system clock; the Mτ fraction is measured from the first strand and the other strand is measured as Mτ', the final measurement is (M+Mτ) - (Mτ - (Δt) d2 -Δt d1 ))＝M'τ+(Δt d2 -Δt d1 ) The method comprises the steps of carrying out a first treatment on the surface of the When deltat > T, the system clock is divided into an integer part and a decimal part for measurement, the integer part of the system clock is realized through a counting function, and the decimal part of the system clock is measured by utilizing a plurality of parallel short chains.
7. A segmented time-to-digital converter applying the control method of the segmented time-to-digital converter according to any one of claims 1 to 6, characterized in that the segmented time-to-digital converter comprises a plurality of short-chain and short-chain pre-connected delay units for generating a fixed delay time; measuring the thin time of a signal to be measured in the TDL TDC by using a plurality of short chains;
different fixed delay treatments are introduced before each short chain, so that each short chain essentially performs the purpose of parallel measurement on different areas of the signal to be measured.
8. A computer device comprising a memory and a processor, the memory storing a computer program which, when executed by the processor, causes the processor to perform the steps of the method of controlling a segmented time-to-digital converter as claimed in any one of claims 1 to 6.
9. A computer readable storage medium storing a computer program which, when executed by a processor, causes the processor to perform the steps of the method of controlling a segmented time-to-digital converter according to any one of claims 1 to 6.
10. An information data processing terminal, characterized in that the information data processing terminal is arranged to implement the segmented time-to-digital converter as claimed in claim 7.
CN202310499001.4A 2023-05-05 2023-05-05 Segmented time-to-digital converter, control method, medium, equipment and terminal Pending CN116482959A (en)

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