CN108594933B - Calibration method for measuring inherent error of TDC (time-to-digital converter) time interval - Google Patents

Calibration method for measuring inherent error of TDC (time-to-digital converter) time interval Download PDF

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CN108594933B
CN108594933B CN201810259312.2A CN201810259312A CN108594933B CN 108594933 B CN108594933 B CN 108594933B CN 201810259312 A CN201810259312 A CN 201810259312A CN 108594933 B CN108594933 B CN 108594933B
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CN108594933A (en
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张钰
胡万鹏
王建利
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Miyin Hangzhou Information Technology Co Ltd
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Hangzhou Electronic Science and Technology University
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    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/02—Digital function generators
    • G06F1/022—Waveform generators, i.e. devices for generating periodical functions of time, e.g. direct digital synthesizers
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Abstract

The invention discloses a calibration method for measuring an inherent error of a TDC time interval. The existing calibration method for measuring the inherent error at the time interval can increase the complexity of the structure of the whole measuring system and has poor reconstruction. The method designs a random signal required by code density calibration according to the source of TDC inherent error; the random signal is composed of different pulse width signals so as to simulate a time interval signal to be measured with a random width in actual measurement; and testing the delay chain by using the random signal to obtain a test sample, analyzing the sample data to obtain the bit width error of the delay chain unit, and calibrating. The invention ensures the cycle sequence of the random sequence on the premise of preventing deadlock, and ensures the original cycle sequence to be unchanged on the premise of adding an all-zero state.

Description

Calibration method for measuring inherent error of TDC (time-to-digital converter) time interval
Technical Field
The invention belongs to the technical field of signal processing, and particularly relates to a calibration method for measuring an inherent error at a TDC time interval.
Background
The high-precision time interval measurement technology is widely applied to the fields of fluorescence life detection, quantum communication, aerospace, high-energy physical research, global navigation systems, high-sensitivity sensors and the like. The main components of TDC (time measurement system) include coarse measurement and fine measurement. The error source of the TDC is mainly divided into two parts: intrinsic errors due to process imperfections, measurement errors due to variations in pressure, voltage and temperature parameters. The former mostly adopts an improved system structure to perform error compensation, and the latter mostly adopts a search technical manual to perform error compensation.
At present, calibration methods for measuring inherent errors at intervals are also available, but most of the calibration methods are realized by improving the circuit structure of the measuring system, but the schemes increase the complexity of the whole measuring system structure and have poor reconstruction.
Disclosure of Invention
The invention aims to provide a calibration method for measuring the intrinsic error of TDC time interval, which is reconfigurable and has a simple structure.
The invention relates to a calibration method for measuring an inherent error at a TDC time interval, which comprises the following specific steps:
generating random signal with random pulse width by random signal generator, simulating time interval signal to be measured in actual measurement by using pulse signal with random pulse width in random signal, and generating random signalInputting a signal into a delay chain, recording an output state value of a delay chain unit at the arrival time of a falling edge of a random signal, judging the position of the delay chain unit corresponding to the output state value, then adding one to a pulse counter corresponding to the delay chain unit at the position to obtain a test sample consisting of events recorded by each unit of the delay chain, and counting the number n of the events recorded by the (i + 1) th unit in the delay chainiAnd the total number N of the test samples, wherein i is 0,1,2, …, M, the total number N of the test samples is the sum of the times that the random signal is detected in each unit of the delay chain, then the number M +1 of the delay chain units is combined, the nonlinear characteristic INL (i) of the bit width of the delay chain units is obtained based on the code density calibration principle, and finally the bit width nonlinear error delta is calculated according to INL (i)i＝INL(i)×ΔτiWherein, Δ τiObtaining the bit width of the ith unit of the delay chain after calibration for the bit width of the ith unit of the delay chain before calibration
Figure BDA0001609834910000011
Linear feedback shift register in random signal generator0Register R1Register R2And a register R3Composition is carried out; setting the leap step length of the linear feedback shift register to L, and the feedback logic of the linear feedback shift register
Figure BDA0001609834910000021
j is 1,2,3 or 4, based on the initialization vector Q0＝(Q0(0),Q0(1),Q0(2),Q0(3) To obtain:
Figure BDA0001609834910000022
obtaining a state transition matrix A according to a set feedback function f (x), and then obtaining:
Figure BDA0001609834910000024
the output sequence of the first stage is: q. q.s1＝[q1(0),q1(1),q1(2),q1(3)]Wherein:
Figure BDA0001609834910000025
the output sequence of the second stage is: q. q.s2＝[q2(0),q2(1),q2(2),q2(3)]Wherein:
Figure BDA0001609834910000026
the output sequence of the third stage is: q. q.s3＝[q3(0),q3(1),q3(2),q3(3)]Wherein:
Figure BDA0001609834910000027
the output sequence of the fourth stage is: q. q.s4＝[q4(0),q4(1),q4(2),q4(3)]Wherein:
Figure BDA0001609834910000028
to this end, a random number sequence q is appliedj(0) J 1,2,3 or 4 as register R0Is a random number sequence qj(1) J 1,2,3 or 4 as register R1Is a random number sequence qj(2) J 1,2,3 or 4 as register R2Is a random number sequence qj(3) J 1,2,3 or 4 as register R3The output value of (1).
The generation of the random signal is done by a direct digital frequency synthesizer (DDS) in a random signal generator,wherein q isj(0),qj(1),qj(2) And q isj(3) As a frequency control word for the phase accumulator in the DDS.
The invention has the following beneficial effects:
1. the invention designs the random signal required by code density calibration according to the source of the TDC inherent error. The random signal is composed of different pulse width signals so as to simulate a time interval signal to be measured with a random width in actual measurement. And testing the delay chain by using the random signal to obtain a test sample, analyzing the sample data to obtain the bit width error of the delay chain unit, and calibrating.
2. The invention improves the measurement precision of the TDC measurement system by reducing the miscounting rate and bit width error.
3. The invention adds feedback logic fb0Ensuring the cycle sequence of the random sequence on the premise of preventing deadlock; adding feedback logic fb1And fb2And the original circulation sequence is ensured to be unchanged on the premise of adding an all-zero state (ensuring balance of 0 and 1 in a random sequence).
Drawings
FIG. 1 is a schematic diagram of a TDC measurement technique in the present invention.
Fig. 2 is a flowchart of the error calibration operation of the present invention.
Fig. 3 is a schematic circuit diagram of a linear feedback shift register according to the present invention.
Detailed Description
The invention is further described below with reference to the accompanying drawings.
The invention provides a calibration method for measuring an inherent error of a TDC time interval, which is used for reducing the inherent measurement error of a TDC measurement system caused by process defects.
Referring to fig. 1, the time difference between the rising edge of the signal S1 and the rising edge of the signal S2 is the time interval T to be measured, and the measurement process of the time interval T to be measured is as follows:
the signal C is used as a driving signal of the delay chain and a counting clock of the coarse counter, so that the output state value of each unit of the delay chain is changed; upon arrival of signal S1, the first fine counter is on signal CThe rising edge arrival time records and latches the output state values of the units of the delay chain at the moment, and the rough counter performs an adding operation. When the signal S2 comes, the second fine counter records and latches the output state values of the cells of the delay chain at the time when the rising edge of the signal C comes, stops the counting operation of the coarse counter, and latches the counting result of the coarse counter. Obtaining a measuring result T of the time interval T to be measured according to the recording results of the coarse counter, the first fine counter and the second fine counterMeasuring＝N×T0+△t1-△t2Wherein, T0Is the period of the signal C which is the system reference clock signal, N is the integral number of periods of the signal C counted by the coarse counter △ t1The product of the result and the ideal bit width of the delay chain element is recorded for the first fine counter, △ t2The product of the result and the ideal bit width of the delay chain unit is recorded for the second fine counter.
Referring to fig. 2, a calibration method for measuring an intrinsic error at a TDC time interval includes the following steps:
generating random signals with random pulse widths by a random signal generator, simulating a time interval signal to be measured in actual measurement by using the pulse signals with random pulse widths in the random signals, inputting the random signals into a delay chain, recording output state values of delay chain units at the arrival time of falling edges of the random signals, judging the positions of the delay chain units corresponding to the output state values, adding one to pulse counters corresponding to the delay chain units at the positions to obtain test samples consisting of events recorded by each unit of the delay chain, and counting the number n of the events recorded by the (i + 1) th unit in the delay chainiAnd the total number N of the test samples, wherein i is 0,1,2, …, M, the total number N of the test samples is the sum of the times that the random signal is detected in each unit of the delay chain, then the number M +1 of the delay chain units is combined, the nonlinear characteristic INL (i) of the bit width of the delay chain units is obtained based on the code density calibration principle, and finally the bit width nonlinear error delta is calculated according to INL (i)i＝INL(i)×ΔτiWherein, Δ τiObtaining the bit width of the ith unit of the calibrated delay chain for the bit width of the ith unit of the delay chain before calibrationIs Δ τi*＝Δτi-δi。
Referring to fig. 3, a linear feedback shift register in a random signal generator is composed of a register R0Register R1Register R2And a register R3Composition is carried out; setting the leap step length L of the linear feedback shift register to 4, and the feedback logic f of the linear feedback shift registerb(j)＝fb0(j)⊕fb1(j)⊕fb2(j) J is 1,2,3 or 4, based on the initialization vector Q0＝(Q0(0),Q0(1),Q0(2),Q0(3) To obtain:
Figure BDA0001609834910000041
Figure BDA0001609834910000042
in this embodiment, Q0＝(0,0,0,1)。
When the feedback function is f (x) x4At + x +1, the state transition matrix is:
this gives:
Figure BDA0001609834910000052
the output sequence of the first stage is: q. q.s1＝[q1(0),q1(1),q1(2),q1(3)]Wherein:
Figure BDA0001609834910000053
the output sequence of the second stage is: q. q.s2＝[q2(0),q2(1),q2(2),q2(3)]Wherein:
Figure BDA0001609834910000054
the output sequence of the third stage is: q. q.s3＝[q3(0),q3(1),q3(2),q3(3)]Wherein:
the output sequence of the fourth stage is: q. q.s4＝[q4(0),q4(1),q4(2),q4(3)]Wherein:
Figure BDA0001609834910000056
to this end, a random number sequence q is appliedj(0) J 1,2,3 or 4 as register R0Is a random number sequence qj(1) J 1,2,3 or 4 as register R1Is a random number sequence qj(2) J 1,2,3 or 4 as register R2Is a random number sequence qj(3) J 1,2,3 or 4 as register R3The output value of (1).
The generation of the random signal is done by a direct digital frequency synthesizer (DDS) in the random signal generator. Q is to bej(0),qj(1),qj(2) And q isj(3) When the frequency control word is used as the frequency control word of the phase accumulator in the DDS, the phase increment is changed by taking the frequency control word which is continuously changed by the phase accumulator when the random signal is synthesized, and the different phase increments lead the duty ratios of square wave signals read from the ROM/RAM to be different, thereby generating the random signal with random pulse width required by the invention.
The invention adds feedback logic fb0Ensuring the cycle sequence of the random sequence on the premise of preventing deadlock; adding feedback logic fb1And fb2And the original circulation sequence is ensured to be unchanged on the premise of adding an all-zero state (ensuring balance of 0 and 1 in a random sequence).

Claims (2)

  1. A calibration method for measuring an inherent error at a TDC time interval is characterized in that: the method comprises the following specific steps: generating random signals with random pulse widths by a random signal generator, simulating a time interval signal to be measured in actual measurement by using the pulse signals with random pulse widths in the random signals, inputting the random signals into a delay chain, recording output state values of delay chain units at the arrival time of falling edges of the random signals, judging the positions of the delay chain units corresponding to the output state values, adding one to pulse counters corresponding to the delay chain units at the positions to obtain test samples consisting of events recorded by each unit of the delay chain, and counting the number n of the events recorded by the (i + 1) th unit in the delay chainiAnd the total number N of the test samples, wherein i is 0,1,2, …, M, the total number N of the test samples is the sum of the times that the random signal is detected in each unit of the delay chain, then the number M +1 of the delay chain units is combined, the nonlinear characteristic INL (i) of the bit width of the delay chain units is obtained based on the code density calibration principle, and finally the bit width nonlinear error delta is calculated according to INL (i)i＝INL(i)×ΔτiWherein, Δ τiObtaining the bit width of the ith unit of the delay chain after calibration for the bit width of the ith unit of the delay chain before calibration
    Figure FDA0002272785090000011
  2. 2. The calibration method for TDC time interval measurement of intrinsic error as claimed in claim 1, wherein: linear feedback shift register in random signal generator0Register R1Register R2And a register R3Composition is carried out; setting the leap step length of the linear feedback shift register to L, and the feedback logic of the linear feedback shift registerOr 4, according to the initialization vector Q0＝(Q0(0),Q0(1),Q0(2),Q0(3) Obtained by：
    Figure FDA0002272785090000013
    Figure FDA0002272785090000014
    Obtaining a state transition matrix A according to a set feedback function f (x), and then obtaining:
    Figure FDA0002272785090000015
    the output sequence of the first stage is: q. q.s1＝[q1(0),q1(1),q1(2),q1(3)]Wherein:
    Figure FDA0002272785090000021
    the output sequence of the second stage is: q. q.s2＝[q2(0),q2(1),q2(2),q2(3)]Wherein:
    Figure FDA0002272785090000022
    the output sequence of the third stage is: q. q.s3＝[q3(0),q3(1),q3(2),q3(3)]Wherein:
    Figure FDA0002272785090000023
    the output sequence of the fourth stage is: q. q.s4＝[q4(0),q4(1),q4(2),q4(3)]Wherein:
    Figure FDA0002272785090000024
    to this end, a random number sequence q is appliedj(0) J 1,2,3 or 4 as register R0Is a random number sequence qj(1) J 1,2,3 or 4 as register R1Is a random number sequence qj(2) J 1,2,3 or 4 as register R2Is a random number sequence qj(3) J 1,2,3 or 4 as register R3The output value of (d);
    the generation of the random signal is performed by a direct digital frequency synthesizer (DDS) in a random signal generator, wherein q is divided intoj(0),qj(1),qj(2) And q isj(3) As a frequency control word for a phase accumulator in a direct digital frequency synthesizer.
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CN105183428A (en) * 2015-08-12 2015-12-23 中国电子科技集团公司第四十一研究所 Pseudo-random signal generation method
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