RU2399156C1 - Method of correcting analogue-to-digital conversion errors and device for realising said method - Google Patents

Abstract

FIELD: physics.

SUBSTANCE: device has an input signal source, an analogue signal switch, an amplifier, an analogue-to-digital converter, a control computer system, as well as a zero voltage source and a reference voltage source. Another version of the method of correcting analogue-to-digital conversion errors involves analogue-to-digital conversion of the initial signal and matching it with the reference signal where, before operation (during adjustment) the device is calibrated under normal conditions, involving measurement of the signal which corresponds to zero and measurement of the reference signal. The obtained values are saved in nonvolatile memory in form of a zero code and a standard value code. Measurement during operation is carried out as follows: incoming signals are measured at all inputs, with subsequent low-pass filtering of values obtained in the measurement cycle. In order to reduce effect of noise in the measurement channel, the zero correction code and the gain compensation factor are determined in each measurement cycle, after which measurements are corrected at the measurement inputs.

EFFECT: high accuracy of realising the disclosed method with minimum hardware and software expenses.

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Description

The invention relates to measuring equipment and can be used in information-measuring systems and measuring and computing systems for correcting errors of analog-to-digital conversion associated with zero offset and drift of the gain of the measurement path. The most effective application of this method in multichannel systems for measuring parameters with constant or slowly changing values. The magnitude of the zero offset and the drift of the gain are due to the temperature and time instability of the elements of the measurement path.

Known methods for correcting errors of analog-to-digital conversion, for example, the method [1], which perform analog-to-digital (direct) conversion of the original signal, digital-to-analog (inverse) conversion of the signal, reduced by the value of the model signal of direct conversion of the original signal, the received signal subjected to direct conversion, carry out the inverse transformation of the signal increased by the value of the reference signal of the result of the direct conversion of the original signal obtained from The signal is also subjected to direct conversion, and the adjusted result of the conversion of the original signal is calculated by the mathematical formula.

The described method is implemented using a device containing a control computer complex (UVK), a common bus line, an accurate digital-to-analog converter, a measured signal source, an input analog switch, a group normalizing converter with a non-linear conversion function, an analog and analog switch digital converter.

The disadvantage of this technical solution is the complexity and low speed.

There is also known a method [2], which includes correction based on sequential digital-to-analog and analog-to-digital conversion of signals, followed by storing the result of analog-to-digital conversion in random-access memory, in which the testing process is carried out, at the beginning it is carried out continuously from the moment the analog- D converter 2 for ⁿ clock cycles, followed by latching the test code signal at the output code of the corrected n-bit analog-to-digital th transducer, wherein the test signal is a step function voltage level of the instantaneous value which is proportional to the code number of clock pulses, and in the case of linearization of the complete test period (2 ⁿ clock cycles) will coincide with an idealized characteristic of the analog-digital conversion, wherein during the continuous testing, the correction mode is blocked, and upon completion of continuous testing, the stage of correction of errors in analog-to-digital conversion, correction modes and periodic tests are alternated for one clock cycle, and periodic testing is carried out due to the possible instability of the conversion characteristics of the analog-to-digital converter, while in the correction mode the output code of the analog-to-digital converter serves as an address for outputting a code for the instantaneous voltage value lying on the idealized analog-to-digital conversion characteristic .

The described method is implemented using a device containing a clock generator (GTI), an n-bit binary counter, an (n + 1) -input element I, RAM (2 ⁿ words × n bits), an n-bit digital-to-analog converter, a switch analog signals, adjustable n-bit ADC, divider by two, two-input OR element, n-element key block, while the GTI output is connected to the input of an n-bit binary counter, the outputs of which are simultaneously connected to n inputs of an (n + 1) -input element And, to the inputs of RAM and to the inputs of the n-bit DAC, output which is connected to the second data input of the analog switch, the first information input of which serves as an input device and an output connected to an input of the corrected n-bit ADC, which outputs are addressable RAM inputs; the output of the (n + 1) -and input element AND is connected to the input of the divider by two, whose inverse output is simultaneously connected to the (n + 1) -th input of the (n + 1) -in input element And and with the second input of the two-input element OR, the first input which is connected to the GTI output, and the output is simultaneously connected to the control input of the analog signal switch, the RAM write control input and the n-element key block control input, the outputs of the latter are the device outputs.

The closest in technical essence to the claimed one is a method for correcting errors of analog-to-digital conversion [3], including analog-to-digital (direct) conversion of the original signal, in which the corrected k-bit analog-to-digital converter from the moment of switching is switched to continuous testing mode, which is carried out 2 ^m times (k and m are related by the relation: k = m + n), and the test signal is a step function of the voltage, which varies in the range of input signals of the corrected an analog-to-digital converter and identified with 2 ^m reference signals, the code equivalent of the serial number of which serves as the address of the memory cells of the RAM, into which the output code of the tested analog-to-digital converter is recorded. During continuous testing, the correction mode is blocked. Upon completion of the stage of continuous testing, the stage of correction of errors in analog-to-digital conversion is carried out, characterized by the alternation of two cycles: analysis of the input signal and periodic testing, determined by the order of arrival of groups of 2 ^n-1 pulses. During the analysis of the input signal, an analog-to-digital conversion of the samples of the information input signal and storing of the result are carried out, with periodic testing, the result of the analog-to-digital conversion is simultaneously corrected and the analog-to-digital converter is periodically tested, which is carried out due to the possible instability of the parameters of the working analog-to-digital converter . In the process of continuous testing of the ADC, a correction table is created, in which the values of deviations from the ideal characteristics of the ADC are entered for each value of the DAC code. The correction of the measured value is carried out by the correction value corresponding to the given value of the ADC signal.

The described analog-to-digital conversion correction method is implemented by a device containing a clock pulse generator (GTI), a k-bit binary counter, a control unit, an m-element key block, an m-bit DAC, an analog signal switch, a correctable k-bit ADC, RAM ( 2 ^m words × k bits), k-bit value storage register Y ₁ , calculator, m-bit value storage register U _E1 , m-bit adder, m-element key block, block of three-input OR circuits, k-bit storage register values Y ₂ , k-bit register x injuries of the value Y ₃ , while the GTI output is connected to the input of a k-bit binary counter, k outputs of which are connected to k inputs of the control unit, and m outputs from k (from (n + 1) -th to k-th) are simultaneously connected to m inputs of the key block and m-bit DAC, the output of which is connected to the second information input of the analog signal switch, the first information input of which serves as the input of the device, and the output is connected to the input of the corrected k-bit ADC, k outputs of which are information inputs of RAM and storage register values Y ₁ , k outputs of which are connected to the second group of information inputs of the calculator, and m outputs from k (from (n + 1) -th to k-th) are simultaneously connected to m inputs of the storage register of the value U _Э1 and m inputs of the first group of inputs of the adder , the second group of inputs of which is the input of the least significant bit to which a voltage is applied corresponding to the level of a logical unit.

The disadvantages of the described technical solutions designed to correct the error of the analog-to-digital conversion are significant hardware and software costs for performing compensation, the need to periodically interrupt the measurement process to perform a lengthy continuous testing procedure, as well as the strict requirement for the monotonicity of the ADC conversion characteristics, since otherwise In this case, ambiguities may occur, and accordingly, errors when performing the correction.

The closest in technical essence to a device that implements the proposed method is the device presented in [1].

When creating the claimed invention, the task was to develop a technical solution that allows the correction of errors of zero offset and gain drift caused by the action of temperature and long-term instability of the components used with minimal hardware and software costs.

To solve this problem, when correcting the error of the analog-to-digital conversion, including analog-to-digital conversion of the original signal and its identification with the reference signal, before starting the measurement process, the device is calibrated under normal conditions, including the measurement of the signal corresponding to zero and the measurement of the reference signal, the obtained values are recorded in non-volatile memory in the form of a zero code and a reference value code and are used later in the operation for performing correction of the measurement values obtained with arbitrary departure measuring circuit parameters; during operation, a measurement cycle is carried out, including the measurement of incoming signals for all N + 2 inputs, followed by low-pass filtering of the values obtained in the measurement cycle, to reduce the influence of interference in the measurement path, in each measurement cycle, the zero correction code is determined as the difference in the code of the measured zero value and the code of the zero value obtained during calibration, and the correction coefficient of the gain as the ratio of the difference of the code of the signal value obtained when measuring the signal of the reference source, and the code for correcting zero to the difference between the code for the standard voltage during calibration and the code for zero when calibrating, after which the measurements are corrected for N measuring inputs by multiplying the difference of the value obtained from the N input (N varies from 1 to N), and the code correction of zero to gain correction factor. This method is implemented using a hardware-software complex containing a signal source, N outputs of which are connected to the corresponding measuring N inputs of the analog signal switch, connected via a normalizing amplifier to the input of an analog-to-digital converter, the output of which is connected to the input of the control computer complex, the first output whose bus is connected to the input bus of the analog-to-digital converter, and the second output bus is connected to the input bus of the analog si channels into which an additional source of voltage of zero and a source of reference voltage are added, the outputs of which are connected respectively to the (N + 1) and (N + 2) inputs of the analog signal switch.

The presented technical solution with high linearity of the characteristics of modern ADCs and high stability of the output voltage of modern sources of reference voltage (used as a reference voltage source) allows correcting the errors of zero offset and gain drift caused by temperature and time instability of the elements of the measurement path with the necessary accuracy. simple means.

The invention is illustrated by drawings, in which Fig. 1 is a functional diagram of a device that implements the proposed method for correcting errors of analog-to-digital conversion, Fig. 2 is a diagram explaining the essence of the proposed method.

A device that implements the proposed method contains a source of 1 input (measured) signals, the outputs of which are connected to the measuring N inputs of the switch 2 analog signals, the (N + 1) -th input of which is connected to the output of the source 3 of zero voltage, a (N + 2) the input is connected to the output of the source 4 of the reference voltage, the output of the switch 2 analog signals through a normalizing amplifier 5 is connected to the input of an analog-to-digital converter (ADC) 6, the output of which is connected to the input of the control computer complex (UVK) 7, the first output on the UVK 7 is connected to the input bus of the ADC 6, and the second output bus of the UVK 7 is connected to the input bus of the switch 2 analog signals. Switch 2 analog signals is a channel selector, which can be performed, for example, on an ADG408 analog multiplexer chip, normalizing amplifier 5 can be performed on an operational amplifier chip, analog-to-digital converter 6 is implemented on an ADC chip, the control computing complex 7 is a microcontroller , which can be performed, for example, on a chip type 80C51.

The proposed method using the described device is implemented as follows.

During the setup process (before operation), the device is calibrated under normal conditions, for this, the inputs (N + 1) and (N + 2) of the switch 2 are analog signals, to which the signals from the output of source 3 of zero voltage and source 4 of reference voltage are supplied are connected in series to the input of the normalizing amplifier 5 to perform measurements of the values of these signals. The measurements are carried out using an analog-to-digital converter 6. The measured values are in the form of codes K _{cal. 0} (code of the value of zero during calibration) and K _{cal. floor} (code of the reference voltage during calibration) is stored in the non-volatile memory of the UVK 7. Measurements during operation are performed as follows: measure the signals coming from the outputs of the signal source 1 to the N measuring inputs of the switch 2 analog signals, and from the outputs of the source 3 of zero voltage and source 4 reference voltages - at (N + 1) and (N + 2) inputs of switch 2, respectively. After obtaining the measured values for all (N + 2) inputs, low-frequency filtering of the signals is carried out to reduce the influence of noise and interference in the measurement path. In each measurement cycle, a zero correction code K _{corr. 0} and a gain correction coefficient M _corr . _{U are calculated} using UVK 7:

To _correl . ₀ = To _{meas. 0} - To _{cal. 0} ,

where K _{Izm 0} - code value of the signal obtained by measuring the zero value of the signal from source 3;

M _corre.u = (K _meas. -K _{corre 0} ) / (K _cal. -K _{cal 0} ),

where K _amend. - code value of the signal obtained by measuring the signal of the reference source 4.

Further, to correct the values of the signals obtained by N measuring inputs, carry out software correction of the measured values using UVK 7:

K _corr . _N = (K _{rev. N} -K _corr . ₀ ) M _corr .

where K _{meas. N} is the code of the signal value received from the signal source 1 at the input N (N varies from 1 to N) in the measurement cycle;

K _kopp.N - the adjusted value at the input N (N varies from 1 to N). Thus, the zero correction code and the gain correction coefficient are determined in all measurement cycles, and the measured values are corrected for all measuring inputs from 1 to N. The proposed method using the described device allows the correction of zero offset and coefficient drift errors amplification caused by the action of temperature and long-term instability of the components used with minimal hardware and software costs.

INFORMATION SOURCES

1. RF patent No. 984030, IPC Н03К 13/02, publ. 12/23/1982.

2. RF patent No. 2334355, IPC Н03М 1/10, Н03М 1/06, publ. 09/20/2008.

3. RF patent No. 2352060, IPC Н03М 1/10, publ. 04/10/2009.

Claims (2)

1. A method for correcting errors in analog-to-digital conversion, including analog-to-digital conversion of the original signal and its identification with the reference signal, characterized in that before starting operation during the setup process, the device is calibrated under normal conditions, including measuring the signal corresponding to zero, and measuring reference signal, the obtained values are recorded in non-volatile memory in the form of a zero code and a reference value code and are used later in the operation for correction of measurement values performed with arbitrary departure of the parameters of the measurement circuit, then during operation a measurement cycle is carried out, which includes the measurement of incoming signals for all N + 2 inputs, followed by low-pass filtering of the values obtained in the measurement cycle to reduce the influence of interference in the path measurement, in each measurement cycle, the zero correction code is determined as the difference between the measured zero value code and the zero value code obtained during calibration, and the correction coefficient k gain as the ratio of the difference of the code of the signal value obtained when measuring the signal of the reference source and the zero correction code to the difference of the code of the value of the reference voltage during calibration and the code of the zero value during calibration, after which the measurements are corrected for N measurement inputs by multiplying the difference of the value obtained on the N input (N varies from 1 to N), and a zero correction code for the gain correction factor. 2. A device for correcting errors in analog-to-digital conversion, containing a signal source, N outputs of which are connected to the corresponding measuring N inputs of an analog signal switch, connected via a normalizing amplifier to an input of an analog-to-digital converter, the output of which is connected to the input of a control computer complex, the first whose output bus is connected to the input bus of the analog-to-digital converter, and the second output bus is connected to the input bus of the analog switch signals, characterized in that it introduced a source of zero voltage and a reference voltage source, the outputs of which are connected respectively to the (N + 1) and (N + 2) switch inputs analog signals.

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