SU1679630A1 - Method for calibrating linearity of digital-to-analog converter - Google Patents

Description

The invention relates to electrical engineering and can be used to create precision multi-bit digital-analog (DAC) and analog-to-digital (ADC) converters and control of their production. The purpose of the invention is to improve accuracy. The calibration of the “bit DAC” consists in measuring the differences between the analog output value of the calibrated DAC when I include the first most significant bits and the analog. The invention relates to electrical measuring technology and can be used to create precision multi-digit digital-analog (DAC) and analog-digital (A / D) converters and control of their production.

The purpose of the invention is to improve the accuracy of the calibration of the digital-to-analog converter.

measure and perform πτ = Ν-Ι measurement cycles according to the number of low-order digits of the calibrated DAC. In each k-th cycle of changes, where k is the cycle number, measure the difference between the output analog values of the calibrated and reference DAC when the k-th digit is turned on in that, the difference between the output analog values of the calibrated and reference DAC when the first one turns on in relation to the k-th digit, and in the second - the k-th digit. After measured for all 5 = 2-1 code combinations in the I senior bits of the difference between the output analog values of the reference and calibrated DAC when applying for their senior bits code number I, where G is the cycle number, and turn off the lower bits and the difference between the output analog values the reference and calibrated DAC while maintaining the code at the first, filing for the high bits of the second code I - 1 and turning on its low bits. According to the measurement results, the errors of the group of high-order bits and the errors of the lower bit weights of the calibrated DAC are determined. 1 il.

SP

with

The drawing shows the block diagram of the device that implements the proposed method.

The device contains an additional analog measure 1, an analog switch 2, a reference digital-to-analog converter 3, an input bus 4 of a reference DAC, a calibrated DAC 5, an input bus 6 of a calibrated DAC, a differential meter 7,

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output bus 8 difference meter and device 9 set the input signals.

Key 2 provides for feeding to the first input of the meter 7 the difference of the additional analog measure 1, the base potential of the device or the signal from the output of the reference DAC 3. Busbars 4 and 6 are supplied with sets of input signals for the reference and calibrated DAC. From exit 8, the measurement reading is taken.

Assuming the errors of the low-order weights are independent of the code and assuming the errors of the high-order bits on different code combinations are arbitrarily dependent on the code, but constant for a particular code, the analog output value of the DAC (voltage or current) can be represented as

A (B) = Σ «1 ' ³ 1 +.

| = 1

t = N —I

+ <2k · Duck + Δι. (one)

k = 1

where "1," g ..... "PC," ν-ηι, ... / 7ν) - N digit input code of the DAC;

ύ} and | - ideal value output1 = 1

analog analog value of the DAC; t

2 "kAak - output error k = 1

analog value of the DAC, due to errors in the weights of the lower included digits Δ Ek;

the error of the analog output value of the DAC, due to the error of the group of high-order bits on the K code, and K is the numerical equivalent of the code combination of the high-order bits a _n | _{+ a} > ₈ ... α _Ν

I = Σ «Ν-ι + 1 · 2 ^Н.

1 = 1

those. It is assumed that the errors of the mutual influences of the lower digits of the discrete divider of the DAC are negligible, and the errors of the mutual influence of the higher digits are not distinguished, but are estimated integrally.

The calibration process is as follows.

Determine the error of the group of high-order bits and the error of the lower bit weights of the calibrated DAC 5. The calibration procedure is applicable to any binary DAC. Since the output signal

the calibrated DAC 5 can be of a different nature (current, voltage), then the k-th bit weight is denoted by a _k , and the output analog signal of the DAC for code K is denoted by A (B).

Calibration starts by measuring the difference ν ₃ τ between the analogue measure 1 atet and the output analogue value of the calibrated DAC 5 when it is fed to the code B input of the binary equivalent of the number (3 = lax ^ " ¹ , where 1max = 2-1, which corresponds to the maximum code combination in the senior ranks.

The value of ν _{3Τ is} stored for subsequent calibration cycles and is equal to

ν ₃ τ = Eth - (Σ "1 * ^a 1 + ^ (max) · (2)

1 = 1

To determine the errors of the weights of the lower digits, m measurement cycles are performed, where m is the number of the lower digits produced as follows.

A calibrated DAC 5 is supplied with a set of input signals, by which only the lower-order digit weight ak is turned on, where is the cycle number, k = t, t-1,. ,, 1. The output of the calibrated DAC 5, subject _{to the} error is equal to a La _to La + _k. The output signal of the reference DAC 3 BK is set approximately equal to a _to + La _to and through the analog key 2 is fed to the input of the meter 7. The latter measures the signal difference (a _to + La _to ) -Vk, and the result

ν _'κ = (ak + Δ and _{K) to} (3)

fix. Then, in the calibrated DAC 5, the k-th digit is switched off and the smaller k-th bit weights are turned on; now a day off

k - 1

DAC signal 5 is equal to the sum of Σ ( ^a 1 + La]).

1 = 1

The meter 7 measures the difference between the specified amount and the output signal VK of the reference DAC 3, the result obtained

k - 1

ν! = Σ (31 + Δ ₃ )) - Βκ (4)

1 = 1

fix.

Then 5 = 2-1 measurement cycles are performed, where 1 = Ν-t. In each 3rd cycle, where 3 = 1 $ is the number of the cycle, the following actions are performed. First, the code of the number L is fed to the upper bits of the calibrated DAC 5, and the lower code is filled with the lower code, which corresponds to the input of the code Vg ^{1 to the} DAC 5 - the binary equivalent of the number

five

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6

0 ^< = Τ · 2 ^ΓΤ1 , the output signal of the calibrated DAC 5 is equal to

Α (ΚΙ ¹ > Σ AE1 + 4 ·

1 = 1

The reference DAC 3 is supplied with such a set of input signals that its analog output signal B [is approximately equal to the analog output signal of the calibrated DAC 5. Measuring instrument 7 measures this difference, and the result

νι ¹ = £ SG | a] 4- - Βι (5)

] = 1

fix.

Then on the calibrated DAC 5, the code Κι ^{2 is given the} binary equivalent of the number 0 = 1-2 ^t -1, that is, the code of the number 1-1 is sent to the higher digits, and the lower digits include: the output signal of the calibrated DAC 5 is now

A (P ^) = Σ «1 a | + Δ ϊ - ι 4 1 = 1

t

+ Σ ^Δθ ι ·

1 = ¹

The meter measures the difference between this signal and the output signal of the reference DAC 3. and the result obtained

V? = C £] a] + Δι - 1 +

1 = 1

t

. + Y · Δ a] - W (6)

B + 1

fix. These measurements are performed for all code combinations in (high-order bits).

According to the results of 2 -1 measurement cycles determine the error of the higher digits.

Based on a certain error of the high order bits on code 1-1 and measurement results, the error of the most significant digit from the group of the least significant is determined, after which the errors of all the lower order digits are successively calculated.

Consider the sequence of calculating the errors of the higher digits.

Subtracting from the measurement result (5) the measurement result (6) we get

νχ = νί - = a _о + А [- Δ] -ι-ί Yes ,.

1 = 1

where Zo is the low-order weight. (Denoting / ’у * '= Δ (- Δχ-ι and assuming =, we have

A (= £ Δι *. Using £, we write

^{1 = 1}

νχ, = 3 ₀ + Δ? - § Δβ), (7)

1 = 1

where it comes from

Δι = νΐ-3 ₀ + ^ Aa), (8)

1 = 1

and for 1max ⁼ 2 * -1 we get

A (max = ABLAX ^- 3 4 Δ 3}. (9)

1 = 1

Subtracting (9) from (8). we have

▼

Αί 'ASLaks = ^ν Ι - ^at 1max' (1 θ)

from where

Ac = Ablax У "YY-Y ^ ax · (11)

Summing up expressions (11) for all 1 = 1.2-1, we get

2 '-1

+ Σ νΐ- ( ² “ ¹ ) 'νΐΜ3« · (12)

1 = 1

Considering in the formula (7) that a _E t = § 05 31 and 1 = 1

2 * -1 *

A (max = Σ Ac, we have 1 = 1

Wet = AGmax = Σ Ac - (2 - 1) Ablax ~~ .1 = 1

. 2 ¹ . - one

- (2'-1) ν ^ κο + Σ HS, (13)

g = 1

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where it comes from

2-1 ·

x I Σ _νι- y _am ]. (14)

1 = 1

Substituting (14) and (11), we get

Y, "= _H - 'X

2 - 1

2 * -1

χ [Σ V] _{-ν 3Τ} ]. (15)

1 = 1

Considering that νι = 4-ν ?, we get

2 ¹ -1

X [Σ ( ^ν 1 “V?)“ ^At floor 1.

1 = 1

Consider the procedure for calculating the error of low-order weights.

From the result of measurement (3) subtract (4), we get

. · To - 1

νκ = νί-ν ^ = (3π- Σ -aO +

1 = 1

+ Aak - Σ ^La 1 - · 0θ)

| = 1

considering that

k - 1

Ek - Σ ^and 1 = ^a o,

. 1 = 1

where a ₀ is the weight of the lower order, we get

to -1

Uk = a ₀ + Aak- ^ ^Aa b O ⁷ ) 1 = 1

and for k + 1

to -1

Vк +1 = а ₀ + Аак + 1 - Σ Д ^а 1 · О®) 1 = 1

Subtracting (17) from (18). will get

UK + 1-UK ⁼ AZK + ι 2Aai, (19)

where it comes from

And au = - | - (Aak + 1 + Uk = Uk + 1). (20)

Given \ / k = \ / k ¹ ~ \ / k ² , we get

1 1 2 "2

And ak = -tr (A ak + 1 + Uk-Uk-Uk + 1 + Uk + 1).

At the same time, Aa _t +1 = Αι, e 1 / t + 1-Ut + 1 = νίι-ν3. Total error on arbitrary code

K = {“ι,“ 2 Ota, and y4 + 1 .... Dy} is determined

according to the formula

l A (K) = ar Aa] + At,

1 = 1

ι

where i = Σ «ν-ι ₊ 1 · 2 ^th ;

.1 = 1

1 = Ν-t.

Thus, this method provides an estimate of the error of the DAC on all possible code combinations in the high-order bits and improves the calibration of the DAC.

The calibration results for the proposed method can be used for tolerance testing in the production of DAC chips, for their input control, as well as for correction of measurement results performed using measuring instruments including specific calibrated DACs, for example, according to calibration tables.

Claims (2)

The method of calibration of linearity digital-to-analog converter based on the determination of the errors of the weights of its digits and consisting in measuring and remembering the difference between the output analog value of the calibrated digital-analog converter when 1 high-order digit is switched on and an analogue measure equal to the ideal value of the output analog digital-analogue value of the digital analogue digital-analog converter, and equal to the ideal analogue value equal to the analog digital-analogue converter’s digital analog converter. with the inclusion of the first most significant digits in it, after which t cycles are performed (where σι = Ν-Ι is the number of lower digits and N is The total number of digits), in each of which the difference between the output analog outputs of the calibrated and reference transducers is measured and remembered when the k-th digit is switched on (where k = 1t is the cycle number) and the difference between the output analog values of the calibrated and the reference digital-to-analog converters, when turned on, in the operative of the -th digit, starting with the Junior, and in the calibrated one, all the lower digits are relative to the -th, followed by the determination of the errors of all the weights of the lower-order digits , characterized in that, in order to improve accuracy, 5 = 2-1 cycles are additionally carried out, in each of which the difference between the output analog values of the reference and calibrated digital-analogue converters is measured and stored when their_ bits of the I code (where 1 = 1 , 5 cycle number) and switching off the low-order bits and the difference between the output analog values of the calibrated and reference digital-to-analog converters when applying to the high-order digits of the reference digital-to-analog converter of the number code1 and turning off it low-order bits and submission to high-order digits of the calibrated digital-analog converter of the I-1 code and inclusion of its low-order digits, determine the errors of the calibrated digital-analog converter in the high-order digits by the stored values of the corresponding differences: 1 = 1.2 ... ..2-1, 1 = 1 where Λ * = νιι_ „ί —_! _ Х х [Σ (ν / - V? ) - ν "τ]. 1 = 1 & - error of the senior group: discharges when applying for this group code numbers I; ν? - the result of the reference measurement of the difference of the output analog values of the reference and calibrated digital-analog converters when applying the code of number I to their most significant bits and turning off the low-order bits; νί ² is the result of measuring the difference · of the output analog values of the reference and calibrated digital-analogue converters when applying the code I number to the high bits of the reference converter and turning off its low-order bits and feeding the low-order numbers to the high bits of the calibrated code; ν ₃ Γ is the result of measuring the difference between the analogue measure and the output value of the calibrated digital-analogue converter when all I most significant digits are included; the error of the weight of the senior discharge in the group of younger digits is determined by the formula Dat = 4- (Δι + Ut -ν £ - V? + Ν?), and the errors of all other low-order bits are determined by the formula ι 1 2. 1 year Δ ai = ~ 2 (Δ ak + \ / k - \ / k - \ / k + 1 + \ A + 1), k = t-1, t-2,.,. 1 \ / K ¹ is the result of measuring the difference between the output analog values of the reference and calibrated digital-analogue converters when the k-th digit is turned on in this and the other; \ / k ² is the result of measuring the difference of the output analog values of the reference and calibrated digital-to-logic converters when the first digit of them includes the k-th digit, and the second of all the younger ones with respect to the k-th digit. 1679630