RU2326494C1 - Method of correction of analogue-to-digital conversion errors and device for its implementation - Google Patents

Abstract

FIELD: physics, measurement.

SUBSTANCE: invention relates to instrumentation, in particular, to methods of correction of analogue-to-digital conversion (ADC) errors for use in information and measuring systems. The ADC error correction method involves testing and correction; corrected n-bit ADC (7) is tested continuously during 2ⁿ cycles since the moment of its activation, by applying a test signal generated by high-precision n-bit DAC (5) to the ADC input, with subsequent storing, in (the random-access memory) (RAM) (8), the ADC (7) output pattern difference code and the cycle number code, by the address of the output pattern of corrected n-bit ADC (7). After the continuous testing completion, periodic ADC (7) testing and error correction processes alternating during one cycle are performed; in the correction mode, the output pattern of ADC (7) serves simultaneously as the minuend code and the address of the subtrahend code (in (n+1)-bit adder) (9) - the code written to RAM (8) earlier, during the testing mode, carrying information about the deviation of the actual conversion response of ADC (7) from the ideal one. The device also includes clock oscillator (1), n-bit binary counter (2), (n+1)-input AND element (3), 2x(n+1)-input inverting digital switch (4), analogue signal switch (6), OR element (10), and halver (11).

EFFECT: simplification of analogue-to-digital conversion error correction method and increase in its accuracy and speed.

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Description

FIELD OF THE INVENTION

The invention relates to measuring equipment, in particular to methods for correcting errors of analog-to-digital conversion and devices for their implementation, and can be used in information-measuring systems.

State of the art

A known method for correcting errors in analog-to-digital conversion includes analog-to-digital (direct) conversion of the original signal, digital-to-analog (inverse) conversion of the signal, reduced by the value of the model signal of direct conversion of the original signal; the received signal is subjected to direct conversion, the signal is also converted back, increased by the value of the reference signal of the result of the direct conversion of the original signal, the obtained signal is also subjected to direct conversion, the corrected result of the conversion of the original signal is calculated by the formula

where K is the magnitude of the reference signal;

Y ₁ - the result of analog-to-digital conversion of the original signal;

Y ₂ is the result of analog-to-digital conversion of the digital-to-analog value conversion (Y ₁ -К);

Y ₃ is the result of analog-to-digital conversion of the digital-to-analog value conversion (Y ₁ + K).

To implement this method, a measuring and computing device containing a control computer complex (UVK), a common bus line, an accurate digital-to-analog converter, a source of the measured signal, an input switch of analog signals, a group normalizing converter with a nonlinear conversion function, and an analog-to-digital converter were used (USSR author's certificate No. 984030 dated 12/23/1982).

The disadvantage of this method and device for its implementation is high complexity, low accuracy and low speed, and in addition, for certain characteristics of the converter, when nonlinearity is essential, the correction algorithm is not feasible.

Closest to the proposed invention and taken by the authors as a prototype is a method for correcting errors of analog-to-digital conversion, which consists in generating a code signal proportional to the input analog signal with its subsequent storage, implementing n correction cycles, in the first of which the first reference code signal is generated, which is used as a stored code signal followed by digital-to-analog and analog-to-digital conversion with storing the result, after h it is formed by the second reference code signal by adding an exemplary code signal to the first reference code signal followed by its digital-to-analog and analog-to-digital conversion with storing the result, the corrected code of the input analog signal is calculated from the code signals proportional to the input and two reference signal, it is stored and compared with a stored code signal proportional to the input signal, if the received difference does not exceed a predetermined value in advance, then form yhodnoy coded signal equal to the corrected signal to the code, otherwise perform the following correction cycles in which to use the stored previous cycle adjusted correction code signal as a first reference code signal; the calculation of the corrected code signal is carried out according to the formula (2)

X ' _{(i-1) .sk} = X _{(i-1) .sk} + K _i , moreover:

for i = 2, ..., n;

where K is the magnitude of the reference signal;

X _nsk - not adjusted code of the input signal;

X _i.sk - adjusted code of the input signal;

- результат цифрового измерения входного сигнала;

- the result of digital measurement of the input signal;

Y _i , Y ' _i - the results of analog-to-digital conversion of the first and second reference signals.

To implement this method, a measuring and computing device (complex) was used, containing a trunk, a digital-to-analog converter, a switch, an analog-to-digital converter, and a computer (RF Patent No. 2085033 of 07.20.1997).

The disadvantage of this method and device for its implementation is high complexity, low accuracy and low speed.

Disclosure of invention

The technical result, which can be achieved using the present invention, is to reduce the complexity of implementation while improving accuracy and speed.

The technical result is achieved by the fact that in the method of correction of errors of analog-to-digital conversion, including correction based on sequential digital-to-analog and analog-to-digital conversion of signals, followed by storing the result of analog-to-digital conversion in random access memory, a testing process is introduced, which is carried out at the beginning continuous operation from the moment the analog-to-digital converter is turned on for 2 ⁿ cycles, followed by storing the output difference code of the analog-to-digital converter code and the clock number code to the address of the output code of the corrected n-bit analog-to-digital converter, to the input of which a test signal is presented, which is a stepwise voltage function, the instantaneous value of which is proportional to the code of the number of clock pulses, and in the case of linearization for a complete test period ⁽ⁿ 2 cycles) will coincide with an idealized characteristic of the analog-digital conversion, wherein during the continuous testing mode correlator It is blocked, and upon completion of continuous testing, the stage of correction of errors in the analog-to-digital conversion begins, and the correction and periodic testing modes alternate for one clock cycle, and periodic testing is carried out due to the possible instability of the conversion characteristics of the analog-to-digital converter, while the output code is in the correction mode An analog-to-digital converter serves as both a reducible code and the address of a subtracted code - a code recorded earlier in the operation Noe memory during the test mode, carrying information about a deviation distorted (real) conversion characteristic analog-digital converter from the ideal; the result of the calculation is a code for the voltage value lying on the idealized characteristic of the analog-to-digital conversion.

An apparatus for implementing a method for correcting errors in analog-to-digital conversion, comprising a switch for analog signals, the first information input of which serves as the input of the device, and the output is connected to the input of a corrected n-bit analog-to-digital converter, the outputs of which are address inputs of random access memory (2 ⁿ words × n bits), a clock generator, an n-bit binary counter, an (n + 1) -and input element And, 2 × (n + 1) -input inverting digital switch, n- a digital-to-analog converter, an (n + 1) -digit adder, a two-input OR element, a divider by two, the output of the clock being connected to the input of an n-bit binary counter, the outputs of which are simultaneously connected to n inputs of the (n + 1) -input element And, to the n inputs of the first group of the 2 × (n + 1) input inverting digital switch and the inputs of the n-bit digital-to-analog converter, the output of which is connected to the second information input of the analog signal switch; the outputs of the corrected n-bit analog-to-digital converter are connected to the n inputs of the second group of inputs of the (n + 1) -bit adder, the logic null level is applied to the (n + 1) -th input of the second group of inputs of which (which is a sign bit); The n outputs of the (n + 1) -bit adder are the device outputs, in addition, the first to kth and (n + 1) -th (sign) outputs are simultaneously connected to the (k + 1) -th inputs of the random access memory, the corresponding outputs of which are connected to similar inputs of the second group of inputs of a 2 × (n + 1) input inverting digital switch, which has inputs of the second group of inputs, from (k + 1) -th to the n-th and (n + 1) - the first input of the first group of inputs has a logic zero level, and the (n + 1) -th input of the second group of inputs, which is the control input, is simultaneously connected to the output by the two-input OR element, the control input of the analog signal switch, the output of the device U _ref. prohibiting the removal of information coming from the output of the device; the outputs of the inverting digital switch are connected to the inputs of the first group of inputs of the (n + 1) -bit adder, the lowest level of the transfer of which the level of the logical unit; the output of the (n + 1) -and input element And is connected to the input of the divider by two, the inverse output of which is simultaneously connected to the (n + 1) -th input of the (n + 1) -input element And and with the second input of the two-input element OR, the first input which is connected to the output of the clock generator.

The 2 × (n + 1) -inverting inverting digital switch contains an inverter, (n + 1) -inverting switching modules, each of which includes two two-input AND elements, a two-input OR-NOT element, and the control input of the inverting digital switch is connected to the second inputs of the first two-input element And directly, and the second two-input element And through the inverter; the first inputs of both two-input elements And are the inputs, respectively, of the first and second groups of inputs of the inverting digital switch, while the numbers of the inputs of the inverting digital switch correspond to the numbers of the inverting switching modules; the outputs of two-input elements AND are inputs of two-input elements OR NOT, the outputs of which are the outputs of the inverting switching modules and the corresponding outputs of the inverting digital switch, while the numbers of the outputs of the inverting digital switch correspond to the numbers of the inverting switching modules.

The essence of the method for correcting errors in analog-to-digital conversion is to use testing and correction processes, and from the moment the corrected n-bit analog-to-digital converter is turned on, it is continuously tested for 2 ⁿ cycles by supplying a test signal generated by a high-precision n-bit to its input digital-to-analog converter (DAC), followed by storing the difference code of the output code of the analog-to-digital converter and the code of the measure number to the address the output code of the corrected n-bit analog-to-digital converter; upon completion of continuous testing, the processes of periodic testing and correction of errors of the analog-to-digital conversion are carried out for one clock cycle, while in the correction mode, the output code of the analog-to-digital converter serves as both a reducible code and the address of the subtracted code - the code previously recorded in the random access memory during the test mode, which carries information about the deviation of the distorted (real) conversion characteristics of the analog-to-digital conversion driver from the ideal; the result of the calculation is a code for the voltage value lying on the idealized characteristic of the analog-to-digital conversion.

Brief Description of the Drawings

Figure 1 shows the linear undistorted and convex additively-multiplicative (distorted) ADC conversion characteristics.

Figure 2 shows the linear undistorted and concave additively-multiplicative (distorted) characteristics of the ADC conversion.

Figure 3 shows the linear undistorted and convex-concave additively-multiplicative (distorted) characteristics of the ADC conversion.

Figure 4 shows the structural diagram of a device for implementing the method of correction of errors of analog-to-digital conversion.

Figure 5 shows the structural diagram of an inverting digital switch.

Figure 6 shows the timing diagrams of the operation of the device implementing the method for correcting errors of analog-to-digital conversion.

The implementation of the invention

The basis of the proposed method for correcting errors of analog-to-digital conversion are the following concepts.

The analog-to-digital conversion process can be characterized by two main types of conversion characteristics:

- linear undistorted, figure 1, 2, 3, the function y = f (x);

- additive multiplicative (distorted), figure 1, 2, 3, the functions y _and = f _and (x)

These characteristics of the conversion of the ADC are described by the expressions:

y = x

_and y = a + b · x + a · x ² + ... + h · x ^g,

where a, b, c, h are weights, on which, as a rule, conditions are imposed:

In the General case, the distorted characteristics of the conversion of the ADC y _and take the form of convex y _{and +} , concave y _{and -} or alternately convex-concave y _{and ±} curves, Figs. 1, 2, 3. The error of the conversion, in this case, will be determined by the relations:

,

,

where x ₀ is the voltage value of the input signal at the time of sampling (voltage amplitude of the discrete value of the converted signal);

or in general form:

Δy _and (x ₀ ) = f (x ₀ ) -f _and (x ₀ ).

Despite the fact that x, being, in fact, an analog quantity, is characterized by an infinite number of possible values, x ₀ , as a discrete quantity, takes only 2 ⁿ values, where n is the ADC capacity. Therefore, the previous expression can be represented in matrix form:

or

or

where i∈ [1, ..., 2 ⁿ ].

Since the function y = x serves as a description of the linear distortionless characteristic of the ADC conversion, the matrix of distortionless values || f (x _i ) || will be deterministic. In turn, the matrix of ADC values to be corrected || f _and (x _i ) || and the deviation matrix || Δy _and (x _i ) || can only be determined a posteriori. In this case, the monotonicity of the conversion characteristics, FIGS. 1 and 2, ensures compliance with:

Moreover, this correspondence, in real ADCs, as a rule, is unambiguous.

Considering the fulfillment of the equality y = x and the requirement that the voltage levels of the quantization steps of the ADC and DAC of the same bit are equal, the previous relationship can be represented as:

The specified relationship inherent in a particular ADC can be identified by testing it in the entire range of input signals. Namely, by applying a test signal of a given level x _{T.i to the} ADC input and calculating the deviations Δy _and (x _тi ) according to (3), using the ADC output signal f _and (x _T.i ). Thus, the set of values {Δy _and (x _T.i )} of the deviation of the distorted (real) characteristics of the ADC conversion from the undistorted (ideal) takes on a deterministic character.

When the converted signal X _cj , having the status of a random signal, is received at the ADC input, the output code signal f _and (x _с.j ) is compared with the set of test values of the deviation of the ADC conversion characteristic {Δy _and (x _T.i )} and when the condition is met:

f _and (x _cj ) ∈ [1, ..., 2 ⁿ ].

a decision is made on compliance

Thus, the proposed method for correcting errors of analog-to-digital conversion is as follows.

At the first stage, from the moment of switching on, the corrected n-bit ADC is subjected to continuous testing for 2 ⁿ clock cycles, the essence of which is to provide the ADC input with a signal generated by a high-precision n-bit DAC. In this case, the signal voltage level is proportional to the cycle number (Fig. 6, a, e). The ADC output code serves as the address of the memory cells of the random access memory (RAM), in which the difference code of the clock number and the ADC output code is recorded.

By the time the 2 ^n- th clock arrives in RAM, a matrix (3) of determinate deviations of the additive-multiplicative (distorted, that is, real) characteristics of the ADC conversion from the undistorted (ideal) is formed. The role of the coefficients of the matrix of posterior values of the additive-multiplicative (distorted) characteristics of the ADC conversion is played by the list of possible ADC output codes.

Upon completion of the stage of continuous testing (Fig. _6. e; t _{nest test} ), the ADC switches to the error correction mode. At this stage, the periodic testing of the ADC is carried out in the second (active) half of the clock cycles ( _Fig.6 . E; t _{first test} ). Periodic testing is carried out due to the possible instability of the parameters of a working ADC. During the first (passive) half of the clocks, an analysis and subsequent correction of the samples of the information input signal is performed (Fig. 6. e; t _cor ). Upon receipt of the converted signal at the input of the ADC, the RAM is transferred to the mode of reading information from the cells whose address corresponds to the output code of the ADC. The read code is subtracted from the output of the ADC (4). The generated code will correspond to the distortionless analog-to-digital conversion mode.

The block diagram of a device for implementing the method for correcting errors of analog-to-digital conversion is shown in Fig.4.

A device for implementing the analog-to-digital conversion error correction method comprises a clock pulse generator (GTI) 1, an n-bit binary counter 2, an (n + 1) -input element AND 3, 2 × (n + 1) -input inverting digital switch (ILC) ) 4, n-bit digital-to-analog converter (DAC) 5, switch 6 of analog signals, adjustable n-bit ADC 7, RAM 8 (2 ⁿ words × (k + 1) bits), (n + 1) -bit adder 9, two-input element OR 10, divider by two 11, and the output of the GTI 1 is connected to the input of the n-bit binary counter 2, the outputs of which simultaneously connected to n inputs of the (n + 1) input element And 3, to n inputs of the first group of 2 × (n + 1) input ICC 4 and the inputs of the n-bit DAC 5, the output of which is connected to the second information input of the switch 6 analog signals, the first information input of which serves as the input of the device, and the output is connected to the input of the corrected n-bit ADC 7, the outputs of which are connected simultaneously to the address bus of RAM 8 and to the n inputs of the second group of inputs of the (n + 1) -bit adder 9, (n + 1) -th input of the second group of inputs of which (which is a sign bit m) filed logic-zero level; The n outputs of the (n + 1) -bit adder 9 are the device outputs, in addition, the first to kth and (n + 1) -th (sign) outputs are simultaneously connected to the (k + 1) -th RAM inputs 8 whose corresponding outputs are connected to similar inputs of the second group of inputs of the 2 × (n + 1) -input ICC 4, which has inputs of the second group of inputs from the (k + 1) th to the n-th and (n + 1) -th the input of the first group of inputs has a logic zero level, and the (n + 1) -th input of the second group of inputs, which is the control input, is simultaneously connected to the output of the two-input element OR 10, the control input of the switch 6 tax signals output device U _bits. , allowing the removal of information coming from the output of the device; the outputs of the ICC 4 are connected to the inputs of the first group of inputs of the (n + 1) -bit adder 9, to the lowest transfer bit of which a logical unit level is supplied; the output of the (n + 1) -and input element And 3 is connected to the input of the divider 11 into two, the inverse output of which is simultaneously connected to the (n + 1) -th input of the (n + 1) -input element And 3 and to the second input of the two-input element OR 10, the first input of which is connected to the output of the GTI 1.

2 × (n + 1) -inverting inverting digital switch 4 contains an inverter 12, (n + 1) -inverting switching modules 13, each of which includes two two-input elements And 14 and 15, two-input element OR-NOT 16, and the control input of the ICC 4 is connected to the second inputs of the two-input elements And 14 directly, and And 15 through the inverter 12; the first inputs of the two-input elements And 14 And 15 are the inputs, respectively, of the first and second groups of inputs of the IDC 4, while the numbers of the inputs of the IDC 4 correspond to the numbers of the inverting switching modules 13; the outputs of the two-input elements AND 14 and AND 15 are the inputs of the two-input elements OR-NOT 16, the outputs of which are the outputs of the inverting switching modules 13 and the corresponding outputs of the ICC 4, while the numbers of the outputs of the ICC 4 correspond to the numbers of the inverting switching modules 13.

The inverting digital switch 4 operates as follows.

When a control signal with a low voltage level is received at the input U _control to the second inputs of the two-input elements And 14 serves the level of logical zero. At the second inputs of the two-input elements And 15 serves the level of the logical unit formed by the inverter 12. Elements And 14 are locked, the elements And 15 open. Switching of signals of the first group of inputs of ICC 4 is prohibited. Switching of signals of the second group of inputs of ICC 4 is performed with simultaneous inversion of states by means of OR-NOT 16 elements.

When a control signal with a high voltage level is received at the input U _control the second inputs of the two-input elements And 14 serves the level of the logical unit. At the second inputs of the two-input elements And 15 a logic zero level is generated formed by the inverter 12. Elements And 14 are opened, Elements And 15 are locked. Switching signals of the second group of inputs of the ILC 4 is prohibited. The switching of the signals of the first group of inputs of the ICC 4 is carried out with the simultaneous inversion of states by means of OR-NOT 16 elements.

Diagrams explaining the principle of operation of the device implementing the method for correcting errors of analog-to-digital conversion are shown in Fig.6, in particular, diagrams of output signals:

a) - GTI1;

b) - direct output of the trigger of the least significant bit of the n-bit binary counter 2;

c) - n-input element And 3;

g) - inverse output of the divider 11 into two;

d) - n-bit DAC 5;

e) - two-input element OR 10.

A device for implementing a method for correcting errors in analog-to-digital conversion works as follows.

The device operates in two stages - the testing phase and the correction phase.

The stage of continuous testing begins at the moment the device is turned on and continues for the first 2 ⁿ cycles of the GTI 1 (Fig. 6. a, e). By a power difference, the divider by two 11 is set to zero. A high level of potential, from the inverse output of the divider to two 11 (Fig. 6. g), is fed to the second input of the two-input element OR 10, as a result of which a high potential level is also established at its output (Fig. 6. e), which will not depend on the level of logical potential at the first input of a two-input element OR 10 (output signals GTI 1). The level of high potential from the output of the two-input element OR 10 provides:

- switching through a switch 6 analog voltage signals from the output of the DAC 5 to the input of the ADC 7;

- translation of RAM 8 into recording mode;

- switching the output code of the n-bit binary counter 2 and the sign code, followed by their inversion, to the first group of inputs of the adder 9;

- the formation of a signal prohibiting the reading of information from the outputs of the device (high potential level at the output of U _ref. ).

The output code of the n-bit binary counter 2 carries information about the measure number, while being the coefficient of the matrix of distortionless values || f (x _i ) || (3).

Taking into account the introduction of voltage with the level of a logical unit to the input of the low-order transfer of the adder 9 and the inversion by the CID 4, the output code of the n-bit binary counter 2 is converted into an additional negative number code (the second term in expression (3)).

The voltage level of the signal at the output of the DAC 5 is proportional to the clock number (code of the n-bit binary counter 2), (Fig. 5. d).

The output code of the ADC 7 simultaneously arrives at the second inputs of the adder 9 and serves as the address of the memory cells of the RAM 8, into which the output code of the adder 9 is written, which is the coefficients of the deviation matrix || Δy _and (x _i ) || (3).

RAM 8 (2 ⁿ words × (k + 1) bits) is characterized by the fact that k <n, and the value of k is determined by the marginal error of the corrected ADC. For example, in the case of a 16-bit ADC with a maximum error of 1%, the absolute error expressed by:

- in quantization levels, will be:

δ = 2 ^16/100 = 655 levels

- among the categories, will be:

512 = 2 ⁹ <n _δ <2 ¹⁰ = 1024.

Given the peak nature of the errors, it is legitimate to take k = 9. (k + 1) -th digit is significant, then (k + 1) = 10. The total RAM memory will be:

2 ⁿ · (k + 1) = 2 ¹⁶ · 10 = 655360 bits.

By the time the 2 ^n- th clock arrives in RAM 8, a matrix code is generated (3) of the determined values of the deviation of the additive-multiplicative (distorted) characteristics of the ADC conversion from the undistorted (ideal) one. In this case, the coefficients of the deviation matrix will be tightly interconnected with the additive-multiplicative (distorted) characteristic of the ADC 7 conversion (ADC 7 output codes).

At the moment of the input of the n-bit binary counter of the 2 (2 ⁿ -1) -th pulse from the output of the GTI 1 at all outputs of the counter 2, and therefore at the output of the (n + 1) -input element And 3, the level of the logical unit is set (Fig 6.c). Upon receipt of the input n-bit binary counter 2 2 ^n- th pulse:

- n-bit binary counter 2 is reset;

- at the output of the (n + 1) -input element And 3 the level of logical zero is set, (Fig 6.c);

- at the inverted output of the divider by two 11, the logical zero level is set (Fig. 6.d), (this state remains unchanged until the device is turned off);

- at the second input of the two-input element OR 10, the logic zero level is set (Fig 6.e);

- the stage of continuous testing is completed (Fig.6.e; t _nep.test ), the correction stage begins.

Stage of correction.

Upon the onset of the active part of the cycle (the pulse coming from the output of the GTI 1 (Fig.6.a), the algorithm of the device is similar to the algorithm of the continuous testing phase. Periodic testing of the ADC 7 is necessary due to the possible instability of the parameters of the working ADC.

Upon the onset of the passive part of the cycle (pause in the receipt of pulses from the output of the GTI 1 (Fig.6.a) at the output of the two-input element OR 10, the logic zero level is set (Fig.6.е; t _cor ), which:

- provides switching through a switch 6 analog voltage signals from the input of the device to the input of the ADC 7;

- RAM 8 is transferred to the mode of reading information from cells whose address corresponds to the output code of the ADC 7;

- the formation of a signal that allows the reading of information from the outputs of the device (low potential level at the output of U _ref. ).

- switching the output code of RAM 8, with their subsequent inversion, to the first group of inputs of the adder 9.

Taking into account the introduction of voltage with the level of a logical unit to the input of the low-order transfer of the adder 9 and the inversion performed by the ICC 4, the output code of the RAM 8 is converted into an additional code of a negative number (the second term in expression (4)).

The output of the ADC 7 is nothing but the coefficients of the matrix of posterior values of the additive-multiplicative (real) characteristics of the ADC conversion. Using RAM 8 and adder 9 provides a comparison of the coefficients of the matrices of the ideal and real characteristics of the conversion of the ADC.

That is, in the case of using a device that implements the proposed method for correcting errors in analog-to-digital conversion, it is possible to provide a distortionless analog-to-digital signal conversion with minimal use of computing resources.

The minimum use of computing resources significantly distinguishes the proposed method and device for its implementation, compared with the prototype, for a number of indicators:

1) implementation difficulties - the prototype is undoubtedly more complicated, since a measuring and computing complex (actually a special processor) was used for its implementation;

2) the degree of error correction - the prototype provides lower accuracy of the ADC due to the use of the division operation (2), (3), (4) which, without fail, is accompanied by calculation errors, since the dividend and divider are discrete values, which means that along with with the standard error of digital systems, due to the magnitude of the quantization step (of which the device according to the proposed method is not spared), there is an additional error - calculation error;

3) speed - the prototype has significantly lower speed due to the use of an iterative algorithm, which involves at least two cycles of analog-to-digital conversions, for each of which the conversions must be carried out three times (values Y, Y _i , Y ' _i , (2) ), that is, the real speed of the prototype, without taking into account the loss of time for calculations, is at least three times less than that of the device according to the proposed method.

During the comparative evaluation of the prototype and the device according to the proposed method, it is impossible not to take into account the criterion of the device’s readiness for use (time the device goes to operating mode), according to which the device by the proposed method clearly loses. However, it should be noted that the measuring technique, to which the invention belongs, necessarily involves preliminary “warming up” of the equipment before starting the measurements, which means that the duration of the testing phase of the device according to the proposed method, which is a fraction of a second (unit seconds), will have practically no effect on the coefficient readiness of measuring equipment (information measuring system). The validity of the aforementioned is due to the fact that high-speed ADCs primarily require the conversion characteristics correction. In particular, the ADC 12281 12-bit serial-parallel ADC performs up to 20 million samples per second (G. Volovich, ADC and DAC chips / G. I. Volovich, V. B. Ezhov. - M .: Publishing House “ Dodeka-XXI ", 2005. - 432 p.), Because of this, the stage of continuous testing according to the expression

,

,

where k = 2 is the number of calls to the ADC per cycle;

N _n = 2 ⁿ = 2 ¹² - the number of ticks for the period of continuous testing of the ADC;

N _t = 2 · 10 ⁷ - the number of samples per second (the number of calls to the ADC per second);

will be:

That is, in the case of the implementation of the device according to the proposed method, in relation to the prototype, there will be:

1) decrease in complexity;

2) increase in accuracy;

3) increased performance.

Claims (2)

1. A method for correcting errors in analog-to-digital conversion, including correction based on sequential digital-to-analog and analog-to-digital conversion of signals, followed by storing the result of analog-to-digital conversion in a random access memory, characterized in that a testing process is introduced into it, which is carried out at the beginning continuous operation from the moment the analog-to-digital converter is turned on for 2 ⁿ cycles, followed by storing the difference code of the output analog code -digital converter and clock number code at the address of the output code of the corrected n-bit analog-to-digital converter, to the input of which a test signal is presented, which is a step-by-step voltage function, the instantaneous value of which is proportional to the code of the number of clock pulses in the case of linearization for the full test period (2 ⁿ cycles) will coincide with the idealized characteristic of analog-to-digital conversion, while during continuous testing the correction mode is blocked, and upon completion of continuous testing, the stage of correction of errors in the analog-to-digital conversion begins, and the correction and periodic testing modes alternate during one cycle, and periodic testing is carried out due to the possible instability of the conversion characteristics of the analog-to-digital converter, while in the correction mode the output code of the analog-to-digital the converter serves as both a reducible code and the address of a deductible code - a code previously recorded in random access memory device during the test mode, carrying information about the actual deviation distorted characteristics conversion analog-digital converter from the ideal; the result of the calculation is a code for the voltage value lying on the idealized characteristic of the analog-to-digital conversion. 2. A device for error correction of analog-to-digital conversion, containing a switch of analog signals, the first information input of which serves as the input of the device, and the output is connected to the input of the corrected n-bit analog-to-digital converter, the outputs of which are address inputs of random access memory (2 ⁿ words × n bits), characterized in that a clock generator, an n-bit binary counter, an (n + 1) -and input element And, 2 × (n + 1) -invert digital input a torus, an n-bit digital-to-analog converter, an (n + 1) -bit adder, a two-input OR element, a divider by two, and the output of the clock generator is connected to the input of an n-bit binary counter, the outputs of which are simultaneously connected to n inputs (n + 1 ) -input element And, to the n inputs of the first group of a 2 × (n + 1) -input inverting digital switch and the inputs of an n-bit digital-to-analog converter, the output of which is connected to the second information input of the analog signal switch; the outputs of the corrected n-bit analog-to-digital converter are connected to the n inputs of the second group of inputs of the (n + 1) -bit adder, the logical null level is supplied to the (n + 1) -th input of the second group of inputs of which is a sign bit; The n outputs of the (n + 1) -bit adder are the outputs of the device, in addition, the outputs from the first to the kth and (n + 1) -th (sign) are simultaneously connected to the (n + 1) -th inputs of the random access memory, the corresponding outputs of which are connected to similar inputs of the second group of inputs of a 2 × (n + 1) input inverting digital switch, which has inputs of the second group of inputs, from (k + 1) -th to the n-th and (n + 1) - the first input of the first group of inputs has a logic zero level, and the (n + 1) -th inputs of the second group of inputs, which is the control input, is simultaneously connected to the course of the two-input element OR, the control input of the analog signal switch, the device output U _ref. prohibiting the removal of information coming from the output of the device; the outputs of the inverting digital switch are connected to the inputs of the first group of inputs of the (n + 1) -bit adder, the lowest level of the transfer of which the level of the logical unit; the output of the (n + 1) -and input element And is connected to the input of the divider by two, the inverse output of which is simultaneously connected to the (n + 1) -th input of the (n + 1) -input element And and with the second input of the two-input element OR, the first input which is connected to the output of the clock; a 2 × (n + 1) input inverting digital switch contains an inverter, (n + 1) inverting switching modules, each of which includes two two-input AND elements, a two-input OR-NOT element, and the control input of the inverting digital switch is connected to the second inputs of the first two-input element And directly, and the second two-input element And through the inverter; the first inputs of both two-input elements And are the inputs of the first and second groups of inputs of the inverting digital switch, respectively, while the numbers of the inputs of the inverting digital switch correspond to the numbers of the inverting switching modules; the outputs of two-input elements AND are inputs of two-input elements OR NOT, the outputs of which are the outputs of the inverting switching modules and the corresponding outputs of the inverting digital switch, while the numbers of the outputs of the inverting digital switch correspond to the numbers of the inverting switching modules.

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