RU67361U1 - DEVICE CORRECTION DEVICE FOR ANALOG-DIGITAL CONVERSION - Google Patents

Abstract

The utility model relates to measuring equipment, in particular to error correction devices for analog-to-digital conversion and can be used in information-measuring systems. The technical result is to reduce the complexity of the implementation while improving accuracy and speed. The analog-to-digital conversion error correction device contains an RS trigger, two two-input AND elements, a clock generator, two two-input OR elements, an n-bit binary counter, an n-input AND element, a 2 × (n + 1) -invert digital inverter, n-bit DAC, analog signal switcher, adjustable n-bit ADC, RAM (2 ⁿ words × (k + 1) bits), (n + 1) -bit adder, m-bit binary counter, m-input element I. 6 ill. 2 S.P. F-ly

Description

The technical field to which the utility model relates.

The utility model relates to measuring equipment, in particular to error correction devices for analog-to-digital conversion, and can be used in information-measuring systems.

State of the art

A device for correcting errors of analog-to-digital conversion, which is a measuring and computing device containing a control computer complex (UVK), a bus type common bus, an accurate digital-to-analog converter, a measured signal source, an input switch of analog signals, a group normalizing converter with non-linear conversion function, analog-to-digital converter (ADC). The principle of operation of this device is based on analog-to-digital (direct) conversion of the original signal, digital-to-analog (inverse) conversion of the signal, reduced by the value of the model signal of direct conversion of the original signal; the received signal is subjected to direct conversion, the signal is also converted inverse, increased by the value of the model signal of the result of direct conversion of the original signal, the obtained signal is also subjected to direct conversion, the corrected result of the conversion of the original signal is calculated by the formula

where K is the magnitude of the reference signal;

Y ₁ - the result of analog-to-digital conversion of the original signal;

Y ₂ - the result of the analog-to-digital conversion of the digital-to-analog value conversion (Y ₁ -К);

Y ₃ - the result of the analog-to-digital conversion of the digital-to-analog value conversion (Y ₁ + К).

(USSR author's certificate No. 984030 dated 12/23/1982).

The disadvantage of this device is its high complexity, low accuracy and low speed, and in addition, for certain characteristics of the converter, when nonlinearity is essential, the correction algorithm is not feasible.

Closest to the proposed utility model and taken by the authors as a prototype is a measuring and computing device (complex) containing a trunk, a digital-to-analog converter, a switch, an analog-to-digital converter, and a computer. The principle of operation of this device involves the formation of a code signal proportional to the input analog signal and its storage, followed by n correction cycles, the first of which forms the first reference code signal, which is used as a stored code signal followed by digital-analog and analog-to-digital its transformation with storing the result, after which form the second reference code signal by adding an exemplary code signal to the first reference code the input signal, followed by its digital-to-analog and analog-to-digital conversion with storing the result, the corrected code of the input analog signal is calculated from the code signals proportional to the input and two reference signals, it is stored and compared with the stored code signal proportional to the input signal; if the obtained difference does not exceed the predetermined value in advance, then generate an output code signal equal to the adjusted

otherwise, the following correction cycles are carried out, in which the corrected code signal stored in the previous correction cycle is used as the first reference code signal; the calculation of the corrected code signal is carried out according to the formula (2)

, moreover:

for i = 2, ..., n;

where K is the magnitude of the reference signal;

X _nsk - not adjusted code of the input signal;

X _i.cc - adjusted code of the input signal;

- the result of digital measurement of the input signal;

- the results of analog-to-digital conversion of the first and second reference signals.

(RF patent No. 2085033 dated 07/20/1997).

The disadvantage of this device is its high complexity, low accuracy and low speed.

Utility Model Disclosure

The technical result that can be achieved using the proposed model is to reduce the complexity of the implementation while improving accuracy and speed.

The technical result is achieved by the fact that in the device for the correction of errors of analog-to-digital conversion containing a switch

analog signals, the first information input of which serves as the input of the device, and the output is connected to the input of a corrected n-bit analog-to-digital converter, the outputs of which are address inputs of random access memory (RAM) (2 ⁿ words × n bits), a clock pulse generator ( GTI), two two-input elements AND, RS trigger, two two-input elements OR, m-bit binary counter, m-input element And, n-bit binary counter, n-input element And, 2 × (n + 1) -invert digital commute ator, n-bit digital-to-analog converter (DAC), (n + 1) -digit adder, with the inverse and direct outputs of the RS trigger connected, respectively, to the first inputs of the first and second two-input elements And, the second inputs of which are connected to the output of the GTI , the output of the first two-input element AND, through the two-input element OR, is connected to the input of an n-bit binary counter, the outputs of which are simultaneously connected to the inputs of the n-input element And, to the n inputs of the first group of a 2 × (n + 1) input inverting digital switch and inputs np gas tube DAC, whose output is connected to second data input of the analog switch; the output of the n-input element AND is connected to the S input of the RS trigger; the output of the second two-input element And serves as the input of the m-bit binary counter, the outputs of which are connected to the inputs of the m-input element And, the output of which is simultaneously connected to the second input of the first two-input OR element and the first input of the second two-input OR element, the second input of which is connected to the first input the first two-input element And; the outputs of the corrected n-bit analog-to-digital converter are connected to the n inputs of the second group of inputs of the (n + 1) -bit adder, the logic null level is applied to the (n + 1) -th input of the second group of inputs of which (which is a sign bit); n outputs of the (n + 1) -bit adder are the outputs of the device, in addition, the outputs from the first to

k-th and (n + 1) -th (sign) are simultaneously connected to the (k + 1) -th inputs of random access memory, the corresponding outputs of which are connected to similar inputs of the second group of inputs of a 2 × (n + 1) -invert digital switch, which has inputs of the second group of inputs, from the (k + 1) -th to the n-th and (n + 1) -th inputs of the first group of inputs, a logic zero level is applied, and the (n + 1) -th input of the second group inputs, which is the control input, is simultaneously connected to the output of the second two-input element OR, the control input of the analog signal switch, you the course of the device U _ref. prohibiting the removal of information coming from the output of the device; the outputs of the inverting digital switch are connected to the inputs of the first group of inputs of the (n + 1) -digit adder, to the lower transfer bit of which a logical unit level is applied.

The 2 × (n + 1) -inverting inverting digital switch contains an inverter, (n + 1) -inverting switching modules, each of which includes two two-input AND elements, a two-input OR-NOT element, and the control input of the inverting digital switch is connected to the second inputs of the first two-input element And directly, and the second two-input element And through the inverter; the first inputs of both two-input elements And are the inputs, respectively, of the first and second groups of inputs of the inverting digital switch, while the numbers of the inputs of the inverting digital switch correspond to the numbers of the inverting switching modules; the outputs of the two-input elements AND are inputs of the two-input elements OR NOT, the outputs of which are the outputs of the inverting switching modules and the corresponding outputs of the inverting digital switch, while the numbers of the outputs of the inverting digital switch correspond to the numbers of the inverting switching modules.

Brief Description of the Drawings

Figure 1 shows the linear distortionless and convex additive-multiplicative (distorted) characteristics of the conversion of the ADC.

Figure 2 shows the linear distortionless and concave additive-multiplicative (distorted) characteristics of the ADC conversion.

Figure 3 shows the linear distortionless and convex-concave additive-multiplicative (distorted) characteristics of the ADC conversion.

Figure 4 shows a structural diagram of a device for correcting errors of analog-to-digital conversion.

Figure 5 shows the structural diagram of an inverting digital switch.

Figure 6 shows the timing diagrams of the device for correcting errors of analog-to-digital conversion.

Utility Model Implementation

The basis of the proposed device error correction analog-to-digital conversion are the following concepts.

The analog-to-digital conversion process can be characterized by two main types of conversion characteristics:

- linear undistorted, figure 1, 2, 3, the function y = f (x);

- additive multiplicative (distorted), figure 1, 2, 3, the functions y _and = f _and (x);

These characteristics of the conversion of the ADC are described by the expressions:

where a, b, c, h are weights, on which, as a rule, conditions are imposed:

In the General case, the distorted characteristics of the conversion of the ADC y _and take the form of convex y _{and +} , concave y _{and -} or alternately convex-concave y _{and ±} curves, Figs. 1, 2, 3. The error of the conversion, in this case, will be determined by the relations:

where x ₀ is the voltage value of the input signal at the time of sampling (voltage amplitude of the discrete value of the converted signal);

or in general form:

Despite the fact that x, being, in fact, an analog quantity, is characterized by an infinite number of possible values, x ₀ , as a discrete quantity, takes only 2 ⁿ values, where n is the ADC capacity. Due to this, the previous expression can be represented in matrix form:

or

or

where i∈ ### U2351, ..., 2 ⁿ ### U251.

Since the function y = x serves as a description of the linear distortion-free characteristic of the ADC conversion, the matrix of distortionless values

will be deterministic. In turn, the matrix of ADC values to be corrected and deviation matrix can only be determined a posteriori. At the same time, the monotonicity of the conversion characteristics, FIGS. 1 and 2, ensures compliance with:

Moreover, this correspondence, in real ADCs, as a rule, is unambiguous.

Given the equality y = x, and the requirement of equal voltage levels of the quantization steps for the ADC and DAC of the same bit, the previous relationship can be represented as:

The specified relationship inherent in a particular ADC can be identified by testing it in the entire range of input signals. Namely, by supplying a test signal of a given level x _{Ti to the} ADC input, and calculating the deviations Δy _and (x _ti ) according to (3), using the ADC output signal f _and (x _ti .). Thus, many meanings deviations of the distorted (real) characteristics of the conversion of the ADC from the distortionless (ideal) becomes deterministic.

When the converted signal x _s.j , having the status of a random signal, is received at the ADC input, the output code signal f _and (x _s.j ) is compared with the set of test values of the deviation of the ADC conversion characteristic and upon fulfillment of the condition:

a decision is made on compliance

Block diagram of an analog-to-digital error correction device

conversion is shown in Fig.4.

The device for error correction of analog-to-digital conversion contains RS trigger 1, two-input element I2, two-input element IZ, GTI 4, two-input element OR 5, n-bit binary counter 6, n-input element And 7, 2 × (n + 1) - input inverting digital switch (CLC) 8, n-bit DAC 9, switch 10 of analog signals, adjustable n-bit ADC 11, RAM 12 (2 ⁿ words × (k + 1) bits), (n + 1) -digit adder 13, a two-input OR element 14, an m-bit binary counter 15, an m-input element AND 16, with the inverse and direct outputs of trigger RS 1 connected, respectively, to the first inputs of the two-input elements And 2 and 3, the second inputs of which are connected to the output of the GTI 4, the output of the two-input element And 2, through the two-input element OR 5, is connected to the input of the n-bit binary counter 6, the outputs of which are simultaneously connected to the inputs of the n-input element And 7, to the n inputs of the first group of 2 × (n + 1) -input ICC 8 and the inputs of the n-bit DAC 9, the output of which is connected to the second information input of the switch 10 analog signals, the first information input of which serves as an input devices, and the output is connected to the input of the corrected n-bit ADC 11, the outputs of which are connected simultaneously to the address bus of RAM 12 and to the n inputs of the second group of inputs of the (n + 1) -bit adder 13, to the (n + 1) -th input of the second group of inputs of which (which is a sign bit) a logic zero level is applied; The n outputs of the (n + 1) -bit adder 13 are the device outputs, in addition, the first to kth and (n + 1) -th (sign) outputs are simultaneously connected to the (k + 1) -th RAM inputs 12 , the corresponding outputs of which are connected to similar inputs of the second group of inputs of the 2 × (n + 1) -input ICC 8, which has the inputs of the second group of inputs, from (k + 1) -th to the n-th and (n + 1) - the first input of the first group of inputs has a logic zero level, and the (n + 1) -th input of the second group of inputs, which is the control input, is simultaneously

connected to the output of the two-input element OR 14, the control input of the switch 10 analog signals, the output of the device U _ref. prohibiting the removal of information coming from the output of the device; the outputs of the ICC 8 are connected to the inputs of the first group of inputs of the (n + 1) -bit adder 13, to the lower transfer bit of which a logical unit level is supplied; the output of the two-input element And 3 serves as the input of the m-bit binary counter 15, the outputs of which are connected to the inputs of the m-input element And 16, the output of which is simultaneously connected to the second input of the two-input element OR 5 and the first input of the two-input element OR 14, the second input of which is connected to the first input of the two-input element And 2.

2 × (n + 1) -inverting inverting digital switch 8 contains an inverter 17, (n + 1) -inverting switching modules 18, each of which includes two two-input elements And 19 and And 20, two-input element OR-NOT 21, moreover, the control input of the ICC 8 is connected to the second inputs of the two-input elements And 19 directly, and And 20 through the inverter 17; the first inputs of the two-input elements And 19 and And 20 are the inputs, respectively, of the first and second groups of inputs of the ILC 8, while the numbers of the inputs of the ILC 8 correspond to the numbers of the inverting switching modules 18; the outputs of the two-input elements And 19 and And 20 are the inputs of the two-input elements OR-NOT 21, the outputs of which are the outputs of the inverting switching modules 18 and the corresponding outputs of the ICC 8, while the numbers of the outputs of the ICC 8 correspond to the numbers of the inverting switching modules 18.

The inverting digital switch 8 operates as follows.

When a control signal with a low voltage level is received at the input U _control , to the second inputs of the two-input elements And 19 served as a logic level zero. At the second inputs of the two-input elements And 20 serves the level of the logical unit formed by the inverter 17.

Elements And 19 are locked, Elements And 20 open. Switching signals of the first group of inputs of the ILC 8 is prohibited. The switching of the signals of the second group of inputs of the ICC 8 is performed with the simultaneous inversion of states, by means of the elements OR-NOT 21.

When a control signal with a high voltage level is received at the input U _control , to the second inputs of the two-input elements And 19 served the level of the logical unit. At the second inputs of the two-input elements And 20, a logic zero level is generated by the inverter 17. Elements And 19 are opened, Elements And 20 are locked. Switching signals of the second group of inputs of the ILC 8 is prohibited. The switching of the signals of the first group of inputs of the ICC 8 is performed with the simultaneous inversion of states, by means of the elements OR-NOT 21.

Diagrams explaining the principle of operation of the device errors of analog-to-digital conversion are shown in Fig.6, in particular, diagrams of output signals:

a) - GTI 4;

b) - inverse output of the RS trigger 1;

C) - direct output RS trigger 1;

g) - n-input element And 7;

d) - n-bit DAC 9;

e) - two-input element OR 14.

A device for correcting errors of analog-to-digital conversion works as follows.

The device operates in two stages - the testing phase and the correction phase.

Testing phase.

The stage of continuous testing begins at the moment the device is turned on and continues for the first 2 ⁿ cycles of the GTI 4 (Fig. 6.a). By power drop, RS trigger 1 is set to zero. A high level of potential with the inverse output of the RS trigger 1 (Fig 6.b),

arrives at the second input of the two-input element OR 14, which ensures the formation of a high potential level at its output, as well as the first input of the two-input element And 2, thereby allowing the passage of pulses from the output of the GTI 4, through the element OR 5, to the input n- bit binary counter 6.

A low level of potential from the direct output of the RS trigger 1 (Fig 6.B), is fed to the first input of the two-input element And 3, thereby prohibiting the passage of pulses from the output of the GTI 4, to the input of the m-bit binary counter 15.

The level of high potential at the output of OR 14 (Fig 6.e), provides:

- switching, by means of a switch 10 analog signals, voltage from the output of the DAC 9 to the input of the ADC 11;

- translation of RAM 12 into recording mode;

- switching the output code of the n-bit binary counter 6 and the sign code, followed by their inversion, to the first group of inputs of the adder 13;

- the formation of a signal prohibiting the reading of information from the outputs of the device (high potential level at the output of U _ref. ).

The output code of the n-bit binary counter 6 carries information about the measure number, while being a coefficient of the matrix of distortionless values (3).

Taking into account the introduction of a voltage with a logic level of one to the low-order transfer input of the adder 13, and the inversion by the ICC 8, the output code of the n-bit binary counter 6 is converted into an additional negative number code (the second term in expression (3)).

The voltage level of the signal at the output of the DAC 9 is proportional to the clock number (n-bit binary counter code 6), (Fig. 6.e).

The output code of the ADC 11 is simultaneously fed to the second inputs

the adder 13 and serves as the address of the memory cells of the RAM 12, which records the output code of the adder 13, which is the coefficients of the deviation matrix (3).

RAM 12 (2 ⁿ words × (k + 1) bits) is characterized by the fact that k <n, and the value of k is determined by the marginal error of the corrected ADC. For example, in the case of a 16-bit ADC with a maximum error of 1%, the absolute error expressed by:

- in quantization levels, will be:

- among the categories, will be:

Given the peak nature of the errors, it is legitimate to take k = 9. (k + 1) -th digit is significant, then (k + 1) = 10. The total RAM memory will be:

By the time the 2 ^n- th clock arrives, in RAM 12 a matrix code is generated (3) of the determined values of the deviation of the additive-multiplicative (distorted) characteristics of the ADC conversion from the undistorted (ideal) one. In this case, the coefficients of the deviation matrix will be strictly interconnected with the additive-multiplicative (distorted) characteristic of the ADC 11 conversion (ADC output codes 11).

At the moment of the input of the n-bit binary counter 6, the (2 ⁿ -1) th pulse from the output of the GTI 4, at all the outputs of the counter 6, and therefore at the output of the n-input element And 7, the level of the logical unit is set (Fig. 6.d). Upon receipt of the input n-bit binary counter 6 2 ^n- th pulse:

- n-bit binary counter 6 is reset;

- at the output of the n-input element And 7, set the level of logical zero, (Fig 6.d);

- at the inverted output RS of trigger 1, the logic zero level is set (Fig.6. b), (this state remains unchanged until the device is turned off);

- a logic zero level is applied to the second input of the two-input element OR 14 (Fig 6.b), (this state remains unchanged until the device is turned off);

- at the direct RS output of flip-flop 1, the level of the logical unit is set (Fig. 6.c), (this state remains unchanged until the device is turned off);

- the stage of continuous testing is completed (Fig.6.e; t _nep.test ), the correction stage begins.

Stage of correction.

The correction stage is characterized by two unequal algorithms:

- periodic testing algorithm;

- An error correction algorithm for analog-to-digital conversion.

The periodic testing algorithm takes place during the 2 ^m- GTI tact cycle 4 (Fig.6.e). During the 2 ^m- nog cycle, the outputs of the m-bit binary counter 15 establish a high potential level, and the device operation algorithm will be similar to the algorithm of the continuous testing step (with the difference that only every 2 ^m will pass to the input of the m-bit binary counter 6 GTI momentum 4). Periodic testing of the ADC 11 is necessary due to the possible instability of the parameters of the working ADC. The interval of full testing of the ADC 11 will be 2 ^{m + n} cycles GTI 4.

In the interval (periodically repeating) from the 1st (2 ^m ) to 2 ^m-2- nd cycles of the GTI 4, the logic zero level is set at the output of the two-input element OR 14 (Fig.6.е; t _cor ), as a result of this:

- provides switching, by means of a switch 10 analog voltage signals from the input of the device to the input of the ADC 11;

- RAM 12 is transferred to the mode of reading information from cells, address

which corresponds to the output code of the ADC 11;

- a signal is formed allowing the reading of information from the outputs of the device (low potential level at the output of U _ref. ).

- provides switching output code of RAM 12, with subsequent inversion, to the first group of inputs of the adder 13.

Taking into account the introduction of voltage with the level of a logical unit to the input of the transfer of the least significant bit of the adder 13, and the inversion by the ICC 8, the output code of the RAM 12 is converted into an additional code of a negative number (the second term in expression (4)).

The output of the ADC 11 is nothing but the coefficients of the matrix of posterior values of the additive-multiplicative (real) characteristics of the ADC conversion. By means of RAM 12 and the adder 13 provides a comparison of the coefficients of the matrices of the ideal and real characteristics of the conversion of the ADC 11.

That is, in the case of using an analog-to-digital conversion error correction device, it is possible to provide a distortionless analog-to-digital signal conversion, with minimal use of computing resources.

The minimum use of computing resources significantly distinguishes the proposed device, compared with the prototype, for a number of indicators:

1) implementation difficulties - the prototype is undoubtedly more complicated, since a measuring and computing complex (actually a special processor) was used for its implementation;

2) the degree of error correction - the prototype provides lower accuracy of the ADC due to the use of the division operation (2), (3), (4) which is necessarily accompanied by calculation errors, since the dividend and divisor are discrete values, and therefore, along with the standard error digital systems, due to the magnitude of the quantization step (which the device according to the proposed

method), there is an additional error - calculation error;

3) speed - the prototype has significantly lower speed due to the use of the iterative algorithm, which involves at least two cycles of analog-to-digital conversions, for each of which the conversions must be carried out three times (values Y, Y _i , , (2)), that is, the real speed of the prototype, without taking into account the loss of time for calculations, is at least three times less than that of the proposed device.

During the comparative evaluation of the prototype and the proposed device, one cannot but take into account the criterion of the device’s readiness for use (the time the device goes to operating mode), according to which the proposed device clearly loses. However, it should be noted that the measuring technique, to the field of which the utility model belongs, necessarily involves preliminary “warming up” of the equipment before starting the measurements, which means that the duration of the testing phase of the proposed device, which is a fraction of a second (unit seconds), will have practically no effect on the coefficient readiness of measuring equipment (information measuring system). The validity of the aforementioned is due to the fact that high-speed ADCs primarily require the conversion characteristics correction. In particular, the 12-bit serial-parallel ADC 12281 ADC performs up to 20 million samples per second (G. Volovich, ADC and DAC chips / G. I. Volovich, V. B. Ezhov. - M .: Publishing House “ Dodeka-XXI ", 2005. - 432 p.), Because of this, the stage of continuous testing according to the expression

where k = 2 is the number of calls to the ADC per cycle;

N _n = 2 ⁿ = 2 ¹² - the number of ticks for the period of continuous testing

ADC;

N _t = 2 · 10 ⁷ - the number of samples per second (the number of calls to the ADC per second);

will be:

That is, in the case of the implementation of the proposed device, in relation to the prototype, there will be:

1) decrease in complexity;

2) increase in accuracy;

3) increased performance.

Claims (2)

1. The device for error correction of analog-to-digital conversion, containing a switch of analog signals, the first information input of which serves as the input of the device, and the output is connected to the input of the corrected n-bit analog-to-digital converter, the outputs of which are address inputs of random access memory (2 ⁿ words × n bits), characterized in that a clock generator, two two-input AND elements, an RS trigger, two two-input OR elements, an m-bit binary count are introduced into the device chik, m-input element And, n-bit binary counter, n-input element And, 2 × (n + 1) -invert digital inverter, n-bit digital-to-analog converter, (n + 1) -bit adder, and inverse and RS direct outputs of the trigger are connected, respectively, to the first inputs of the first and second two-input AND elements, the second inputs of which are connected to the output of the clock generator, the output of the first two-input AND element, through the two-input OR element, is connected to the input of the n-bit binary counter, the outputs which one temporarily connected to the inputs of the n-input element And, to the n inputs of the first group of the 2 × (n + 1) -invert digital inverter and the inputs of the n-bit digital-to-analog converter, the output of which is connected to the second information input of the analog signal switch, the output of the n-input element And is connected to the S input RS trigger, the output of the second two-input element And serves as the input of the m-bit binary counter, the outputs of which are connected to the inputs of the m-input element And, the output of which is simultaneously connected to the second input of the first about the two-input OR element and the first input of the second two-input OR element, the second input of which is connected to the first input of the first two-input AND element, the outputs of the corrected n-bit analog-to-digital converter are connected to n inputs of the second group of inputs of the (n + 1) -digit adder, the (n + 1) -th input of the second group of inputs of which (which is a sign bit) is supplied with a logic zero level; The n outputs of the (n + 1) -bit adder are the outputs of the device, in addition, the outputs from the first to the kth and (n + 1) -th (sign) are simultaneously connected to the (k + 1) -th inputs of random access memory , the corresponding outputs of which are connected to similar inputs of the second group of inputs of a 2 × (n + 1) input inverting digital switch, which has inputs from the (k + 1) th to the n-th and (n + 1) inputs of the second group of inputs the input of the first group of inputs is set to a logic zero level, and the (n + 1) input of the second group of inputs, which is the control input, is simultaneously connected to Odom second two-input OR element, the input analog switch control signal, the output of the U _Lock. prohibiting the removal of information coming from the output of the device, the outputs of the inverting digital switch are connected to the inputs of the first group of inputs of an (n + 1) -bit adder, the lowest level of transfer of which is supplied with the level of a logical unit. 2. The device for error correction of the analog-to-digital conversion according to claim 1, characterized in that the 2 × (n + 1) input inverting digital switch contains an inverter, (n + 1) inverting switching modules, each of which includes two two-input AND element, a two-input OR-NOT element, and the control input of the inverting digital switch is connected to the second inputs of the first two-input element And directly, and the second two-input element And through the inverter, the first inputs of both two-input AND elements are the moves of the first and second groups of inputs of the inverting digital switch, respectively, while the numbers of the inputs of the inverting digital switch correspond to the numbers of the inverting switching modules, the outputs of the two-input elements And are the inputs of the two-input elements OR, NOT the outputs of which are the outputs of the inverting switching modules and the corresponding outputs of the inverting digital switch, wherein the output numbers of the inverting digital switch correspond to the numbers of the inverting commutator tion modules.