CN116243583A

CN116243583A - Neural network measurement calibration system and method for TDL-TDC

Info

Publication number: CN116243583A
Application number: CN202111470307.4A
Authority: CN
Inventors: 吴东岷; 许玥; 张宝顺; 曾中明
Original assignee: Suzhou Institute of Nano Tech and Nano Bionics of CAS
Current assignee: Suzhou Institute of Nano Tech and Nano Bionics of CAS
Priority date: 2021-12-03
Filing date: 2021-12-03
Publication date: 2023-06-09

Abstract

The invention discloses a neural network measurement calibration system and method for TDL-TDC, wherein the system comprises: the TDL-TDC module is used for completing initial calibration of the delay chain by adopting a code density calibration method to obtain an initial calibration value; the temperature sensing module is used for acquiring the running temperature of the system on the FPGA chip and obtaining running temperature information; and the upper computer neural network calibration module builds a multi-layer learning network, takes the running temperature information and the initial calibration value as the input of the network, outputs the running temperature information and the initial calibration value as the delay time of the delay unit, and builds a corresponding nonlinear change relation between the temperature information and the delay time of the delay unit. According to the invention, the nonlinear change relation corresponding to the delay time data and the temperature data of the delay unit is found out through the learning network, and a more accurate nonlinear calibration result of each section of unit of the current delay chain can be obtained only through one calibration and temperature acquisition during actual work.

Description

Neural network measurement calibration system and method for TDL-TDC

Technical Field

The invention relates to the technical field of signal measurement, in particular to a neural network measurement calibration system and method for TDL-TDC.

Background

The TDC (time-to-digital converter) is an important component of a detection system, and is often found in electronic instruments and meters and signal processing systems, and is an instrument for converting an analog signal into a digital signal expressed in time. The method is widely applied to various fields such as laser radar ranging, sonar ranging, remote sensing imaging and the like.

TDC is typically implemented by two methods, ASIC (application specific integrated circuit) construction or FPGA (field programmable gate array) based construction, and the accuracy of TDC operation depends on its internal structure's ability to more accurately divide measurements over time. Common fine time measurement methods include: the measurement accuracy achieved by the two methods is closely related to the system running frequency, so that in the TDC system, the structure of the tap delay chain is adopted.

Currently, the calibration function implementation of a TDC constructed based on a tapped delay chain mainly depends on a code density calibration method. The code density calibration method has long calibration time, which can lead to overlong dead time of the system. Meanwhile, as the delay time of the TDL-TDC delay unit is related to factors such as PVT (process, voltage and temperature), a large amount of delay time calibration is often needed to continuously meet the requirement of working accuracy along with the increase of the operating temperature in actual working, so that the influence caused by the problems is further aggravated.

In the prior art, a long-chain TDC is usually built by using an FPGA, so that the total delay time of a delay chain in the TDL-TDC is longer than the time period of signals to be detected, and the aim of continuously collecting 2 continuous signals to be detected is fulfilled. At different temperatures, the continuous signals to be measured with fixed frequency are respectively collected to obtain 2 delay time tap and tap_d values, so that a difference value T ₀ =lap_d-tap. Different temperatures can be measured to obtain a plurality of different T ₀ As a result, at room temperature T _0(room) For reference temperature, calculating temperature coefficient relation coeffecient=t corresponding to different temperature difference values compared with room temperature _0(room) /T ₀ . In practical application, the code density calibration module is used to collect the initial delay units of each delay chain at room temperatureAnd linearly correcting the delay time of each delay chain in operation according to the current temperature coefficient calculated by the reference delay chain, namely multiplying the initial delay time value by the temperature coefficient result obtained by the reference delay chain to obtain the delay time of each delay chain at the current temperature. Because the scheme uses a fixed constant coefficient, after the delay time of the delay units at different positions of the delay chain is multiplied and calibrated, only the result after the delay time calibration of the delay units at the middle part of the delay chain meets the working requirement, and the delay error is still larger after the delay time calibration of a large number of delay units at the front and rear parts of the delay chain.

The information disclosed in this background section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person of ordinary skill in the art.

Disclosure of Invention

The invention aims to provide a neural network measurement calibration system and method of a TDL-TDC, which can solve the problems of fixed calibration coefficient value and large linear calibration error in the prior art.

To achieve the above object, an embodiment of the present invention provides a neural network measurement calibration system for a TDL-TDC, including:

the TDL-TDC module is built on the FPGA chip, and the TDL-TDC module adopts a code density calibration method to complete initial calibration of the delay chain so as to obtain an initial calibration value;

the temperature sensing module is used for acquiring the running temperature of the FPGA chip system on chip and obtaining running temperature information;

and the upper computer neural network calibration module builds a multi-layer learning network, takes the running temperature information and the initial calibration value as the input of the network, outputs the running temperature information and the initial calibration value as the delay time of the delay unit, and builds a corresponding nonlinear change relation between the temperature information and the delay time of the delay unit.

In one or more embodiments, the learning network includes a sample of network training including an input vector X, an expected output quantity t, a deviation between a network output value Y and the expected output value t, and the error is reduced along a gradient direction by adjusting a connection strength Wij of an input node and a hidden node, a connection strength Tjk between the hidden node and an output node, and a threshold value, and after repeated learning training, a network parameter corresponding to the minimum error is determined, and training is stopped.

In one or more embodiments, the learning network further includes a weight updating step that includes:

(1) Initializing the connection weight of each layer, and setting the learning rate and the inertia coefficient;

(2) Inputting a sample pair, and calculating the node output value of each layer;

(3) And according to the gradient descent strategy, adjusting the parameters in the negative gradient direction of the objective function.

In one or more embodiments, the learning network updates the weights using accumulated errors, and updates the parameters after reading the entire training set.

In one or more embodiments, the TDL-TDC module includes:

the coarse time measuring module is used for measuring a coarse time interval between the Start pulse signal to be measured and the Stop pulse signal to be measured;

the fine time measuring module is used for respectively measuring small time intervals from the rising edge of the Start pulse signal to be measured and the Stop pulse signal to be measured to the rising edge of the system clock signal by adopting a tap delay chain method;

the edge detection module finds the edge jump position of the non-thermometer code output by the delay chain and converts the edge jump position into a single thermal code;

the encoder module converts the single thermal code into binary system to obtain the total number of the signals passing through the delay unit;

the on-chip calibration module is used for completing initial calibration of the delay chain by using a code density calibration method;

and the serial port communication module is used for uploading the initial calibration value and the running temperature information to the upper computer neural network calibration module.

In one or more embodiments, the TDL-TDC module further includes:

the Wave-unit transmitter module is used for respectively separating an input single Start pulse signal to be measured and a Stop pulse signal to be measured into 2 continuous pulse signals, and inputting the separated pulse signals into the fine time measurement module.

In one or more embodiments, the TDL-TDC module further includes:

the oscillation signal generation module generates a random pulse signal independent of a system clock signal, obtains the calibrated delay time of each delay cell and uploads the delay time to the upper computer neural network calibration module.

In one or more embodiments, the coarse time measurement module accumulates the time interval to be measured using 2 inverted gray code adders, uses the value of the positive counter when the pulse signal to be measured is coming in the first half cycle, and uses the value of the negative counter when the pulse signal to be measured is coming in the second half cycle.

In one or more embodiments, the results of the fine time measurement module are latched using a dual stage flip-flop.

To achieve the above object, an embodiment of the present invention further provides a neural network measurement calibration method for TDL-TDC, including:

constructing a TDL-TDC module on an FPGA chip, and completing initial calibration of a delay chain by adopting a code density calibration method to obtain an initial calibration value;

acquiring an FPGA chip system on chip to obtain operation temperature information;

and constructing a multi-layer learning network, taking the running temperature information and the initial calibration value as the input of the network, outputting the running temperature information and the initial calibration value as the delay time of the delay unit, and establishing a corresponding nonlinear change relation between the temperature information and the delay time of the delay unit.

Compared with the prior art, the nonlinear variation relation corresponding to the delay time data and the temperature data of the delay unit is found out through the learning network, and a more accurate nonlinear calibration result of each section of unit of the current delay chain can be obtained only through one calibration and temperature acquisition.

Drawings

FIG. 1 is a schematic diagram of a neural network measurement calibration system for TDL-TDC according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of a TDL-TDC system waveform according to one embodiment of the present invention;

FIG. 3 is a schematic diagram of an FPGA tapped delay chain according to an embodiment of the invention;

FIG. 4 is a schematic diagram of a BP neural network model according to an embodiment of the invention;

FIG. 5 is a schematic illustration of a neural network training process, according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of multi-pulse detection according to an embodiment of the present invention;

FIG. 7 is a flowchart of a neural network calibration module, according to one embodiment of the present invention;

FIG. 8 is a state transition diagram generated by a state machine built by an on-chip calibration module according to the code density calibration principle in accordance with an embodiment of the present invention.

Detailed Description

The following detailed description of embodiments of the invention is, therefore, to be taken in conjunction with the accompanying drawings, and it is to be understood that the scope of the invention is not limited to the specific embodiments.

Throughout the specification and claims, unless explicitly stated otherwise, the term "comprise" or variations thereof such as "comprises" or "comprising", etc. will be understood to include the stated element or component without excluding other elements or components.

According to the invention, a neural network measurement calibration system for TDL (tapped delay chain) -TDC is provided, wherein the TDL-TDC is built on an FPGA platform, and meanwhile, a neural network is built on an upper computer. And after the upper computer network training is completed, the subsequent application is carried out by matching with the TDL-TDC of the FPGA platform.

As shown in FIG. 1, the neural network measurement calibration system for the TDL-TDC comprises a TDL-TDC module, a temperature sensing module and an upper computer neural network calibration module, wherein the TDL-TDC module adopts a code density calibration method to complete initial calibration of a delay chain, and an initial calibration value is obtained; the method comprises the steps that the operating temperature of a system on a chip of a temperature sensing module FPGA chip is obtained, and operating temperature information is obtained; and the upper computer neural network calibration module builds a multi-layer learning network, takes the running temperature information and the initial calibration value as the input of the network, outputs the running temperature information and the initial calibration value as the delay time of the delay unit, and builds a corresponding nonlinear change relation between the temperature information and the delay time of the delay unit.

The TDL-TDC module includes: the device comprises a Wave-unit emitter module, a coarse time measuring module, a fine time measuring module, an edge detection module, an encoder module, an on-chip calibration module, a serial port communication module and an oscillation signal generation module.

Referring to fig. 2, the input signals include a Start pulse signal to be measured and a Stop pulse signal to be measured, which are respectively a Start pulse signal to be measured and an end pulse signal to be measured at a required timing interval, and Start timing after the rising edge of the Start signal arrives, and Stop timing after the rising edge of the Stop signal arrives. Clk is the system clock signal.

The Wave unit transmitter module is used for respectively copying the Start pulse signal to be detected and the Stop pulse signal to be detected into 2 pulse signals, namely forming 2 Start pulse signals to be detected and 2 Stop pulse signals to be detected. The copied signals are used for measuring for multiple times, and the influence of errors such as ultra-wide bits on the precision is eliminated.

The coarse time measuring module comprises a coarse counter and a data processing module and is used for measuring the coarse time interval between the Start and Stop input pulse signals to be measured. The coarse time measurement module accumulates the time interval to be measured by using 2 reversed-phase Gray code adders, and when the pulse signal to be measured arrives in the first half period, the value of a normal-phase counter is used; when the pulse signal to be measured arrives in the latter half period, the value of the counter is used. And performing edge detection on the pulse signal to be detected to obtain an interval Gate signal Gate between two signal edges, wherein the adder count period T is equal to N when the gate=1, and the coarse time interval between Start and Stop pulses is equal to N x T.

Referring to fig. 3, the fine time measurement module includes a delay chain and a flip-flop, and the fine time measurement module adopts a tapped delay chain method to divide a small time interval (Δt1, Δt 2) between a rising edge of a pulse signal to be measured and a rising edge of a system clock signal into small times (Ti) of delay units (adders are delay units), and the total delay time of the delay chain is a sum of delay times of delay units through which the signal passes. The result is latched using a dual stage flip-flop.

Referring to fig. 6, in some embodiments, a plurality of Stop pulse signals to be measured are included: corresponding to Stop1, stop2, stop3 and Stop4 …, small time intervals between rising edges of the Stop pulse signals to be measured and rising edges of the system clock signals are respectively shown as Deltat 1, deltat 2, deltat 3 and Deltat 4 …, and 4 Stop pulse signals to be measured are used for illustration, and a plurality of channels are built to measure pulse signals of multiple channels simultaneously.

The edge detection module finds the non-thermometer coded edge jump position output by the delay chain and converts the position into a single thermal code, and then the single thermal code is converted into binary by the encoder module to obtain the total number of signals passing through the delay unit.

The encoder uses the fat tree structure, and the fat tree principle formula is as follows:

wherein, H [ i ] is the single thermal code obtained by edge detection, and B [ k ] is the binary code obtained by the encoder.

The on-chip calibration module builds a state machine on the FPGA chip to complete the initial calibration of the delay chain by using a code density calibration method.

An oscillation signal generation module is used for generating a random pulse signal independent of a TDC measurement clock. And obtaining the calibrated delay time on each delay cell, storing the delay time in the corresponding address of the storage module and transmitting the delay time to the upper computer for subsequent use.

The temperature sensing module is integrated on the FPGA chip and used for collecting the running temperature of the chip and transmitting the running temperature to the upper computer.

And the serial port communication module is used for uploading the initial calibration value and the temperature information to the upper computer neural network calibration module.

In this embodiment, the fine time measurement module inputs the pulse signal copied by the Wave unit transmitter module during working, and inputs the independent pulse signal of the oscillation signal generation module during on-chip calibration.

The on-chip calibration module builds a state machine according to the code density calibration principle, and a state transition diagram generated by a state machine program is shown in fig. 8. S0 is an initial waiting state, and enters into S1 when a calibration trigger signal arrives; in the S1 state, all calibration data stored by the storage module are cleared to 0, and the storage module data are triggered to enter the S2 state after all the calibration data are cleared to 0; in the S2 state, a statistical histogram is established, and when the random pulse signal finally falls on a certain delay unit, 1 is added to the data (address obtained by an encoder) of the address corresponding to the memory module. Entering an S3 state when the number of the random signals reaches a specified requirement N; and in the S3 state, calculating the statistical histogram obtained in the S2 according to the formula to obtain the calibrated delay time of each delay cell chip, and storing the calibrated delay time in the corresponding address of the storage module.

With reference to fig. 4 and 5, the upper computer builds a multi-layer BP neural network, sets a multi-layer hidden layer by taking temperature information and an initial calibration value as inputs of the network, and outputs the multi-layer hidden layer as delay time of the delay unit. Through nonlinear fitting of neurons, the delay time change trend of the delay unit at different temperatures can be learned, and the network training samples comprise an input vector X, an expected output quantity t and deviation between a network output value Y and the expected output value t. The error is reduced along the gradient direction by adjusting the connection strength Wij of the input node and the hidden layer node, the connection strength Tjk between the hidden layer node and the output node and the threshold value, and the network parameters (weight and threshold value) corresponding to the minimum error are determined through repeated learning training, so that the training is stopped. The trained neural network can process the input information of similar samples by itself and output the result information which has the smallest error and is subjected to nonlinear conversion.

When the upper computer neural network is built for the first time, the original data samples of the code density calibration modules with different temperatures and corresponding code densities, which are measured for many times, are transmitted to the upper computer through the serial port communication module; during training, a BP neural network is used for training to obtain a corresponding function relation between delay time and temperature of a delay unit; in actual operation, only the initial delay time value of the delay unit at the room temperature in the first operation after power-on is calibrated and acquired is transmitted to the upper computer, and the current operation temperature value acquired by the temperature sensor is brought into the functional relation obtained by training in the subsequent operation, so that the delay time under the current temperature condition can be correspondingly obtained.

According to the embodiment, the neural network result after training is adopted to replace a large number of calibration steps required by the TDC in actual working, the delay time of each delay chain delay unit at the current temperature can be obtained based on the network calibration result, the fine time measurement result is obtained through calculation according to the delay time, and the time interval of the current pulse to be measured can be obtained by matching with the coarse time measurement result and is used in a subsequent imaging processing system. A schematic flow chart of the actual operation of the neural network calibration module is shown in fig. 7.

The weight updating step of the neural network comprises the following steps:

(1) Initializing the connection weight of each layer, and setting the learning rate and the inertia coefficient.

(2) And inputting a sample pair, and calculating the node output value of each layer.

The standard BP algorithm updates the connection weight for only one training sample at a time, the parameter update is very frequent, and the effect of updating different training samples may be "offset". In order to finally achieve the minimum error on all training data, the invention adopts accumulated error to update the weight, and updates the parameters after reading the whole training set, thereby greatly accelerating the training speed.

And fitting a corresponding functional relation between the temperature condition and the delay time through the BP network. When the method is used, the delay time of each group of delay units at the current temperature can be directly calculated according to the functional relation obtained by the trained network by giving the current operating temperature condition and the initial delay time value obtained by once calibration of the on-chip calibration module during each power-on operation.

The obtained delay time under the current temperature condition can be directly stored in an upper computer and applied to a subsequent data processing system, and meanwhile, the delay time can be transmitted back to an embedded board for storage from the upper computer by using a serial communication module, so that the on-chip use is facilitated.

The pulse interval time calculation formula is:

t＝N＊T+Δt ₁ -Δt ₂

wherein T is the interval time between two pulses, N is the number of the coarse counters with corresponding phases, T is the counter counting period, deltat 1 is the time interval from the edge of the Start signal to the Start of counting the edge of the coarse counter (obtained by delaying the total time by the internal delay unit), and Deltat 2 is the time interval from the edge of the Stop signal to the Stop counting edge of the coarse counter (obtained by delaying the total time by the internal delay unit).

According to a preferred embodiment of the present invention, there is also provided a neural network measurement calibration method for TDL-TDC, including the steps of:

(1) Constructing a TDL-TDC module on an FPGA chip, and completing initial calibration of a delay chain by adopting a code density calibration method to obtain an initial calibration value;

(2) Acquiring the running temperature of the system on the FPGA chip to obtain running temperature information;

(3) And constructing a multi-layer learning network, taking the running temperature information and the initial calibration value as the input of the network, outputting the running temperature information and the initial calibration value as the delay time of the delay unit, and establishing a corresponding nonlinear change relation between the temperature information and the delay time of the delay unit.

According to the system, the corresponding function relation between the temperature and the delay time is obtained through training of the neural network, so that nonlinear calibration can be carried out on each delay part of the delay chain, errors are smaller compared with the linear calibration in the prior art, and meanwhile the inconsistency of each section of the front, middle and rear of the delay chain can be considered; the on-chip stop work is not needed to free time for the on-chip calibration module to re-measure the update delay time, so that the dead time of the system operation is reduced; when the acquired data volume of different temperature calibration samples and different development board types calibration samples is large enough, the TDC system based on neural network calibration can be flexibly used under different temperature change conditions, and meanwhile, the TDC system can be flexibly transplanted in different development board environments, and the network model is retrained when the development boards do not need to be replaced.

In addition, the system in the embodiment moves complex calculation from the on-chip resources to the upper computer, the upper computer finishes calibration and can directly process data at the upper computer, so that the occupation of the on-chip resources is reduced, and the whole structure is easy to realize.

In another embodiment, the neural network may also be deployed onto an FPGA platform. Firstly, constructing a TDL-TDC part on an FPGA platform, and then acquiring different temperatures and corresponding original data samples by using an on-chip calibration module to train an optimally designed network model in a server. And secondly, extracting parameters such as network weight, bias and the like after training optimization is completed, and storing and transplanting relevant parameters into the FPGA. And finally, constructing a neural network structure on the FPGA platform by utilizing the FPGA on-chip structure, resources and network parameters obtained by previous optimization. And inputting the initial value and the temperature into the network-on-chip, and directly calculating to obtain the delay time of the delay unit by matching the TDL-TDC built by the FPGA with the network-on-chip of the FPGA. The system in the embodiment is convenient for the transplanting and moving of the embedded system, can flexibly configure the hardware structure, and when the computer needs to be changed, the FPGA can be reassembled, so that the power consumption is lower than that of the system built by using an upper computer.

In another embodiment, the TDL-TDC and network structure migration may also be solidified in an ASIC, integrating the entire system into one chip. The system in the embodiment has the advantages of lower power consumption, higher speed and highest energy efficiency, has the function of embedded equipment, is more stable, and is favorable for mass production application.

The foregoing descriptions of specific exemplary embodiments of the present invention are presented for purposes of illustration and description. It is not intended to limit the invention to the precise form disclosed, and obviously many modifications and variations are possible in light of the above teaching. The exemplary embodiments were chosen and described in order to explain the specific principles of the invention and its practical application to thereby enable one skilled in the art to make and utilize the invention in various exemplary embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims and their equivalents.

Claims

1. A neural network measurement calibration system for TDL-TDC, comprising:

the temperature sensing module is used for acquiring the operation temperature of the FPGA chip and obtaining operation temperature information;

2. The neural network measurement calibration system for TDL-TDC of claim 1, wherein the learning network, whose samples of network training include the input vector X, the expected output quantity t, the deviation between the network output value Y and the expected output value t, decreases the error in the gradient direction by adjusting the coupling strength Wij of the input node and the hidden node, the coupling strength Tjk between the hidden node and the output node, and a threshold value, and determines the network parameter corresponding to the minimum error through repeated learning training, and the training is stopped.

3. The neural network measurement calibration system for TDL-TDC of claim 1, wherein the learning network, the weight updating step thereof comprises:

4. The neural network measurement calibration system of claim 1, wherein the learning network updates the weights using accumulated errors, and updates the parameters after reading the entire training set.

5. The neural network measurement calibration system for TDL-TDC of claim 1, wherein the TDL-TDC module comprises:

6. The neural network measurement calibration system for TDL-TDC of claim 5, wherein the TDL-TDC module further comprises:

the Wave-unit transmitter module is used for respectively separating the input single Start pulse signal to be measured and Stop pulse signal to be measured into 2 continuous pulse signals, and inputting the separated pulse signals into the fine time measurement module.

7. The neural network measurement calibration system for TDL-TDC of claim 5, wherein the TDL-TDC module further comprises:

8. The neural network measurement calibration system of claim 1, wherein the coarse time measurement module accumulates the time interval to be measured using 2 inverted gray code adders, uses a value of a normal counter when the pulse signal to be measured arrives in the first half period, and uses a value of an inverted counter when the pulse signal to be measured arrives in the second half period.

9. The neural network measurement calibration system for TDL-TDC of claim 1, wherein the result of the fine time measurement module is latched using a two stage flip-flop.

10. A neural network measurement calibration method for TDL-TDC, comprising:

acquiring the running temperature of a system on a chip of the FPGA chip to obtain running temperature information;