CN117155395B

CN117155395B - FPGA-based tap delay chain type TDC coding method and system

Info

Publication number: CN117155395B
Application number: CN202311152578.4A
Authority: CN
Inventors: 孔洁; 安一郎; 颜俊伟; 王泽坤; 佘乾顺
Original assignee: Institute of Modern Physics of CAS
Current assignee: Institute of Modern Physics of CAS
Priority date: 2023-09-07
Filing date: 2023-09-07
Publication date: 2024-03-26
Anticipated expiration: 2043-09-07
Also published as: CN117155395A

Abstract

The invention relates to a method and a system for encoding a tapped delay chain type TDC based on an FPGA, wherein the method comprises the following steps: the segmentation module divides the thermometer code into a plurality of sub-codes with equal number of bits; the precoding module encodes the subcodes, counts the number of logic 1 in the corresponding thermometer code section, and generates precoding zone bits; the signal identification module analyzes the zone bit, finds out the precoding module group where the boundary line of the signal logic 0 and the logic 1 is positioned in the original tap output by identifying the boundary position of the logic 0 and the logic 1, and outputs the corresponding 0-1 edge mark group number and the group number of which the thermometer code is all logic 1 before the group; the data gating module gates and outputs a logic 1 count sum in a precoding group where a logic 0-1 demarcation is positioned according to the 0-1 edge mark; and the multiplication module multiplies the multiplication factor by the thermometer code bit number corresponding to each group of precoding, and adds the logic 1 count sum in the precoding grouping output by the data gating module to obtain the fine time code.

Description

FPGA-based tap delay chain type TDC coding method and system

Technical Field

The invention relates to a tap delay chain type TDC (time-digital converter) coding method and system based on an FPGA (field programmable gate array), and relates to the technical field of high-precision time-digital conversion (TDC).

Background

A Tapped-Delay Line (TDL) Time-to-Digital Converter, TDC) is a Time measurement technique based on a digital logic circuit, and the principle of the technique is to calculate Time by using the transmission Delay of a digital signal in a logic unit, wherein the smaller the Delay effect of the logic unit on the digital signal, the more uniform the Delay Time, the better the Time minimum resolution of the TDC, and the higher the resolution accuracy. Due to the advantages of high counting rate, low dead time, high time resolution precision and simple circuit, the TDL type TDC has wide application in the research fields of high timing precision requirement and high data processing pressure, especially in the fields of nuclear physics and particle physics.

The Field Programmable Gate Array (FPGA) has the advantages of rich digital logic resources and low development cost, and has unique advantages in the research and application of TDL type TDC. The method has the advantages of remarkable improvement of the manufacturing process of the FPGA chip due to the development of the chip manufacturing technology in recent years, rich logic resources, high integration level and low development cost, and the method makes the realization of large-scale and high-precision TDC design on an FPGA platform possible.

The TDL type TDC delays an input signal by using chain-shaped logic units, each logic unit comprises a corresponding tap for reading out the signal, and the TDC system obtains a time measurement result by sampling the read-out signals of all taps and performing coding output. For a large-scale and high-precision TDC system, the timing precision is mainly determined by the size and uniformity of a logic unit of a tap delay chain, and the achievable scale is mainly determined by the resource utilization rate of an encoder. The TDL-type TDC tap output data is typically presented in the form of a thermometer code, where a logic 1 corresponds to the location through which the signal propagates in the delay chain and a logic 0 corresponds to the location to which the signal has not propagated. The thermometer code is usually encoded by a progressive encoding method (for example, wallace encoder) based on a pipeline, the principle is that the tap output of a delay chain is primarily encoded into a plurality of groups of subcodes with shorter digits, then the subcode groups are reduced by progressive encoding of the pipeline, the number of the code bits of each group is increased, and the finally output encoding result is the count value of the thermometer code. The method is stable under the condition of high-speed operation, but the lower the frequency of use of the encoders grouped at the rear end part of the delay chain is due to the randomness of the TDL output, the waste of logic resource occupation can be caused under the condition that the occupied resources of the encoders corresponding to the front end and the rear end of the delay chain are consistent, and the design scale of the TDC system is influenced.

Disclosure of Invention

The present invention aims to solve at least one of the technical problems existing in the prior art. Therefore, the invention aims to provide the FPGA-based tap delay chain type TDC coding method and system with the advantages of resource optimization, simple structure, stable performance and high precision.

In order to achieve the purpose of the aspects, the invention adopts the following technical scheme:

in a first aspect, the present invention provides an FPGA-based tapped delay chain TDC coding system, comprising:

the segmentation module is used for dividing the thermometer code into a plurality of sub-codes with equal number of bits;

the number of the precoding modules is set to be a plurality of groups, each precoding module is used for encoding the sub-codes, counting the number of logic 1 in the corresponding sub-code section, generating one-bit precoding zone bit at the same time, and if the processed sub-codes have logic 1, the precoding zone bit is 1, otherwise, the precoding zone bit is 0;

the signal identification module is used for analyzing the pre-coding flag bit, finding out a pre-coding module where a signal logic 0 and logic 1 boundary line is located in the original tap output by identifying the boundary position of logic 0 and logic 1 in the pre-coding flag bit, and outputting a corresponding logic 0-1 edge flag packet number and the number of groups, namely multiplication factors, where the thermometer codes are all logic 1 before the group;

the data gating module is used for gating and outputting a logic 1 count sum in a precoding packet where a logic 0-1 demarcation is positioned according to the logic 0-1 edge mark packet number;

and the multiplication module is used for multiplying the multiplication factor by the thermometer code bit number corresponding to each group of precoding, and adding the result obtained by multiplying the multiplication factor by the logic 1 count sum in the precoding grouping output by the data gating module to obtain the fine time code.

Further, the FPGA adopts Kintex-7 series XC7K325TFFG900-2 model designed and developed based on Xilinx corporation.

Further, the pre-coding module is realized by adopting a lookup table and an adder in the FPGA, and the realization process is as follows: the lookup table logic unit is of a 6-input and 1-output structure, the structure is used for counting the logic 1 number in the segmented subcode by taking 6 bits as a group, a 3-bit counting result is obtained, and the adder is used for adding the counting results of the multiple lookup table structures covering the whole segmented subcode to obtain the logic 1 count of the whole segmented subcode.

Further, the signal identification module adopts a lookup table or a multipath gating device in the FPGA, when the number of the precoding module groups is small, the signal identification module is realized by using the FPGA lookup table, and according to a preset truth table and the precoding zone bit of each group of precoding modules, the precoding group number of a logic 0 and 1 boundary line is directly output; when the number of the precoding module groups is large, the judgment and selection of the marker bits of each group of the precoder is realized through a multipath gate in the FPGA.

Further, the data strobe module is realized by adopting a multiplexing gate and a register of an FPGA: and each group of pre-coding modules outputs and stores the signals in a one-stage or multi-stage register, waits for the gating signals from the signal identification module, and outputs corresponding sub-coding results through a multi-path gating device in the FPGA according to the gating signals.

Further, the multiplication module is implemented by adopting a register or a combination of a multiplier and an adder, wherein when the multiplication module is implemented by adopting a multiplier and adder structure in an FPGA, the calculation process of the logic 1 counting result+ of the sub-code group in which the boundary line between logic 0 and 1 is positioned (the group number before the group is multiplied by the thermometer code number contained in each group of sub-codes); in the case that the number of sub-code bits is the power of 2, the multiplication in the calculation is directly accomplished by shifting, and the multiplication module is implemented by using a register.

In a second aspect, the present invention provides a method for encoding a tapped delay chain type TDC encoding system based on an FPGA, including:

s1: dividing thermometer codes into a plurality of subgroups of set digits and inputting the subgroups into corresponding pre-coding modules;

s2: each precoding module calculates the number output count sum of logic 1 in the input thermometer codes and simultaneously generates a precoding zone bit;

s3: the obtained precoding flag bits of a plurality of groups are formed into a thermometer code according to the sequence of the first group at the lowest position and the last group at the highest position, the number of the precoding module groups where the logic 1 is obtained by calculating the number of the logic 0-1 boundary lines, and the number of groups where the thermometer codes are all logic 1 before the group is obtained, namely the multiplication factor n;

s4: acquiring a precoding grouping value at which a logic 0-1 boundary is positioned according to the S3, and gating and outputting a thermometer code logic 1 count sum k corresponding to the precoding module;

s5: multiplying the number n of groups calculated in the step S3 by the number of thermometer code bits processed by each group of precoding modules, namely, setting a number n, and adding the number n with k output in the step S4 to obtain thermometer code counts, namely: the set digit n+k.

Further, when the number of taps of the delay chain is 192, the implementation process of the coding method includes:

s1: dividing 192-bit thermometer codes into 6 groups of 32-bit subgroups and inputting the subgroups into corresponding pre-coding modules;

s2: each pre-coding module calculates the number output count sum of logic 1 in the input 32-bit thermometer code and simultaneously generates 6 flag bits;

s3: the obtained 6 groups of flag bits are formed into a thermometer code according to the sequence of the first group at the lowest position and the last group at the highest position, the number of the precoding module groups where the logic 1 is obtained by calculating the number of the logic 0-1 boundary lines, and the number of groups where the thermometer codes are all logic 1 before the group is obtained, namely the multiplication factor n;

s4: according to S3, obtaining a precoding grouping value at which a logic 0-1 boundary is positioned, and gating and outputting thermometer code logic 1 count and k corresponding to the precoding module grouping;

s5: multiplying the multiplication factor n calculated in the step S3 by the thermometer code bit number 32 processed by each group of precoding modules, namely 32×n, and adding the thermometer code count and k output in the step S4 to obtain a represented 192-bit thermometer code count: 32 x n+k.

The invention adopts the technical proposal and has the following characteristics:

1. the FPGA-based tap delay chain type TDC encoder provided by the invention provides a reliable method and a path for improving the logic resource utilization rate of the TDC, and provides a TDC design scheme with optimized resource, simple structure, stable performance and high precision for a high-speed high-precision timing system based on the FPGA.

2. Compared with the traditional TDC based on the progressive coding method, the method saves about 17% of logic resources under the condition of not affecting time resolution precision and system stability, and has important significance in the aspects of upsizing, systemizing, reducing design cost and the like of the TDL type TDC design based on the FPGA.

3. The invention relates to a high-speed, high-precision and large-scale TDL type TDC based on an FPGA, which is a coding system with high resource utilization rate and stability under a high-speed clock.

4. The invention provides a new coding method from thermometer codes to binary original codes, and provides a digital logic implementation scheme based on the method, which has a certain pushing effect on the technical development of the related fields.

In conclusion, the invention can be widely applied to the field of nuclear physics and particle physics.

Drawings

Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Like parts are designated with like reference numerals throughout the drawings. In the drawings:

fig. 1 is a schematic diagram of coding principle according to an embodiment of the present invention.

Fig. 2 is a schematic diagram of an encoding system according to an embodiment of the present invention.

Fig. 3 is a schematic diagram of an encoding method according to an embodiment of the present invention.

Detailed Description

It is to be understood that the terminology used herein is for the purpose of describing particular example embodiments only, and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. The terms "comprises," "comprising," "includes," "including," and "having" are inclusive and therefore specify the presence of stated features, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and/or groups thereof. The method steps, processes, and operations described herein are not to be construed as necessarily requiring their performance in the particular order described or illustrated, unless an order of performance is explicitly stated. It should also be appreciated that additional or alternative steps may be used.

Although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms may be only used to distinguish one element, component, region, layer or section from another region, layer or section. Terms such as "first," "second," and other numerical terms when used herein do not imply a sequence or order unless clearly indicated by the context. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the example embodiments.

For ease of description, spatially relative terms, such as "inner," "outer," "lower," "upper," and the like, may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. Such spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures.

The only logical 0 and logical 1 boundary corresponds to the location in the delay chain to which the signal propagates due to the non-bit-reversal nature of the thermometer code. Thus, the encoding method of the present invention encodes the tap output of the delay chain separately in segments. As shown in fig. 1, assuming that the number of tap outputs is m×n, the tap outputs are divided into M subsections, each subsection contains N thermometer codes, and only one subsection contains a logic 0-1 boundary, and the section where the signal propagates is determined by searching the logic 0-1 boundary, the thermometer codes in the preceding section of the subsection are all logic 1, and the thermometer codes in the following section are all logic 0. Therefore, only the segment where the logic 0-1 boundary is located is specifically encoded, the encoding process of the previous segment is simplified into the number of segments multiplied by the number of segments, and finally the count of logic 1 in the thermometer code output by the delay chain tap is obtained, so that the encoding number of bits to be processed in the encoding process is simplified, and the logic resource consumption of an encoding system is saved. The invention provides a method and a system for encoding a tapped delay chain type TDC based on an FPGA, which comprises the following steps: the segmentation module is used for dividing the thermometer code into a plurality of sub-codes with equal number of bits; the number of the precoding modules is set to be a plurality of groups, each precoding module is used for encoding the sub-codes, counting the number of logic 1 in the corresponding sub-code section, generating one-bit precoding zone bit at the same time, and if the processed sub-codes have logic 1, the precoding zone bit is 1, otherwise, the precoding zone bit is 0; the signal identification module is used for analyzing the pre-coding flag bit, finding out a pre-coding module where a signal logic 0 and logic 1 boundary line is located in the original tap output by identifying the boundary position of logic 0 and logic 1 in the pre-coding flag bit, and outputting a corresponding logic 0-1 edge flag packet number and the number of groups, namely multiplication factors, where the thermometer codes are all logic 1 before the group; the data gating module is used for gating and outputting a logic 1 count sum in a precoding packet where a logic 0-1 demarcation is positioned according to the logic 0-1 edge mark packet number; and the multiplication module is used for multiplying the multiplication factor by the thermometer code bit number corresponding to each group of precoding, and adding the result obtained by multiplying the multiplication factor by the logic 1 count sum in the precoding grouping output by the data gating module to obtain the fine time code. Therefore, the invention provides a new thermometer code to binary original code coding method, and provides a digital logic implementation scheme based on the method, which has a certain pushing effect on the technical development of the related field.

Exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present invention are shown in the drawings, it should be understood that the present invention may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. The FPGA of the embodiment can be realized by adopting a Kintex-7 series XC7K325TFFG900-2 type FPGA chip (hereinafter referred to as a K7 chip) designed and developed based on Xilinx company, and the related system modules are built by a bottom logic unit provided by the FPGA chip.

Embodiment one: based on the above principle, as shown in fig. 2, the tapped delay chain type TDC coding system based on the FPGA provided in this embodiment includes a segmentation module, a pre-coding module, a signal identification module, a data strobe module and a multiplication module.

The segmentation module is used for dividing the thermometer code output by the tap latch unit into a plurality of sub-codes with equal bit numbers;

the number of the precoding modules is several, each precoding module is used for encoding the corresponding subcode, counting the number of logic 1 in the corresponding thermometer code section, outputting the number to the data gating module, generating one-bit precoding zone bit at the same time, sending the one-bit precoding zone bit to the signal identification module, and if the processed thermometer code has the logic 1, the zone bit is 1, otherwise, the zone bit is 0;

the signal identification module is used for analyzing the zone bit sent by each group of pre-coding modules and is realized by adopting an LUT structure in the FPGA chip. Because of the non-bit reversal characteristic of the thermometer codes, the flag bits output by the pre-coding module also form a group of thermometer codes, so that the signal identification module can find the pre-coding module group where the signal logic 0 and logic 1 boundary line is positioned in the original tap output by identifying the boundary position of logic 0 and logic 1 in the pre-coding flag bits, and output the corresponding group number (namely 0-1 edge flag) and the group number (multiplication factor) where the thermometer codes are all logic 1 before the group;

the data gating module is used for gating and outputting the precoding grouping values with logic 0-1 boundaries according to the 0-1 edge marks, and is mainly realized by a Multiplexer (MUX) in the chip.

And the multiplication module is used for multiplying the multiplication factor by the thermometer code bit number corresponding to each group of precoding, and adding the precoding grouping thermometer code count value of the logic 0-1 boundary outputted by the data gating module to the obtained result to obtain the final fine time code.

In a preferred embodiment of the present invention, the pre-coding module is mainly used for calculating the number of logical 1 in each segment subcode, and because the number of thermometer code bits to be processed is small, the pre-coding module can be implemented by using a Look-Up Table (LUT) and an adder inside the FPGA chip. Because the lookup table logic unit provided by the FPGA chip is of a 6-input and 1-output structure, the structure can be used for counting the logic 1 number in the segmented subcode by taking 6 bits as a group, and a 3-bit counting result is obtained; and adding the counting results of the plurality of lookup table structures covering the whole segment subcode by using an adder, thereby obtaining the logic 1 count of the whole segment subcode.

In a preferred embodiment of the present invention, the signal recognition module may be implemented by a logic unit such as a look-up table or a multiplexer in the FPGA according to the number of the precoding module groups. When the number of the precoding module groups is small, for example, no more than 6 groups are needed, the precoding module groups can be directly realized by using a lookup table in the FPGA chip, and the precoding group numbers where the boundary lines of logic 0 and 1 are positioned are directly output according to a preset truth table and the zone bits of each group of precoders; when the number of the precoding module groups is large, judgment and selection of the marker bits of each group of the precoder are realized through a multipath gate in the FPGA chip.

In a preferred embodiment of the present invention, the data strobe module is mainly used for strobe scheduling of output data of the pre-encoding module, and is implemented by a multi-path strobe and a register inside the FPGA. Each group of pre-coding modules outputs and stores in a one-stage or multi-stage register, and waits for a gating signal from the signal identification module; and outputting the corresponding sub-coding result to a multiplication module of the next stage through a multi-path gate in the FPGA chip according to the gating signal.

In a preferred embodiment of the present invention, the multiplication module is composed of a multiplier and an adder, and in some specific cases, a more compact structure may be used, for example, in the case that the number of sub-code bits is the power of 2, the multiplication module may be implemented directly using a register. In general, this can be achieved using multiplier and adder structures inside the FPGA chip: calculating the logical 1 count result + (the number of groups before the grouping x the number of thermometer codes contained in each group of subcodes) of the subcode group where the logical 0-1 boundary line is located; in the case where the number of subcode bits is a power of 2, the multiplication in the calculation can be accomplished directly using a shift, and the module can be implemented directly using registers.

Embodiment two: the specific implementation process of the FPGA-based tap delay chain type TDC coding method of the embodiment is described in detail below with reference to specific embodiments. The number of taps of the delay chain adopted in the embodiment is 192, so the code design is to process 192-bit thermometer code input signals, the working clock frequency is selected to be 500MHz, and the FPGA-based tap delay chain type TDC coding method provided by the embodiment comprises the following steps:

s2: each pre-coding module calculates the number of logic 1 in the input 32-bit thermometer code, outputs the number as the count sum of bit width 6 bits, and simultaneously respectively performs bit pressing or processing on all 6bit outputs to generate 6 total flag bits of each group of 1 bit;

s3: the 1bit zone bit of the obtained 6 groups of precoding modules is formed into a 6bit thermometer code according to the sequence of the first group at the lowest position and the last group at the highest position, the number of precoding modules with logic 1 in the thermometer code is calculated to obtain the number of groups of precoding modules with logic 0-1 boundary lines, 3bit data n (namely binary original code form of the thermometer code) is output, the value of the data is equal to the number of groups of precoding modules with logic 0-1 boundary lines minus 1, and the number of groups which are all logic 1 is input before the corresponding groups;

s4: finding out a corresponding 6bit thermometer code logic 1 count and k of the grouping gating output of the precoding module according to the S3;

s5: multiplying the 3bit group number n obtained in the step S3 by the thermometer code bit number 32 processed by each group of pre-coding modules, namely 32 x n, and adding the calculated number n with the 6bit thermometer code count and k output in the step S4 to obtain 192-bit thermometer code count expressed in a binary original code form, namely 32 x n+k, wherein the bit width is 8 bits.

In summary, the embodiment can realize stable encoding processing of dead time of 4ns for delay chain output with the number of taps of 192 bits under 500MHz operation all the time, and the encoding method remarkably improves the utilization rate of logic resources of the TDC encoder and has important significance for large-scale design of the TDC system.

In this specification, each embodiment is described in a progressive manner, and identical and similar parts of each embodiment are all referred to each other, and each embodiment mainly describes differences from other embodiments. In the description of the present specification, reference to the terms "one preferred embodiment," "further," "specifically," "in the present embodiment," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the embodiments of the present specification. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. An FPGA-based tapped delay-chain TDC coding system, comprising:

2. The FPGA-based tapped delay chain TDC coding system of claim 1, wherein the FPGA is model number kinex-7 series XC7K325TFFG900-2, which is developed based on the design of Xilinx corporation.

3. The FPGA-based tap-delay-chain TDC coding system according to claim 1 or 2, wherein the pre-coding module is implemented by using a look-up table and an adder inside the FPGA, and the implementation process is as follows: the lookup table logic unit is of a 6-input and 1-output structure, the structure is used for counting the logic 1 number in the segmented subcode by taking 6 bits as a group, a 3-bit counting result is obtained, and the adder is used for adding the counting results of the multiple lookup table structures covering the whole segmented subcode to obtain the logic 1 count of the whole segmented subcode.

4. The FPGA-based tap-delay-chain TDC coding system according to claim 1 or 2, wherein the signal identifying module uses a look-up table or a multi-way gate in the FPGA, and when the number of the precoding module groups is small, uses the FPGA look-up table to implement, and directly outputs the precoding group number where the boundary of logic 0 and 1 is located according to a predetermined truth table and the precoding flag bits of each group of precoding modules; when the number of the precoding module groups is large, the judgment and selection of the marker bits of each group of the precoder is realized through a multipath gate in the FPGA.

5. The FPGA-based tapped delay chain TDC coding system according to claim 1 or 2, wherein the data strobe module is implemented by multiplexing gates and registers using an FPGA: and each group of pre-coding modules outputs and stores the signals in a one-stage or multi-stage register, waits for the gating signals from the signal identification module, and outputs corresponding sub-coding results through a multi-path gating device in the FPGA according to the gating signals.

6. The FPGA-based tap-delay-chain TDC coding system according to claim 1 or 2, wherein the multiplication module is implemented using a register or a combination of multipliers and adders, and wherein when the multiplication module is implemented using an intra-FPGA multiplier and adder structure, the calculation process of the logical 1 count result + (the number of groups before the grouping x the number of thermometer codes contained in each group of subcodes) of the subcode group where the boundary between logical 0 and 1 is located; in the case that the number of sub-code bits is the power of 2, the multiplication in the calculation is directly accomplished by shifting, and the multiplication module is implemented by using a register.

7. An encoding method of an FPGA-based tap-delay chain TDC encoding system according to any one of claims 1 to 6, comprising:

8. The encoding method according to claim 7, wherein the encoding method implementation process when the number of taps of the delay chain is 192 comprises: