CN106779056A - For the spiking neuron hardware structure of AER feed forward classification systems - Google Patents

Abstract

The present invention relates to AER imageing sensor field of image recognition, to meet requirement of the event-driven feed forward classification system for real-time, parallel processing and miniaturization based on AER imageing sensors, the present invention is intended to provide a kind of SNN spiking neuron hardware based on FPGA platform realizes structure.The technical solution adopted by the present invention is, for the spiking neuron hardware structure of AER feed forward classification systems, by weights storage area, weights read-write gate, membrane potential parallel multiplication, the PSP function generators of more vairable, triggering determining device, control and sequential and modified weight module, 7 are partly constituted altogether.Present invention is mainly applied to imageing sensor image recognition occasion.

Description

For the spiking neuron hardware structure of AER feed forward classification systems

Technical field

The present invention relates to AER imageing sensor field of image recognition, more particularly to one kind is for AER image recognitions classification arteries and veins The neuron hardware rushed in neutral net is realized.

Background technology

AER (Address-Event Representation, AER, address-representations of events) imageing sensor real-time detection The change of target scene, compared to the conventional image sensor based on " frame scan " imaging mode, can filter static background picture Prime number evidence, is greatly reduced redundant data.AER only exports the asynchronous digital flow of event of relevant information, and this causes processing system below System can be designed as complete event-driven.

Event-driven feed forward classification system based on AER imageing sensors, it is similar to other categorizing systems, two can be divided into Point：Feature extraction and classification.Characteristic extraction part uses Gabor anisotropic filters and maximum operation, and classifies and then use arteries and veins Rush neutral net (Spiking Neuron Networks, SNN).First with the difference hardware in AER pixels, threshold value is reached When OPADD flow of event, and be advanced into the anisotropic filter based on Gabor functions, convolution knot of the output comprising characteristic information Really, feature extraction is completed.Each output includes appropriate address coordinate, is specifying in the range of acceptance region, using maximum operation Non-significant information is filtered, then by TFS (Time-to-first spike) unit, impulse response is converted to, there is provided to SNN Classified.

For the requirement of AER output informations and categorizing system, from the LIF (Leakage in the numerous models of SNN Integrate-and-fire) model.The input of LIF produces postsynaptic potential (postsynaptic by TFS Potential, PSP), with rapid increase and the slow shape for declining.It is strong with weights cynapse to be represented between each neuron Degree, the membrane potential of neuron is obtained by the weighted sum superposition of the PSP of all input pulses.It is compared by with threshold value, is determined Whether neuron triggers, and meets the classification task that real world is based on stimulating.If SNN training stages neuron should be triggered, And it is practically without triggering, then the weights at membrane potential peak value (tmax) place can be improved.If should not trigger, and actually touch Hair, then can reduce the weights at membrane potential peak value.If errorless, without amendment.During test, by counting touching for corresponding neuron Hair-like state realizes classification.

The SNN hardware configurations of the categorizing system are as shown in Figure 1.Hardware configuration includes feature input, pulse coder, control Exported with sequential, spiking neuron and triggering state, altogether 5 parts.Input comprising characteristic information enters pulse code Device, in the presence of control and sequential, into spiking neuron, carries out cumulative grade of corresponding weights and operates, and then carries out threshold value Compare, judge the output of triggering state.The feed forward classification system of AER imageing sensors, at the information of AER chips output Reason, completes feature extraction and reduces non-significant feature by Gabor convolution and maximum operation, and output information enters and uses LIF The SNN networks of neuron, wherein comprising address information and temporal information, address information can know the location of pixels that event is produced And respective filter species, temporal information can know event occur time.Pulse coder operation principle is：If net The input quantity of network is N, and a pulse can be regularly activated when being input into effective, and pulse is not produced when without effectively input.

Current SNN algorithms rely primarily on software realization, and speed is slow, and degree of concurrence is low, it is impossible to carry out real-time processing.And it is soft Part needs larger computer supported, in addition to relatively costly, cannot also realize the miniaturization of equipment.In order to meet based on AER The event-driven feed forward classification system of imageing sensor to miniaturization and real-time requirement, for the SNN hardware realities for being used Now become very necessary, and most important in SNN hardware is exactly high number, the spiking neuron with reproducibility.Scene Programmable gate array (Field-Programmable Gate Array, FPGA) is in recent years obtaining the development of high speed, holds very much Easily realize high speed, parallel computation.Realize that the spiking neuron of SNN has for the performance of the categorizing system using FPGA extremely to weigh The meaning wanted.

The content of the invention

To overcome the deficiencies in the prior art, meet the event-driven feed forward classification system based on AER imageing sensors for The requirement of real-time, parallel processing and miniaturization, the present invention is intended to provide a kind of SNN spiking neurons based on FPGA platform are hard Part realizes structure.The technical solution adopted by the present invention is, for the spiking neuron hardware structure of AER feed forward classification systems, by Weights storage area, weights read-write gate, membrane potential parallel multiplication, the PSP function generators of more vairable, triggering determining device, control and when Sequence and modified weight module, 7 are partly constituted altogether, and each several part is specific as follows：

(1) control and sequential and modified weight module：For provide two internal clockings, CLK and SLOW_CLK, wherein The CLK clock cycle is much smaller than SLOW_CLK, and proportion is 1:10000 to 1:500000, for pulse code sampling, membrane potential Compare, determine the speed of network processes；SLOW_CLK is used to coordinate the work of inside neurons, less than a SLOW_CLK Cycle in be obtained in that the membrane potential accumulation result of all of input；RST signal is additionally needed for reset zero setting, and RE Read signal and WE write signals are read and write for weight；

(2) weights read-write gate：The mode of operation of weights is selected by control signal, in read phase, connection weight storage Storage, there is provided appropriate weights, in write phase, connection to input realizes right value update by outside port；

(3) weights holder：It is used to store weights in inside neurons, each neuron weights holder space is input Quantity is multiplied by data width；

(4) the PSP function generators of more vairable：PSP is that have the rapid shape for rising and slowly declining, and (1) is PSP function formulas：

Wherein, K is PSP functional values, and V0 controls rise maximum, when τ m and τ s are the control raising and lowering gradients here Between constant, two constant relationships continue 30 SLOW_CLK cycles altogether for τ s=τ m/4, PSP waveforms, and 30 can be used according to formula Individual discrete point storage correspondence PSP functional values, form 30 look-up tables of data width；

(5) membrane potential parallel multiplication：Including a multiplier and an adder, in each SLOW_CLK cycles, root It is weighted according to formula (2), wherein n is the quantity of all inputs in accumulation period, Δ t is current time and last pulse Time difference, by the direct evaluation of PSP look-up tables, ω is correspondence weights, is read by weights holder：

(6) determining device is triggered：In each clk cycle, the result of membrane potential parallel multiplication all can be with membrane potential threshold value It is compared, if threshold value reaches, produces triggering state, does not trigger otherwise；Triggering determining device includes a comparator, produces SNN triggering states are exported；

(7) modified weight module：When learning for SNN network trainings, the neuron weights to erroneous trigger carry out amendment.

SNN network trainings rule is as follows：Should trigger and not trigger or should not trigger and trigger, read the PSP function generators of more vairable Response numerical value, is multiplied by after learning rate the former weights position that is added to, and is updated；Using internal PSP generators and multiplier reality Existing modified weight operation.

7 part flows are：First by read-write control signal, carry out the renewal and reading of weight；In the stage of reading, Namely test phase, weights are obtained according to the address being input into from weights storage area, obtain PSP from the PSP function generators of more vairable in addition Functional value, it is common to enter in membrane potential parallel multiplication, it is weighted；Result of calculation each clock cycle can with touch Hair threshold value is compared, and the triggering state of neuron is judged using comparator；In the study stage, weights are carried out if desired and is repaiied Just, read-write control signal is now in write phase, using weights correcting module, reads the response numerical value of the PSP function generators of more vairable, right The weights of weights storage element are modified.

7 parts are integrated in on-site programmable gate array FPGA, and weight storage device is comprehensive into storage RAM.

The features of the present invention and beneficial effect are：

The present invention realizes the hardware configuration of SNN spiking neurons based on FPGA platform, meets based on AER image sensings The event-driven feed forward classification systems soft ware of device support under speed is slow, the inferior position such as degree of parallelism is low, high cost, volume are big, favorably Miniaturization and real-time in equipment.

Brief description of the drawings：

Fig. 1 SNN network hardware architectures.

Fig. 2 neuron hardware configurations.

The input pulses of Fig. 3 tetra- are encoded.

Specific embodiment

Neuron hardware configuration for categorizing system SNN proposed by the present invention is as shown in Figure 2.Spiking neuron can have Body is divided into weights storage area, weights read-write gate, membrane potential parallel multiplication, the PSP function generators of more vairable, triggering determining device, control Make and sequential and modified weight module, altogether 7 parts, functions are as follows：

(1) control and sequential：In order to meet the coordination of inside neurons and the speed of network processes, it is necessary to using in two Portion's clock, CLK and SLOW_CLK, wherein CLK clock cycle are much smaller than SLOW_CLK, are sampled with pulse code, membrane potential ratio Compared with determining the speed of network processes.SLOW_CLK is used to coordinate the work of inside neurons, less than SLOW_CLK The membrane potential accumulation result of all of input is obtained with cycle.RST signal is additionally needed for reset zero setting, and RE Read and write for weight with WE.

(2) weights read-write gate：The mode of operation of weights is selected by control signal.In read phase, connection weight storage Storage, there is provided appropriate weights, in write phase, connection to input realizes right value update by outside port.

(3) weights holder：It is used to store weights in inside neurons.Each neuron weights holder space is input Quantity is multiplied by data width.Storage RAM is integrated into FPGA.

(4) the PSP function generators of more vairable：PSP is that have the rapid shape for rising and slowly declining, and (1) is PSP function formulas：

Wherein, K is PSP functional values, and V0 controls rise maximum, when τ m and τ s are the control raising and lowering gradients here Between constant, two constant relationships continue 30 SLOW_CLK cycles altogether for τ s=τ m/4, PSP waveforms, and 30 can be used according to formula Individual discrete point storage correspondence PSP functional values, form 30 look-up tables of data width.

(5) membrane potential parallel multiplication：Including a multiplier and an adder, in each SLOW_CLK cycles, root It is weighted according to formula (2), wherein Δ t is the time difference of current time and last pulse, can be direct by PSP look-up tables Evaluation, ω is correspondence weights, is read by weights holder.

(6) determining device is triggered：In each clk cycle, the result of membrane potential parallel multiplication all can be with membrane potential threshold value It is compared, if threshold value reaches, produces triggering state, does not trigger otherwise.Triggering determining device includes a comparator, produces SNN triggering states are exported.

(7) modified weight module：When learning for SNN network trainings, the neuron weights to erroneous trigger carry out amendment, Learning rules are as follows：Should trigger and not trigger or should not trigger and trigger, read PSP function generators of more vairable response numerical value, be multiplied by Be added to former weights position after habit speed, is updated.Realize that modified weight is grasped using internal PSP generators and multiplier Make.

First by read-write control signal, carry out the renewal and reading of weight.In the stage of reading, that is, test rank Section, the address according to input obtains weights from weights storage area, obtains PSP functional values from PSP functions generation unit in addition, jointly Into in membrane potential parallel multiplication, it is weighted.Result of calculation can be carried out in each clock cycle with activation threshold value Compare, the triggering state of neuron is judged using comparator.In the study stage, modified weight, Read-write Catrol are carried out if desired Signal is now in write phase, using weights correcting module, reads the response numerical value of the PSP function generators of more vairable, stores single to weights The weights of unit are modified.

According to the hardware configuration of the SNN spiking neurons based on FPGA proposed by the present invention, disclosure satisfy that based on AER images The requirement of the event-driven feed forward classification system of sensor.The parameters such as input and output quantity, sample clock frequency and data width It is adjustable.PSP functions durations are 30 SLOW_CLK, comprising 30 equidistant discrete points.The CLK clock cycle is much smaller than SLOW_CLK, may be selected 1:10000 ratio.The pulse coder of SNN input for 4 when principle as shown in figure 3, its In effectively input is represented with white block, black patch represents invalid input.Weights storage area size is relevant with input quantity and data width. Because advantage of the AER imageing sensors on redundant data is reduced and feed forward classification system filter the operation of non-significant feature, Actual SNN inputs quantity can be much smaller than the required input quantity of full connection.Data width is determined by required precision, is defaulted as 16 bit width.The present invention is based on FPGA hardware platform, thus with extremely strong flexibility and low-cost advantage, by parameter Modification, the spiking neuron structure of special SNN neutral nets can be obtained, by parallel data process, solve software processing Platform low speed problem.

Claims (4)

1. a kind of spiking neuron hardware structure for AER feed forward classification systems, it is characterized in that, by weights storage area, weights Read-write gate, membrane potential parallel multiplication, the PSP function generators of more vairable, triggering determining device, control and sequential and modified weight mould Block, 7 are partly constituted altogether, and each several part is specific as follows：

(1) control and sequential and modified weight module：For providing two internal clockings, wherein CLK and SLOW_CLK, CLK Clock cycle is much smaller than SLOW_CLK, and proportion is 1:10000 to 1:500000, for pulse code sampling, membrane potential ratio Compared with determining the speed of network processes；SLOW_CLK is used to coordinate the work of inside neurons, less than SLOW_CLK The membrane potential accumulation result of all of input is obtained in that in cycle；RST signal is additionally needed to read for the zero setting that resets, and RE Signal and WE write signals are read and write for weight；

(2) weights read-write gate：The mode of operation of weights is selected by control signal, in read phase, connection weight holder, Appropriate weights are provided, in write phase, connection to input realizes right value update by outside port；

(3) weights holder：It is used to store weights in inside neurons, each neuron weights holder space is input quantity It is multiplied by data width；

(4) the PSP function generators of more vairable：PSP is that have the rapid shape for rising and slowly declining, and (1) is PSP function formulas：

$K=V_0\×\left(\exp \right(\frac{-t}{{\mathrm{\τ}}_m})-\exp (\frac{-t}{{\mathrm{\τ}}_s}\left)\right)---\left(1\right)$

Wherein, K is PSP functional values, and V0 controls rise maximum, and τ m and τ s are to control the time of the raising and lowering gradient normal here Number, two constant relationships continue 30 SLOW_CLK cycles altogether for τ s=τ m/4, PSP waveforms, according to formula can use 30 from Scatterplot storage correspondence PSP functional values, form 30 look-up tables of data width；

(5) membrane potential parallel multiplication：Including a multiplier and an adder, in each SLOW_CLK cycle, according to public affairs Formula (2) is weighted, and wherein n is the quantity of all inputs in accumulation period, Δ t be current time and last pulse when Between it is poor, by the direct evaluation of PSP look-up tables, ω is correspondence weights, is read by weights holder：

$u\left(t\right)=\underset{i=1}{\overset{n}{\Σ}}\mathrm{\ω}i\×K\left(\mathrm{\Δ}t\right)---\left(2\right)$

(6) determining device is triggered：In each clk cycle, the result of membrane potential parallel multiplication can all be carried out with membrane potential threshold value Compare, if threshold value reaches, produce triggering state, do not trigger otherwise；Triggering determining device includes a comparator, produces SNN Triggering state is exported；

(7) modified weight module：When learning for SNN network trainings, the neuron weights to erroneous trigger carry out amendment.

2. the spiking neuron hardware structure of AER feed forward classification systems is used for as claimed in claim 1, it is characterized in that, SNN nets Network training rules are as follows：Should trigger and not trigger or should not trigger and trigger, read PSP function generators of more vairable response numerical value, be multiplied by Be added to former weights position after learning rate, is updated；Realize that modified weight is grasped using internal PSP generators and multiplier Make.

3. the spiking neuron hardware structure of AER feed forward classification systems is used for as claimed in claim 1, it is characterized in that, 7 portions Split flow is：First by read-write control signal, carry out the renewal and reading of weight；In the stage of reading, that is, test rank Section, the address according to input obtains weights from weights storage area, obtains PSP functional values from the PSP function generators of more vairable in addition, enters jointly Enter in membrane potential parallel multiplication, be weighted；Result of calculation can be compared in each clock cycle with activation threshold value Compared with judging the triggering state of neuron using comparator；In the study stage, modified weight, Read-write Catrol letter are carried out if desired Number write phase is now in, using weights correcting module, the response numerical value of the PSP function generators of more vairable is read, to weights storage element Weights be modified.

4. the spiking neuron hardware structure of AER feed forward classification systems is used for as claimed in claim 1, it is characterized in that, 7 portions Divide and be integrated in on-site programmable gate array FPGA, weight storage device is comprehensive into storage RAM.