CN215769392U - Time-to-digital conversion device and optical ranging sensor - Google Patents

Abstract

The application provides a time-to-digital conversion device and an optical ranging sensor, wherein the time-to-digital conversion device comprises a clock network module, a fine-granularity counting module, a coarse-granularity counting module and a duration calculation module. This application passes through a plurality of second time stamp signals of clock network module according to the first time stamp signal of input to fine grit count module output, each second time stamp signal all is the signal that first time stamp signal obtained after the same time delay, sample at different moments through fine grit count module to each second time stamp signal, and confirm the fine grit count according to the sampling result of each second time stamp signal, confirm the coarse grain count of second time stamp signal through coarse grit count module, confirm the timing value according to fine grit count and coarse grain count through time length calculation module, thereby make time digital conversion device timing precision high, be convenient for realize, it is nimble and scalable low cost.

Description

Time-to-digital conversion device and optical ranging sensor

Technical Field

The application belongs to the technical field of time measurement, and particularly relates to a time-to-digital conversion device and an optical ranging sensor.

Background

In the technical fields of sensors and instrumentation, many applications require the precise measurement of the time interval between two events. Taking an optical distance measuring sensor as an example, a widely used distance measuring method is a pulse Time-of-Flight (pulsed ToF) method, which works on the principle of emitting a short-Time light pulse with high instantaneous power, then measuring the Time interval of the pulse going to a target and returning, and calculating the distance between the target and the sensor by combining the speed of light. Considering the extremely high propagation speed of light, to achieve a desired distance resolution, such as 1 cm, the timing accuracy is required to be at least tens of picoseconds, which poses a great challenge to the design of timing schemes.

The conventional timing device is usually an Application Specific Integrated Circuit (ASIC) developed, and this method has a long development period and high cost, although it has high flexibility and can achieve high performance.

SUMMERY OF THE UTILITY MODEL

The application aims to provide a time-to-digital conversion device and aims to solve the problems that a traditional timing device is long in development period and high in product cost.

In order to achieve the above object, in a first aspect, an embodiment of the present application provides a time-to-digital conversion apparatus, including a clock network module, a fine-grain counting module, a coarse-grain counting module, and a duration calculating module;

the clock network module is used for outputting a plurality of second timestamp signals to the fine-grained counting module according to the input first timestamp signals, and each second timestamp signal is a signal obtained after the first timestamp signal is subjected to the same time delay;

the fine-grained counting module is used for sampling the second timestamp signals and determining fine-grained counting according to sampling results of the second timestamp signals, wherein sampling points of the second timestamp signals are different;

the coarse grain count module is to determine a coarse grain count of the second timestamp signal;

the time length calculating module is used for determining a timing value according to the fine granularity count and the coarse granularity count.

In one possible implementation of the first aspect, the fine-grain count module includes a multi-stage delay chain unit, a sampling unit, and a fine-grain count encoder unit;

the multistage delay chain unit is used for outputting the second timestamp signals after different delays are carried out on the second timestamp signals to obtain a plurality of third timestamp signals;

the sampling unit is used for sampling each third timestamp signal at the same moment;

the fine grain count encoder unit is configured to determine a fine grain count according to a sampling result of each of the third timestamp signals.

In another possible implementation manner of the first aspect, the multi-stage delay chain unit includes a plurality of delay chains, and delay amounts of the delay chains are different.

In another possible implementation manner of the first aspect, the fine-grain counting module further includes a bit-order reordering unit, and the bit-order reordering unit is configured to reorder the sampling result of each third timestamp signal and output the result to the fine-grain counting encoder unit.

In another possible implementation manner of the first aspect, the time-to-digital conversion apparatus further includes a clock management module, and the clock management module is configured to provide a sampling clock for the fine-grained counting module, and provide a system clock or a sampling clock for the coarse-grained counting module.

In another possible embodiment of the first aspect, the clock network module is any one or a variant network of any one of the following clock networks: global clock network, local clock network, horizontal clock network and IO clock network.

In another possible implementation of the first aspect, the sampling unit is a serial-to-parallel converter, a double rate register, or a general register.

In another possible implementation manner of the first aspect, the fine-grained counting module includes a plurality of fine-grained counting modules, and the clock network module is specifically configured to output a plurality of second timestamp signals to each of the fine-grained counting modules according to the first timestamp signal;

sampling points corresponding to the fine-grained counting modules are the same;

and the duration calculation module is used for determining a timing result according to the coarse granularity count and the fine granularity counts determined by the fine granularity count modules by adopting an averaging method.

In another possible implementation manner of the first aspect, the fine-grained counting module includes a plurality of fine-grained counting modules, and the clock network module is specifically configured to output a plurality of second timestamp signals to each of the fine-grained counting modules according to the first timestamp signal;

the sampling points corresponding to the fine-grained counting modules are different;

and the time length calculation module is used for determining a timing result according to the coarse grain count and the fine grain counts determined by the fine grain counting modules.

In a second aspect, the present application provides an optical ranging sensor, including the time-to-digital conversion apparatus.

Compared with the prior art, the embodiment of the application has the advantages that: the time-to-digital conversion device outputs a plurality of second timestamp signals to the fine-grained counting module through the clock network module according to the input first timestamp signals, each second timestamp signal is a signal obtained after the first timestamp signal is subjected to the same time delay, each second timestamp signal is sampled at different moments through the fine-grained counting module, fine-grained counting is determined according to the sampling result of each second timestamp signal, coarse-grained counting of the second timestamp signals is determined through the coarse-grained counting module, and a timing value is determined according to the fine-grained counting and the coarse-grained counting through the time duration calculating module, so that the time-to-digital conversion device is high in timing precision, convenient to realize, flexible, extensible and low in cost.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a time-to-digital conversion apparatus according to an embodiment of the present application;

fig. 2 is a schematic structural diagram of a fine-grained counting module of a time-to-digital conversion apparatus according to an embodiment of the present application;

fig. 3 is a schematic circuit structure diagram of a time-to-digital conversion apparatus according to an embodiment of the present application;

fig. 4 is a schematic structural diagram of a clock network module of a time-to-digital conversion apparatus according to an embodiment of the present application;

fig. 5 is a schematic structural diagram of a multi-stage delay chain unit and a sampling unit of a time-to-digital conversion apparatus according to an embodiment of the present application;

fig. 6 is a sampling waveform diagram of a time-to-digital conversion apparatus provided in an embodiment of the present application;

fig. 7 is a schematic structural diagram of a plurality of fine-grained counting modules of a time-to-digital conversion apparatus according to an embodiment of the present application.

Wherein, in the figures, the respective reference numerals:

the system comprises a 1-clock network module, a 2-fine-grain counting module, a 21-multi-stage delay chain unit, a 22-sampling unit, a 23-fine-grain counting encoder unit, a 24-bit sequence rearrangement unit, a 3-coarse-grain counting module, a 4-duration calculation module and a 5-clock management module.

Detailed Description

In order to make the technical problems, technical solutions and advantageous effects to be solved by the present application clearer, the present application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.

It will be understood that when an element is referred to as being "secured to" or "disposed on" another element, it can be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or be indirectly connected to the other element.

It will be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like, refer to an orientation or positional relationship illustrated in the drawings for convenience in describing the present application and to simplify description, and do not indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be construed as limiting the present application.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.

In order to solve the problems of long development cycle and high product cost of the traditional timing device, one scheme which can be adopted is to utilize a Field Programmable Gate Array (FPGA) to realize high-precision time measurement, namely to finish the high-precision measurement of a time interval based on the internal resources of the FPGA; in specific implementation, a time interpolation mode can be adopted, an FPGA clock signal is used as a counter, and a coarse-grained count value is obtained by counting and measuring time intervals in coarse-grained units; meanwhile, the coarse-grained time unit is further subdivided by means of design resources inside the FPGA to obtain a fine-grained count value, and finally, the coarse-grained count value and the fine-grained count value are integrated to output a final timing result.

Specifically, the time interpolation method may include a tapped delay line method and a multi-phase clock method, where the tapped delay line method may use a carry chain inside the FPGA as a delay path, and determine the fine-grained time by analyzing the number of stages of signals propagating on the delay path in a coarse-grained time unit, and this method may achieve a higher resolution (e.g., tens of picoseconds), but due to uneven delay distribution of the delay path inside the FPGA, a measurement result of the fine-grained time has nonlinearity; meanwhile, the delay time of each stage on the delay path fluctuates due to factors such as manufacturing process, temperature and voltage (PVT), and needs to be calibrated periodically, so that the final scheme becomes complicated and affects flexibility.

The multi-phase clock method can generate a plurality of clocks with the same frequency and equal phase intervals through a clock management module in the FPGA, and samples events at different positions of a coarse-grained time unit by utilizing phase differences of different clocks so as to further divide time granularity.

Therefore, the application provides a time-to-digital conversion device, a plurality of second timestamp signals are output to a fine-grained counting module through a clock network module according to an input first timestamp signal, each second timestamp signal is a signal obtained after the first timestamp signal is subjected to the same time delay, each second timestamp signal is sampled at different moments through the fine-grained counting module, fine-grained counting is determined according to a sampling result of each second timestamp signal, coarse-grained counting of the second timestamp signal is determined through the coarse-grained counting module, and a timing value is determined according to the fine-grained counting and the coarse-grained counting through a time duration calculating module, so that the time-to-digital conversion device is high in timing precision, convenient to implement, flexible, extensible and low in cost.

Fig. 1 is a schematic structural diagram of a time-to-digital conversion apparatus according to a first embodiment of the present application, and only the relevant portions of the apparatus are shown for convenience of description. As shown in fig. 1, the time-to-digital conversion apparatus provided by the present application may include a clock network module 1, a fine-granularity counting module 2, a coarse-granularity counting module 3, and a duration calculating module 4.

The clock network module 1 is configured to output a plurality of second timestamp signals to the fine-grained counting module 2 according to an input first timestamp signal, where each second timestamp signal is a signal obtained after the first timestamp signal is subjected to the same time delay; the fine grain counting module 2 is configured to sample each of the second timestamp signals, and determine a fine grain count according to a sampling result of each of the second timestamp signals, where sampling points of each of the second timestamp signals are different; the coarse-granularity counting module 3 is used for determining the coarse-granularity count of the second time stamp signal; the duration calculation module 4 is configured to determine a timing value according to the fine-grained count and the coarse-grained count.

In the embodiment of the application, after a first timestamp signal to be measured enters the FPGA through the input pin, the clock network module 1 divides the first timestamp signal into a plurality of signals and performs the same delay to output a second timestamp signal, and the time when each second timestamp signal reaches the multi-stage delay chain inside the fine-grain counting module 2 is the same, so that the problem of skew transmission of the signals in different paths inside the FPGA can be solved, meanwhile, because the time when a plurality of second timestamp signals are input into the multi-stage delay chain units 21 inside the fine-grain counting module is the same, and based on the calibration function of the multi-stage delay chain units 21, the delay lengths of all levels of nodes on a link can be uniformly distributed and basically unchanged, so that a timing result has good linearity and consistency, and the influence of a process-voltage-temperature factor on the delay time is eliminated.

The clock network module is a dedicated wiring resource inside the FPGA, is generally used for transmitting clock signals, and may be any one of the following clock networks or a variant network of any one of the following clock networks: global clock networks, local clock networks, horizontal clock networks, and input/output (IN/OUT, IO) clock networks. The clock network module 1 is used for transmitting the first timestamp signal, so that the time when the first timestamp signal reaches the input end of the multistage delay chain unit 21 is basically consistent, and the skew problem caused by the uncontrollable characteristic of common wiring resources is avoided.

In this embodiment, the time-to-digital conversion apparatus may further include a clock management module 5, configured to provide a sampling clock for the fine-grained counting module 2, and provide a system clock or a sampling clock for the coarse-grained counting module 3; the sampling clock output by the clock management module 5 may be the same as the system clock or different (for example, the two are in a frequency multiplication relationship).

Fig. 2 is a schematic structural diagram of a fine-grain counting module of a time-to-digital conversion apparatus according to an embodiment of the present application, and as shown in fig. 2, the fine-grain counting module 2 may include a multi-stage delay chain unit 21, a sampling unit 22, and a fine-grain counting encoder unit 23.

The multistage delay chain unit 21 is configured to output each second timestamp signal after performing different delays, so as to obtain a plurality of third timestamp signals; the sampling unit 22 is configured to sample each third timestamp signal at the same time; the fine grain count encoder unit 23 is configured to determine a fine grain count from the sampling result of each third timestamp signal.

Specifically, a multi-stage delay chain resource (i.e., the multi-stage delay chain unit 21) is usually built in an IO port of the FPGA, in this embodiment, the multi-stage delay chain unit 21 may include a plurality of delay chains, each delay chain may correspond to a second timestamp signal one by one, and each second timestamp signal output by the clock network module 1 is sent into the corresponding delay chain.

For each delay chain, a fixed delay stage number may be set using parameters at the time of instantiation, or the delay stage number of the delay chain may be dynamically adjusted at run-time through a configuration interface. Based on the characteristic that the number of delay stages of the delay chain unit 21 is adjustable, in this embodiment, a plurality of delay chains may be set to have a structure in which the number of delay stages increases sequentially, so that after the plurality of second timestamp signals are respectively delayed by the delay chain unit 21, a plurality of third timestamp signals after different delays may be obtained at the output end of the delay chain unit 21.

The sampling unit 22 may include a plurality of sampling registers, the third timestamp signals with different delay amounts output from the delay chain unit 21 are respectively sent to input ends of the plurality of sampling registers in the sampling unit 22, and the sampling registers sample the third timestamp signals at the input ends under the control of the sampling clock output by the clock management module 5, register and output an instantaneous level state of the signals. Each sampling register can adopt same sampling clock to sample the third time stamp signal of input, because the third time stamp signal of each sampling register input has the delay volume that progressively increases in proper order, consequently, each sampling register uses same sampling clock to sample the third time stamp signal, is in fact equivalent to using a plurality of sampling clocks to sample at the different moments of second time stamp signal to inside sampling clock period, the granularity of timing has further been subdivided.

In this embodiment, the sampling register may be located close to the corresponding delay chain, so that the skew problem caused by inconsistent delay of the routing can be avoided. Specific implementation forms of the sampling register include, but are not limited to, a deserializer (i.e., a serial-to-parallel converter (SERDES)), a double-rate register and a common register resource in the IO logic unit; where the deserializer may operate in a variety of sampling Rate modes including, but not limited to, Single Data Rate (SDR), Double Data Rate (DDR), and Oversampling (OVERSAMPLE).

The sampling result of the time stamp signal obtained by integrating the outputs of the sampling registers may be a bit vector shaped like a thermometer code, and the binary form of the sampling result may be composed of consecutive 0 s and/or consecutive 1 s, where the transition positions of 0 to 1 and/or 1 to 0 correspond to the relative times of the rising edge and/or the falling edge of the second time stamp signal within the system clock cycle, and each time granularity of 0 and 1 corresponds to the delay amount difference between the two stages of delay chains, i.e., a fine-grained time unit. The fine grain count encoder unit 23 takes the bit vector as input and outputs a corresponding fine grain count, which value represents the subdivided position of the rising and/or falling edge of the second timestamp signal within the corresponding system clock cycle.

The coarse-granularity counting module 3 may include a coarse-granularity counter, where the coarse-granularity counter counts at the frequency of the system clock or the sampling clock, and when the fine-granularity counting encoder outputs a valid value (e.g., a value other than 0) in a certain clock cycle, it indicates that a rising edge and/or a falling edge of the second timestamp signal exists in the clock cycle, and at this time, the coarse-granularity counter may output a current count as a coarse-granularity count measured by time, where a coarse-granularity time unit of the coarse-granularity count is the clock cycle (i.e., the system clock or the sampling clock) used by the coarse-granularity counter.

The time length calculating module 4 can obtain a final timing result according to the coarse grain count and the fine grain count and by combining the coarse grain time unit and the fine grain time unit. For example, the coarse-grained count may be multiplied by a coarse-grained time unit to obtain a coarse-measurement time interval, the fine-grained count may be multiplied by a fine-grained time unit to obtain a fine-measurement time interval, and then the coarse-measurement time interval may be added to the fine-measurement time interval to obtain a final timing result.

When the sampling clock of the clock management module 5 is different from the system clock, the fine grain counting module 2 may further include a bit sequence reordering unit 24, configured to reorder bit vectors obtained by sampling the input signal by each sampling register, and send the reordered bit vectors to the fine grain counting encoder unit 23.

Specifically, the sampling state of the third timestamp signal obtained by each sampling register is sent to the bit sequence rearrangement module 24, and the bit sequence rearrangement module 24 may readjust and integrate the bit sequence in the system clock domain according to the interleaving rule between the bit vectors output by each sampling register under the driving of the high-frequency sampling clock, so as to obtain a bit vector which uses the difference between the delay amounts of the delay chains as granularity and reflects the relative time position of the rising edge and/or the falling edge of the second timestamp signal within the system clock cycle.

Taking Xilinx 7 series FPGA as an example, a specific circuit structure of the time-to-digital conversion device is exemplarily shown below.

Fig. 3 is a schematic circuit structure diagram of the time-to-digital conversion apparatus provided in this embodiment, and fig. 4 is a schematic structure diagram of a clock network module of the time-to-digital conversion apparatus provided in this embodiment, as shown in fig. 3 and fig. 4, a first timestamp signal to be detected enters an FPGA through a global input buffer device (IBUFG) at an IO pin, first reaches a global clock Buffer (BUFG) along a general wiring resource (general routing), and then is sent into a global clock network through the BUFG, so as to obtain a plurality of second timestamp signals that have undergone the same time delay.

Fig. 5 is a schematic structural diagram of a multi-stage delay chain unit and a sampling unit of a time-to-digital conversion apparatus according to an embodiment of the present application, and as shown in fig. 5, in an Xilinx 7-series FPGA, a delay chain unit 21 located in an IO block may include a plurality of ideelaye 2, and ideelaye 2 is a device for delaying an input signal, in which a 32-stage delay chain is built. When the idelay 2 and the delay calibration device (IDELAYCTRL) cooperate, IDELAYCTRL performs real-time feedback calibration on the delay chain inside each idelay 2 according to the clock period of the reference clock, so as to ensure that the delay amount of each stage of node inside the delay chain is substantially equal, and the total delay duration of the whole delay chain is kept unchanged. Under the action of a calibration mechanism of the delay calibration device (IDELAYCTRL), the step size (i.e. granularity of further time division within a sampling period) of the IDELAYE2 delay chain is fixed to 1/64 of the clock period of the reference clock, so that the delay calibration device is not influenced by the process-voltage-temperature and has better consistency.

Taking the reference clock CLK _ REF output by the clock management module 5(MMCM) as an example with a frequency of 200MHz, the step size of idelay 2 is 78.125 ps. The delay stage number of each ideelaye 2 may be statically set or dynamically adjusted, and in the case of static setting, when the ideelaye 2 is instantiated by a hardware description language, the delay stage number may be set by a corresponding parameter value. Illustratively, as shown in fig. 5, a total of 16 ideelaye 2 devices are used: IDELAYE2# 1-IDELAYE 2#16, the delay stages are statically set to 1, 2, …, 16 in sequence.

The first time stamp signal reaches the input end of 16 IDELAYE2 along the global clock network to obtain a second time stamp signal, and after the time delay of an IDELAYE2 internal delay chain, 16 third time stamp signals with different delay degrees are obtained at the output end, wherein the delay difference of two adjacent third time stamp signals is the step size of the delay chain, namely 78.125 ps. These signals are then fed to the sampling units 22 (isersense 2, specifically isersense 2#1 to isersense 2#16) adjacent to the corresponding ideelaye 2, the sampling units 22 (isersense 2) being serial-to-parallel converters built into the Xilinx 7 series FPGA IO blocks for converting the high speed serial signals in the high frequency clock domain into parallel data in the low frequency clock domain. The sampling unit 22 (isersense 2) supports multiple serial-to-parallel conversion modes, for example, in this embodiment, a double edge sampling (DATA _ RATE) and a serial-to-parallel conversion ratio of 2:1 (DATA _ WIDTH ═ 4) are adopted, and in this setting, the sampling unit 22 (isersense 2) performs 1 sampling on each pair of input signals at the rising edge and the falling edge of each sampling clock cycle, and outputs a bit vector with a length of 4 every 2 sampling clock cycles.

To match this serial-to-parallel conversion mode, the clock management module 5(MMCM) may output two clocks, respectively a sampling clock CLK _ SAMPLE and a system clock CLK _ SYS, wherein the sampling clock CLK _ SAMPLE is connected to the CLK pin of each sampling unit 22 (isersense 2) for double-edge sampling of its input, for example at a frequency of 400 MHz; the system clock CLK _ SYS, which is at a frequency of 200MHz for example, is connected to the CLKDIV pin of each sampling unit 22 (isersense 2) and is configured to output a bit vector with a total bit width of 4 once from the O1/O2/O3/O4 port every two CLK _ SAMPLE cycles.

Since the 16 inputs of the isetree 2 are the third timestamp signals with sequentially increasing delay lengths, and the increasing step is the step of the ideelaye 2 delay chain (i.e. 78.125ps), while the sampling clock frequency of the isetree 2 is 400MHz, and the corresponding sampling period is 2500ps, if the sampling clock is used uniformly to sample the 16 third timestamp signals with sequentially increasing delay, it is practically equivalent to sampling the second timestamp signals with 16 sampling clocks with intervals of 78.125 ps.

Fig. 6 is a waveform diagram of sampling of the time-to-digital conversion apparatus according to the embodiment of the present application, as shown in fig. 6, the sampling clock (sampling clock #16) of the 16 th isersense 2 samples the third timestamp signal delayed most (delayed by 16 stages), so that the sampling position is the first of all isersenses 2; and the sampling clock of the 1 st isersense 2 (sampling clock #1) samples the least delayed (delay 1 stage) third timestamp signal, so the sampling position is at the end of all isersenses 2.

The sampling position interval of each sampling clock is 78.125ps (i.e. the step size of the delay chain), and the half period of the 400MHz sampling clock, namely 1250ps, is exactly divided into 16 parts, which is equivalent to realizing further time granularity subdivision on the basis of the half period of the sampling clock.

The sampling positions of the bit vectors (bit vector #1 to bit vector #16) output by the 16 isersense 2 in the system clock domain are in a time-interleaved relationship. For example, the 16 th isersense 2 outputs a bit vector of length 4 with corresponding sampled edges being edge 1, edge 17, … …, while the 1 st isersense 2 outputs a bit vector of length 4 with corresponding sampled edges being edge 16, edge 32, … …. Therefore, for 16 groups of bit vectors with the length of 4 obtained in each system clock cycle, the sequence of each bit needs to be readjusted, and finally the bit vectors are integrated into a bit vector with the length of 64, wherein the sequence of the bit sequences corresponds to the time sequence of the sampling edges.

After the bit sequence rearrangement, a bit vector with a length of 64, for example, 000001111111100000 … … 000, is obtained, wherein the transition position of 0 to 1 and/or 1 to 0 corresponds to the subdivided position of the rising edge and/or the falling edge of the second timestamp signal in the system clock cycle, and the subdivided granularity is 78.125 ps. Therefore, the transition positions from 0 to 1 and/or from 1 to 0 are encoded into binary values by a priority encoder (i.e., a fine-grained count encoder), and then a fine-grained count value of the corresponding signal edge moment can be obtained.

Meanwhile, the coarse granularity counter counts the system clock period; when the fine-granularity count value corresponding to a certain system clock period is not 0, the rising edge and/or the falling edge of the timestamp signal are/is captured in the system clock period, and the value of the coarse-granularity counter is recorded as the coarse-granularity count. This uses the coarse-grained count times the coarse-grained time unit (5000ps) plus the fine-grained count times the fine-grained time unit (78.125ps) to obtain the final timing result.

The fine-grained counting module 2 is exemplarily illustrated above by taking a single fine-grained counting module 2 as an example. Fig. 7 is a schematic structural diagram of a plurality of fine-grained counting modules of a time-to-digital conversion apparatus provided in an embodiment of the present application, as shown in fig. 7, in this embodiment, a plurality of fine-grained counting modules 2 may also be included, and the scheme may include, but is not limited to, the following several implementation manners:

the first method comprises the following steps: the fine-grained counting modules 2 simultaneously measure the time of a plurality of concurrent first timestamp signals input from the clock network modules 1, that is, each fine-grained counting module 2 can correspond to different first timestamp signals, and for each fine-grained counting module 2, the duration calculating module 4 can determine a timing result corresponding to the time-to-digital conversion device according to the coarse-grained count and the fine-grained count determined by the fine-grained counting module 2.

And the second method comprises the following steps: the clock network module 1 is specifically configured to output a plurality of second timestamp signals to each fine-grained counting module 2 according to the first timestamp signal.

The sampling points corresponding to the fine-grained counting modules 2 are the same.

The duration calculation module 4 is configured to determine a timing result according to the coarse-granularity count and the fine-granularity counts determined by the fine-granularity count modules 2 by using an averaging method.

The time measurement method comprises the steps that a plurality of fine-grained counting modules 2 are adopted to simultaneously carry out time measurement on a single first timestamp signal input on the same clock network module 1, sampling points corresponding to the fine-grained counting modules 2 are the same, average fine-grained counting is output after measurement results of the fine-grained counting modules 2 are averaged, and a time length calculation module 4 can determine a timing result corresponding to the time-to-digital conversion device according to the coarse-grained counting and the average fine-grained counting determined by the fine-grained counting modules 2, so that jitter of the measurement values is reduced.

And the third is that: the clock network module 1 is specifically configured to output a plurality of second timestamp signals to each fine-grained counting module 2 according to the first timestamp signals;

the sampling points corresponding to the fine-grained counting modules 2 are different;

the duration calculation module 4 is configured to determine a timing result according to the coarse-granularity count and the fine-granularity counts determined by the fine-granularity count modules 2.

The time measurement is performed on a single first timestamp signal input on the same clock network module 1 by adopting a plurality of fine-grained counting modules 2, sampling points corresponding to the fine-grained counting modules 2 are different, sampling clocks adopted by the fine-grained counting modules 2 are the same in frequency and different in phase, and the phases have slight offset, so that fine-grained time units are subdivided again, as shown in fig. 7, a duration calculation module 4 can determine a timing result corresponding to the time-to-digital conversion device according to the coarse-grained count and the subdivided fine-grained count determined by each fine-grained counting module 2, and further improve the time resolution.

The application provides an optical ranging sensor, including time digital conversion device.

In the embodiment of the application, the first timestamp signal is distributed to the multistage delay chains through the clock network module, and the characteristic that the time delay of each branch of the clock network module is equal is utilized to ensure that the input end signal (namely, the second timestamp signal) of each delay chain corresponds to the first timestamp signal at the same moment, so that the problem of skew of signal transmission in different paths in the FPGA is solved; furthermore, the multi-stage delay chain of a common FPGA model supports a calibration function, a compensation circuit is arranged in the multi-stage delay chain, the influence of the process-voltage-temperature (PVT) factors on the delay time can be eliminated, the delay lengths of nodes at all stages on the chain are ensured to be equally distributed and basically unchanged, and the timing result has good linearity and consistency; the timing mode based on the multi-sampling has smaller dead time (not exceeding coarse-grained time units at most), and can quickly and continuously time the timestamp signals with high frequency; by using a plurality of fine-grained counting modules simultaneously, the performance parameters of the whole timing device can be further improved, for example, the jitter of the timing value is reduced by averaging the fine-grained counting modules, or the time resolution of the timing result is further improved by using the phase shift of the sampling clock.

It should be understood that, the sequence numbers of the steps in the foregoing embodiments do not imply an execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.

It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-mentioned division of the functional units and modules is illustrated, and in practical applications, the above-mentioned function distribution may be performed by different functional units and modules according to needs, that is, the internal structure of the apparatus is divided into different functional units or modules to perform all or part of the above-mentioned functions. Each functional unit and module in the embodiments may be integrated in one processing unit, or each unit may exist alone physically, or two or more units are integrated in one unit, and the integrated unit may be implemented in a form of hardware, or in a form of software functional unit. In addition, specific names of the functional units and modules are only for convenience of distinguishing from each other, and are not used for limiting the protection scope of the present application. The specific working processes of the units and modules in the primary quasi-resonant control system can refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.

In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and reference may be made to the related descriptions of other embodiments for parts that are not described or illustrated in a certain embodiment.

Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

In the embodiments provided in the present application, it should be understood that the disclosed time-to-digital conversion apparatus and method may be implemented in other ways. For example, the above-described embodiments of the time-to-digital conversion apparatus are merely illustrative, and for example, the division of the modules or units is only a logical division, and there may be other divisions when the actual implementation is performed, for example, a plurality of units or components may be combined or integrated into another primary quasi-resonant control system, or some features may be omitted or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.

The above-mentioned embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.

Claims (10)

1. A time-to-digital conversion device comprises a clock network module (1), a fine-granularity counting module (2), a coarse-granularity counting module (3) and a duration calculating module (4);

the clock network module (1) is configured to output a plurality of second timestamp signals to the fine-grained counting module (2) according to an input first timestamp signal, where each second timestamp signal is a signal obtained after the first timestamp signal is subjected to the same time delay;

the fine-grained counting module (2) is used for sampling each second timestamp signal and determining fine-grained count according to the sampling result of each second timestamp signal, wherein the sampling points of the second timestamp signals are different;

the coarse granularity count module (3) is configured to determine a coarse granularity count of the second timestamp signal;

the duration calculation module (4) is configured to determine a timing value based on the fine granularity count and the coarse granularity count.

2. The time-to-digital conversion apparatus according to claim 1, wherein the fine-grain count module (2) includes a multi-stage delay chain unit (21), a sampling unit (22), and a fine-grain count encoder unit (23);

the multistage delay chain unit (21) is used for outputting the second timestamp signals after different delays are performed on the second timestamp signals to obtain a plurality of third timestamp signals;

the sampling unit (22) is used for sampling the third timestamp signals at the same time respectively;

the fine grain count encoder unit (23) is configured to determine a fine grain count from a sampling result of each of the third timestamp signals.

3. The time-to-digital conversion apparatus according to claim 2, wherein the multistage delay chain unit (21) includes a plurality of delay chains, and delay amounts of the delay chains are different.

4. The time-to-digital conversion apparatus according to claim 2, wherein the fine-granularity count module (2) further comprises a bit-order reordering unit (24), and the bit-order reordering unit (24) is configured to reorder the sampling result of each of the third timestamp signals and output the result to the fine-granularity count encoder unit (23).

5. The time-to-digital conversion arrangement according to claim 1, characterized in that the time-to-digital conversion arrangement further comprises a clock management module (5), the clock management module (5) being configured to provide a sampling clock for the fine-grained counting module (2) and a system clock or a sampling clock for the coarse-grained counting module (3).

6. Time-to-digital conversion arrangement according to any of claims 1-5, characterized in that said clock network module (1) is any or a variant of any of the following clock networks: global clock network, local clock network, horizontal clock network and IO clock network.

7. A time-to-digital conversion arrangement according to any of claims 2-4, characterized in that the sampling unit (22) is a serial-to-parallel converter, a double-rate register or a normal register.

8. The time-to-digital conversion arrangement according to any of claims 1-5, characterized in that the fine-grain counting module (2) comprises a plurality of modules, the clock network module (1) being configured to output a plurality of second time stamp signals to each of the fine-grain counting modules (2) in dependence of the first time stamp signal, respectively;

the sampling points corresponding to the fine-grained counting modules (2) are the same;

the duration calculation module (4) is used for determining a timing result according to the coarse granularity count and the fine granularity counts determined by the fine granularity count modules (2) by adopting an averaging method.

9. The time-to-digital conversion arrangement according to any of claims 1-5, characterized in that the fine-grain counting module (2) comprises a plurality of modules, the clock network module (1) being configured to output a plurality of second time stamp signals to each of the fine-grain counting modules (2) in dependence of the first time stamp signal, respectively;

the sampling points corresponding to the fine-grained counting modules (2) are different;

the duration calculation module (4) is used for determining a timing result according to the coarse granularity count and the fine granularity counts determined by the fine granularity count modules (2).

10. An optical ranging sensor comprising the time-to-digital conversion device of any one of claims 1 to 9.

Images