CN114995092B - Time-to-digital conversion circuit - Google Patents
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Abstract
The invention discloses a time-to-digital conversion circuit, which comprises: a counter unit for pulse counting the timing signals and outputting residual information between the timing signals and a first counter value; the first time measurement unit comprises a first delay phase-locked loop circuit, a synchronous circuit and an asynchronous circuit, wherein the synchronous circuit is used for carrying out signal retiming on residual information based on a phase signal output by the first delay phase-locked loop circuit and outputting a synchronous signal and a second counter value; the asynchronous circuit is used for directly outputting residual information through a delay chain to obtain an asynchronous signal; a second time measurement unit for interpolating timing of the synchronous signal and the asynchronous signal and outputting a third counter value between the synchronous signal and the asynchronous signal; and a decoder for determining a time difference between the timing signals based on the first counter value, the second counter value, and the third counter value. The circuit of the invention can obtain time measurement data with higher resolution.
Description
Technical Field
The invention relates to the technical field of digital clock circuits, in particular to a time-to-digital conversion circuit.
Background
Along with the development and popularization of intelligent electric automobiles, the laser radar applied to the automobile auxiliary driving field becomes an indispensable vehicle-mounted sensing device, and the vehicle-mounted laser radar has the characteristics of high frame frequency (centimeter-level resolution), multi-line parallel operation, scanning point cloud imaging and the like, so that the multi-channel and high-precision time digital conversion circuit becomes one of key (important) modules of the vehicle-mounted laser radar.
The existing time-digital conversion integrated circuit is generally applied to the field of low-frame-rate and nanosecond-level precision measurement of ultrasonic water meters and the like. The high-resolution time-to-digital conversion chip is usually realized by an ASIC chip, but has low design flexibility and long development period, and has low priority in the application scene of the vehicle-mounted laser radar. The existing time-digital conversion circuit in the vehicle-mounted laser radar application is generally realized by adopting an FPGA device, an adder delay chain in the FPGA is used as a high-frequency clock interpolation source, so that high-precision time measurement is realized, the time delay of a minimum gate circuit in the adder delay chain is limited, the general ranging precision is not more than 50ps, the method needs a complex post-calibration technology to calibrate errors such as noise, temperature drift and offset of the FPGA internal circuit, and the parallel processing of time-digital conversion when channels are more cannot be realized by the FPGA internal resource.
Disclosure of Invention
Therefore, the invention aims to solve the technical problems that the ranging precision of the time-to-digital conversion circuit still cannot meet the use requirement and complex post calibration is required in the prior art.
To this end, the present invention provides a time-to-digital conversion circuit comprising:
a counter unit for pulse counting the timing signals and outputting residual information between the timing signals and a first counter value;
the first time measurement unit comprises a first delay phase-locked loop circuit, a synchronous circuit and an asynchronous circuit, wherein the synchronous circuit and the asynchronous circuit are connected with the first delay phase-locked loop circuit, and the synchronous circuit and the asynchronous circuit are connected with the counter unit; the synchronous circuit is used for carrying out signal retiming on residual information based on the phase signal output by the first delay phase-locked loop circuit and outputting a synchronous signal and a second counter value; the asynchronous circuit is used for directly outputting residual information through a delay chain to obtain an asynchronous signal;
the second time measuring unit is connected with the synchronous circuit and the asynchronous circuit, and is used for carrying out interpolation timing on the synchronous signal and the asynchronous signal and outputting a third counter value between the synchronous signal and the asynchronous signal;
and the decoder is connected with the counter unit, the synchronous circuit and the second time measuring unit and is used for based on the time difference among the first counter value, the second counter value and the third counter value.
Further, the second time measuring unit comprises a second delay phase-locked loop circuit, and the delay chain in the second delay phase-locked loop circuit is a delay chain with a parallel proportional load capacitor with double-end output.
Further, the feedback clock signal of the second delay locked loop circuit is an i-th phase signal in the phase signals output by the first delay locked loop circuit, and the reference clock signal is an i+2-th phase signal in the phase signals output by the first delay locked loop circuit.
Further, if the phase difference outputted by the first delay phase-locked loop circuit is τ 1 N of (2) 1 The phase difference of the phase-separated signal output by the second delay phase-locked loop circuit is tau 2 N of (2) 2 The phase-separated signal is passed through the delay chain of second delay phase-locked loop circuit to obtain phase difference tau 2 The asynchronous signal obtains a phase difference of n after passing through a delay chain of a second delay phase-locked loop circuit 2 τ 2 And N 2 Is n 2 Is a multiple of (2).
Further, the synchronization circuit includes a first flip-flop group and a second flip-flop group, and the first flip-flop group and the second flip-flop group each include N 1 A plurality of triggers; n of the output of the first delay phase-locked loop circuit 1 Phase separated signalRespectively N in the first trigger group 1 The input signals of the triggers are the clock signals of the triggers in the first trigger group; n in the first trigger group 1 The complementary outputs of the flip-flops are respectively connected to N in the second flip-flop group 1 Data input terminals of the flip-flops, and n of input signals of the flip-flops in the first flip-flop group 1 The phase-shifted signals are clock signals of the flip-flops in the corresponding second flip-flop group.
Further, the asynchronous circuit includes a phase difference n 1 τ 1 Is a delay chain of (a).
Further, the second time measurement unit further comprises a latch circuit, the latch circuit is a lattice structure formed by a plurality of triggers, the synchronous phase-separated signal is an input signal of a trigger in the lattice structure, the asynchronous phase-separated signal is a clock signal of the trigger in the lattice structure, and the phase difference between output signals of a transverse trigger group in the lattice structure is τ 2 The phase difference between the output signals of the vertical trigger groups in the lattice structure is n 2 τ 2 。
Further, the delay chain in the first delay locked loop circuit is composed of a plurality of differential delay tunable multiplexers having two input channels.
The technical scheme provided by the invention has the following advantages:
1. according to the time-to-digital conversion circuit, the counter unit, the first time measuring unit and the second time measuring unit which are sequentially connected are arranged, the granularity is from large to small, time measurement data with higher resolution can be obtained, the problem that a large number of delay units and registers are used to cause high integral nonlinearity in the prior art can be solved, and the problem that the precision is limited by process characteristics (PVT) can be solved; meanwhile, by setting that the first time measuring unit comprises a first delay phase-locked loop circuit, a synchronous circuit and an asynchronous circuit, the total delay caused in the synchronous signal propagation process is compensated through the delay in the asynchronous signal propagation path, the time measuring signal can be prevented from shifting between the first time measuring unit and the second time measuring unit, and the time measuring precision of the time digital conversion circuit is ensured.
2. According to the time-to-digital conversion circuit provided by the invention, two signals (i phase and i+2 phase) in the phase signals output by the first delay phase-locked loop circuit are respectively used as the reference clock and the feedback clock of the second delay phase-locked loop, so that time-measurement data signals with small granularity and high resolution can be obtained, and high-frequency external reference clock input is not needed, so that the implementation difficulty of the time-to-digital conversion circuit is reduced.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram of a time-to-digital conversion circuit according to an embodiment of the present invention;
fig. 2 is a circuit structure diagram of a first delay phase-locked loop unit according to an embodiment of the present invention;
FIG. 3 is a circuit block diagram and a timing diagram of a synchronous circuit and an asynchronous circuit according to an embodiment of the present invention;
fig. 4 is a circuit structure diagram of a second delay locked loop unit according to an embodiment of the present invention;
fig. 5 is a circuit configuration diagram of a latch unit according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made apparent and fully in view of the accompanying drawings, in which some, but not all embodiments of the invention are shown. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In the description of the present invention, it should be noted that the azimuth or positional relationship indicated by the terms "upper", "lower", etc. are based on the azimuth or positional relationship shown in the drawings, and are merely for convenience of describing the present invention and simplifying the description, and are not indicative or implying that the apparatus or element in question must have a specific azimuth, be constructed and operated in a specific azimuth, and thus should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
The present embodiment provides a time-to-digital conversion circuit, as shown in fig. 1, including: a counter unit, a first time measurement unit and a second time measurement unit.
The counter unit is used for counting pulses of the timing signals and outputting residual information between the timing signals (Start/Stop) and a first counter value.
The first time measurement unit comprises a first delay phase-locked loop circuit, a synchronous circuit and an asynchronous circuit, wherein the synchronous circuit and the asynchronous circuit are connected with the first delay phase-locked loop circuit, and the synchronous circuit and the asynchronous circuit are connected with the counter unit; the synchronous circuit is used for carrying out signal retiming on residual information based on the phase signal output by the first delay phase-locked loop circuit and outputting a synchronous signal and a second counter value; the asynchronous circuit is used for directly outputting residual information through a delay chain to obtain an asynchronous signal.
Specifically, the first delay-locked loop circuit is configured to output an input reference clock signal (signal Xin in fig. 2 below) via a delay chain to obtain a phase signal (thus, the reference clock signal may be referred to as a phase advance signal, and the feedback clock signal may be referred to as a phase retard signal), and the phase retard signal is obtained via a delay chain of a j-stage delay unit to obtain N 1 Phase lag sub-signal (N) 1 =2j), the phase detector compares the phase lead signal with the nth signal 1 The phase difference between the phase lag sub-signals is processed in the forward channel by a charge pump and a loop filter to generate a voltage signal, and the N-th signal is controlled 1 The phase lag sub-signal is locked to the reference clock frequency. At this time, the 1 st phase lag sub-signal and the N th phase lag sub-signal 1 Phase difference between phase lag sub-signalsJust equal to one input reference clock signal (Xin) period.
Specifically, the circuit structure of the first delay locked loop circuit is shown in fig. 2, where the delay chain unit is composed of a differential delay tunable multiplexer unit (hereinafter referred to as delay unit) having two input channels (the two input channels are only needed in the first delay unit, but all delays are the same in order to maintain a uniform size of time samples), and the end differential signals are cross-coupled back to the first channel of the first delay unit (in order to achieve pulse propagation). The working principle of the delay chain is as follows: the input reference clock signal (Xin) is converted into a differential signal and then transferred to the delay circuit structure. After this, the input channel of the first delay unit is changed and the input reference clock signal starts to circulate in a closed loop, after a certain number of cycles, the first delay unit lets the next jitter free reference edge enter the cycle and outputs the result of the delay chain. Specifically, θ in the figure 0 ～θ N1 For a phase difference of τ 1 And the phase signal outputted by the first delay phase-locked loop circuit of (2) is represented by θ N1 As a feedback clock signal, the phase difference signal is compared with an input reference clock signal to generate a voltage Vctrl1 by controlling the voltage structure process, and the voltage Vctrl1 adjusts the delay time of the differential delay unit until the phase signal theta 0 ～θ N1 Phase difference tau between adjacent phase lag sub-signals 1 Equal to τ ref/ (N+1) (where τ ref For the resolution of the counter unit), the charge pump charges and discharges in balance, the control voltage Vctrl1 locks, and a time sample θ with larger granularity and lower precision (relative to the signal in the second delay-locked loop circuit described below) is obtained 0 ～θ N1 With resolution equal to the phase difference tau 1 。
In addition, recycling Counter (recovery counter) is connected to an external register, so as to control the number of cycles through the external register pair Recycling Counter when the input reference clock signal Xin is not a typical value when designing the circuit and the internal circuit cannot be modified.
Specifically, the synchronization circuit is used for synchronizing residual information between timing signals, and N is obtained 1 Repositioning the phase lag sub-signals results in a higher resolution synchronization signal. Specifically, the synchronization circuit is configured to use the timing signal latched by the counter unit as the clock signal of the flip-flop, and to first count N 1 The phase lag sub-signal is turned to a state and the signal at the reverse output end is used as the input signal of the D trigger, N 1 The phase lag sub-signal is used as a clock reference signal to perform signal retiming, and N is calculated 1 Phase retimed signal via N 1 And the input OR gate obtains a synchronous output signal, and takes the retiming signal as an output end result of a trigger used by the clock signal and outputs the result as a source code of the first time measuring unit (primary coarse interpolation). The asynchronous circuit is used for directly outputting residual information between timing signals through a delay chain (the delay chain can be a delay chain arranged independently or can be a delay chain in a first delay phase-locked loop circuit), and N is also used for the asynchronous circuit in order to avoid the influence of the delay of the signals through the circuit 1 Input OR gate and N therein 1 -1 item 0, the delay difference between the asynchronous signal thus obtained and the synchronous signal is well matched.
Specifically, the circuit structure diagram and the timing diagram of the synchronous circuit and the asynchronous circuit are shown in fig. 3, wherein the first row and the second row of triggers (the first trigger set and the second trigger set) are synchronous circuits, and the first trigger set and the second trigger set comprise N 1 A plurality of flip-flops, N being the output of the first delay-locked loop circuit 1 Phase separated signal (θ) 0 ～θ N1 In the figure, N is 1 For example, shown as=15) are N in the first flip-flop group 1 The input signals of the triggers and the timing signals (Start/Stop) are clock signals of the triggers in the first trigger group; n in the first trigger group 1 The complementary outputs of the flip-flops are respectively connected to N in the second flip-flop group 1 Data input terminals of the flip-flops, and n of input signals of the flip-flops in the first flip-flop group 1 (in the figure, n is 1 For example, 8, i.e. the settling time of the synchronization circuit is 8τ 1 ) The phase-shifted signals are the clock signals of the flip-flops in the corresponding second flip-flop group, and the or gate with 16 input lines in fig. 3 finds a stable flip-flop after the synchronization delay and generates the synchronization signal (sync). As shown in the timing chart of FIG. 3, however, in order to cause the total delay Deltat caused by synchronization S By delaying Δt A Compensation in an asynchronous timing signal path and prevents the measurement signal (synchronous and asynchronous) from shifting between the first time measurement unit and the second time measurement unit (since the interpolation range of the second time measurement unit is the resolution (τ) of the first time measurement unit 1 ) When the mismatch of the measurement signals is greater than τ 1 The second time measurement unit is completely useless, so that the measurement signal offset mismatch needs to be prevented), and the asynchronous circuit comprises a phase difference n 1 τ 1 (at 8τ in FIG. 3) 1 Shown for example) and also generates an asynchronous signal (async) through the or gate.
The second time measuring unit is connected with the synchronous circuit and the asynchronous circuit, and is used for carrying out interpolation timing on the synchronous signal and the asynchronous signal and outputting a third counter value between the synchronous signal and the asynchronous signal.
Specifically, the second time measurement unit includes a second delay locked loop circuit and a latch circuit. Specifically, the delay chain in the second delay phase-locked loop circuit is a delay chain with parallel proportional load capacitance with double-end output, and the principle is as follows: the charge pump and loop filter process the resulting voltage signal, the control circuit signal generates a basic delay, and the load capacitors of different proportions (assuming the number of capacitors is n) generate delay time increments having the same scaling factor, so that the total delay of the signal in the delay structure unit is the basic delay tau in one delay unit e And a delay τ of a single unit capacitance c Multiplying the capacitance number n. Specifically, N in the first-level coarse interpolation circuit is taken 1 Two signals in the phase lag sub-signals are used as a reference clock and a feedback clock in a second delay phase-locked loop circuit, wherein the i-th phase (1 is less than or equal to i is less than or equal to N 1 -2) using the i+2 phase as a feedback clock signal via a large-scale load capacitance delay chainThe phase difference of the load capacitor delay chains with different proportions is adjusted according to the continuously-changing control voltage generated by the phase difference signal by using the load capacitor delay chains with small proportions as a reference clock signal until the control voltage is locked. Specifically, the latch circuit is configured to process the synchronous signal and the asynchronous signal output by the first time measurement unit in the following processing manner: delaying the asynchronous signal by a second delay phase-locked loop circuit to obtain a phase difference n 2 τ 2 (if the phase difference of the output of the second delay phase-locked loop circuit is tau 2 N of (2) 2 Phase separated signal, N 2 Is n 2 A multiple of (a) phase signal (a refers to the number of phases); delaying the synchronous signal by a second delay phase-locked loop circuit to obtain a phase difference tau 2 The phase difference value is adjusted by the control voltage until the control voltage is locked. The B-phase signal output by the synchronous signal is used as the clock signal of the latch circuit, the a-phase signal output by the asynchronous signal is used as the input end signal of the latch circuit, so that interpolation latching can be carried out on the a-B signals to obtain the source code of the second time measuring unit (secondary fine interpolation).
Specifically, the circuit structure of the second delay locked loop circuit is shown in fig. 4, and as described above, the circuit does not need an external reference clock input, but takes the multiphase sample signal output by the first delay locked loop unit as a signal input, and first goes through two parallel load capacitor delay chains with different ratios to delay θ i Using the large-proportion load capacitor delay chain as a feedback clock signal to make theta i+2 The phase detector converts the phase comparison result into control voltage Vctrl2 by using the small-proportion load capacitance delay chain as a reference clock signal, and adjusts the phase difference of the load capacitance delay chains with different proportions until the control voltage is locked. Before locking, the control voltage continuously acts on the delay chain of the parallel load capacitor, and simultaneously adjusts the phase difference value between the synchronous signal output by the first time measuring unit and the split-phase signal generated by the asynchronous signal through the delay unit, and finally realizes that the phase difference value of the adjacent synchronous split-phase signal is tau 2 Adjacent asynchronous split-phase signal phase difference value n 2 τ 2 . That is, when the control voltages in the two-stage interpolation of the time-to-digital conversion circuit in the present embodiment are locked, the resolution of the one-stage coarse interpolation is τ 1 The resolution of the second-order fine interpolation is τ 2 Implementing the resolution level, i.e. τ, for which the time-to-digital conversion circuit is designed 2 。
Specifically, the latch circuit has a structure shown in fig. 5, and is a lattice structure formed by a plurality of flip-flops, so as to latch and output the synchronous split-phase signal and the asynchronous split-phase signal output by the second delay phase-locked loop unit, thereby obtaining the second-level fine interpolation source code with small granularity and high resolution. Specifically, as shown in fig. 5, after the second delay locked loop unit is locked, the synchronization signals are delayed (based on the parallel proportional load capacitor structure) by the delay chains S0 to S7 to obtain a phase difference τ 2 And uses the synchronous split-phase signal as the input signal of the trigger; asynchronous signals are subjected to delay chains (realized based on parallel proportional load capacitor structures) A0-A7 to obtain the phase difference 8 tau 2 And uses the asynchronous split-phase signal as the clock signal of the flip-flop so that the phase difference between the output signals of the lateral flip-flops is tau 2 The phase difference between the output signals of the longitudinal triggers is 8τ 2 And outputs these output signals as source codes for the second-level fine interpolation.
The decoder is connected with the counter unit, the synchronous circuit and the second time measuring unit and is used for based on the time difference among the first counter value, the second counter value and the third counter value. Specifically, the decoder performs weighted addition on the first counter value, the second counter value and the third counter value to obtain complete time measurement data, namely:
T m ＝C*τ ref +(R stop -R start )*τ 1 +(S stop -S start )*τ 2 ，
wherein C, (R) stop -R start ) Sum (S) stop -S start ) Respectively a first counter value, a second counter value and a third counter value, τ ref 、τ 1 And τ 2 Respectively a counter unit, a first time measuring unit and a second time measuring unitResolution of the two-time measurement unit.
According to the time-to-digital conversion circuit, the counter unit, the first time measuring unit and the second time measuring unit which are sequentially connected are arranged, granularity is from large to small, time measurement data with higher resolution can be obtained, and the problem that a large number of delay units and registers are used to cause high integral nonlinearity in the prior art and precision is limited by process characteristics (PVT) can be solved; meanwhile, by setting that the first time measurement unit comprises a first delay phase-locked loop circuit, a synchronous circuit and an asynchronous circuit, the total delay caused in the synchronous signal propagation process is compensated by the delay in the asynchronous signal propagation path, the time measurement signal can be prevented from shifting between the first time measurement unit and the second time measurement unit, and the time measurement precision of the time digital conversion circuit is ensured (through testing, the time digital conversion circuit measurement precision in the embodiment can reach 10 ps).
In addition, the time-digital conversion circuit can configure an internal register in the time-digital conversion circuit according to the frequency of an input reference clock signal, and the control circuit carries out corresponding frequency multiplication processing, so that the flexibility of circuit design is greatly improved; and the working modes of the multiple channels can be switched through an external SPI register, so that parallel data processing of five modes is supported, and the design flexibility is improved.
It is apparent that the above examples are given by way of illustration only and are not limiting of the embodiments. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. While obvious variations or modifications are contemplated as falling within the scope of the present invention.
Claims (7)
1. A time-to-digital conversion circuit, comprising:
a counter unit for counting pulses of the timing signals and outputting residual information between the timing signals and a first counter value;
the first time measurement unit comprises a first delay phase-locked loop circuit, a synchronous circuit and an asynchronous circuit, wherein the synchronous circuit and the asynchronous circuit are connected with the first delay phase-locked loop circuit, and the synchronous circuit and the asynchronous circuit are connected with the counter unit; the synchronous circuit is used for carrying out signal retiming on the residual information based on the phase signal output by the first delay phase-locked loop circuit and outputting a synchronous signal and a second counter value; the asynchronous circuit is used for directly outputting the residual information through a delay chain to obtain an asynchronous signal;
a second time measurement unit connected to the synchronous circuit and the asynchronous circuit, for interpolating timing the synchronous signal and the asynchronous signal, and outputting a third counter value between the synchronous signal and the asynchronous signal; the second time measuring unit comprises a second delay phase-locked loop circuit, and a delay chain in the second delay phase-locked loop circuit is a delay chain with a parallel proportional load capacitor with double-end output;
and the decoder is connected with the counter unit, the synchronous circuit and the second time measuring unit and is used for obtaining the time difference between the timing signals based on the first counter value, the second counter value and the third counter value.
2. The time to digital conversion circuit of claim 1, wherein the feedback clock signal of the second delay locked loop circuit is an i-th phase signal of the phase signals output by the first delay locked loop circuit, and the reference clock signal is an i+2-th phase signal of the phase signals output by the first delay locked loop circuit.
3. A time to digital conversion circuit according to claim 1 or 2, wherein if the output of the first delay locked loop circuit is out of phase τ 1 N of (2) 1 The phase difference of the phase-separated signal output by the second delay phase-locked loop circuit is tau 2 N of (2) 2 The phase-separated signal is then passed through the delay chain of the second delay phase-locked loop circuit to obtain a phase difference tau 2 The asynchronous signal obtains a phase difference of n after passing through a delay chain of the second delay phase-locked loop circuit 2 τ 2 And N 2 Is n 2 Is a multiple of (2).
4. The time to digital conversion circuit of claim 3, wherein the synchronization circuit comprises a first set of flip-flops and a second set of flip-flops, and wherein the first set of flip-flops and the second set of flip-flops each comprise N 1 A plurality of triggers; n of the output of the first delay phase-locked loop circuit 1 The split-phase signals are N in the first trigger group respectively 1 The input signals of the triggers are the clock signals of the triggers in the first trigger group; n in the first trigger group 1 The complementary outputs of the flip-flops are respectively connected to N in the second flip-flop group 1 Data inputs of the flip-flops, and n of the input signals of the flip-flops in the first flip-flop group 1 The phase-shifted signals are clock signals of the corresponding flip-flops in the second flip-flop group.
5. The time to digital conversion circuit according to claim 4, wherein the asynchronous circuit comprises a phase difference n 1 τ 1 Is a delay chain of (a).
6. The time-to-digital conversion circuit according to claim 3, wherein the second time measurement unit further comprises a latch circuit, the latch circuit is a lattice structure formed by a plurality of flip-flops, the synchronous phase-separated signal is an input signal of a flip-flop in the lattice structure, the asynchronous phase-separated signal is a clock signal of a flip-flop in the lattice structure, and a phase difference between output signals of a group of lateral flip-flops in the lattice structure is τ 2 The phase difference between the output signals of the vertical trigger groups in the lattice structure is n 2 τ 2 。
7. The time to digital conversion circuit of claim 1, wherein the delay chain in the first delay locked loop circuit is comprised of a plurality of differential delay tunable multiplexers having two input channels.
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