CN112558519A - Digital signal delay method based on FPGA and high-precision delay chip - Google Patents
Digital signal delay method based on FPGA and high-precision delay chip Download PDFInfo
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Abstract
The invention discloses a digital signal delay method based on FPGA and a high-precision delay chip, which comprises the steps of firstly, calculating a delay parameter of the leading edge or the trailing edge of a digital signal by utilizing a delay time length T set by a user, a width Tw of an output pulse after delay and a measured time value T1 of an input signal relative to an FPGA clock; then, carrying out time delay processing on the digital signal by using the time delay parameter; and finally, synthesizing the front edge and the back edge of the signal subjected to delay processing through logic operation to obtain the output pulse with accurately adjustable delay and width. The digital signal delay method disclosed by the invention utilizes the FPGA and the high-precision delay chip, adopts a digital signal delay mode combining coarse delay with medium delay and fine delay, effectively reduces signal delay jitter, improves delay resolution, finishes most functions in one chip, has simple and reliable hardware circuit and high integration degree, and effectively reduces delay errors.
Description
Technical Field
The invention belongs to the technical field of electronics, and particularly relates to a digital signal delay method based on an FPGA and a high-precision delay chip.
Background
In modern large-scale physical experiments, electronic devices and instruments are generally started and stopped by using an electric pulse trigger signal, or a certain function of test equipment is triggered by using the electric pulse trigger signal in a test. Fig. 1 is a schematic structural diagram of a typical large physical test apparatus in the prior art, and it can be seen from the diagram that the positions and the placements of the devices or instruments are different, and in addition, the requirements on the time and the width of the electric pulse trigger signal input to the device or instrument are different because the functions realized by the devices and the requirements on the start-stop timing sequence of the device or instrument are different. In some experiments with higher requirements, the apparatus and instrument not only require the resolution of the time and width of the trigger signal to be of the order of 10ps, but also have strict requirements on the jitter and rise time of the electrical pulse trigger signal. In order to solve the above problems, a high-precision delay instrument is often used in a trigger system of a large-scale physical experiment to perform delay and width setting on trigger signals of each electronic device and instrument.
The traditional time delay instrument based on an analog time-amplitude converter (TAC) and an analog vernier caliper is gradually replaced by a digital time delay instrument due to the complex circuit, low integration level, high cost and high power consumption.
The existing digital delay methods have the following two types: the first kind adopts high precision delay chip to realize delay, because the method does not process coarse delay for signal, the dynamic range of delay depends on the delay chip, the dynamic range of the general delay chip is only a few microseconds. Therefore, although the delay resolution of the method can reach 10ps level, the dynamic range of the delay is only a few microseconds, and the requirement of a large-scale physical experiment cannot be met;
the second type is that a Field Programmable Gate Array (FPGA) chip is adopted to construct a coarse counter to realize time delay, the time delay dynamic range of the method is large, and the method can meet the experimental requirements, but because the resolution capability of the time delay is determined by the clock period of the coarse counter, the clock period is often in the nanosecond level, and the resolution capability of the method is only in the nanosecond level.
Therefore, a digital signal delay method is needed, which can achieve ps-level delay resolution and large dynamic range time delay, and can reduce delay jitter.
Disclosure of Invention
In view of this, the present invention provides a digital signal delay method based on an FPGA and a high-precision delay chip.
In order to achieve the purpose, the invention adopts the following technical scheme: a digital signal delay method based on FPGA and high-precision delay chip comprises the following steps:
s1: a user sets the delay time T of an input signal and the width Tw of an output pulse after delay according to requirements;
s2: measuring a time value T1 of the input signal relative to the FPGA clock by using the TDC;
s3: respectively calculating the delay parameter of the leading edge or the trailing edge of the digital signal by using the parameters T, Tw and T1;
s4: delaying the leading edge and the trailing edge of the digital signal by using the delay parameter calculated in the step S3;
s5: and synthesizing the front edge and the back edge of the signal subjected to delay processing through logic operation to obtain the output pulse with accurately adjustable delay and width.
Preferably, in step S1, parameters T and Tw satisfy the following relationship: t < Tclk × (2)n-1)，T+Tw＜Tclk×(2n-1), where n is the number of bits of the coarse counter and Tclk is the delay clock period of the coarse delay.
Preferably, the time-to-digital converter (TDC) in step S2 is any one of a TDC built in the FPGA and a dedicated TDC chip outside the FPGA chip.
Preferably, in step S3, the leading edge delay parameter of the signal is related to the parameters T and T1, and the trailing edge delay parameter is related to both the parameters T, Tw and T1.
Preferably, the delay parameters calculated in step S3 include two delay parameters, namely a coarse delay period N and a fine delay Code value Code, or three delay parameters, namely a coarse delay period N, a middle delay stage Tap and a fine delay Code value Code.
Preferably, the digital signal delay processing in step S4 is a combination of a coarse delay and a fine delay, or a combination of a coarse delay, a medium delay and a fine delay.
Preferably, the coarse delay is realized by a coarse delay counter in the FPGA, the medium delay is realized by controlled delay unit IODELAY logic in the FPGA chip or a DLL chip outside the FPGA chip, and the fine delay is realized by a high-precision delay chip outside the FPGA chip or a delay chain resource in the FPGA chip.
The invention has the beneficial effects that: the digital signal delay method disclosed by the invention utilizes the FPGA and the high-precision delay chip, adopts a digital signal delay mode combining coarse delay with medium delay and fine delay, reduces delay jitter and improves delay resolution, and the delay pulse signal obtained by the method can be used for triggering signals of electronic equipment and instruments in large-scale physical experiments; according to the digital signal delay method disclosed by the invention, the time value T1 of the input signal relative to the FPGA clock is measured, even if the input signal is asynchronous with the local clock, the delay function can be accurately realized, and the error is effectively reduced; the digital signal delay method disclosed by the invention respectively delays the front edge and the back edge of the output pulse, and then performs logic operation to obtain synthesis, so that the delay and the width of the output pulse simultaneously meet the requirements of delay resolution and large dynamic range.
Drawings
FIG. 1 is a schematic diagram of a typical large physical experiment layout;
fig. 2 is a schematic diagram of a principle of realizing high-precision time delay.
Fig. 3 is a flow chart of the digital signal delay method based on the FPGA and the high-precision delay chip disclosed by the invention.
Fig. 4 is a schematic structural diagram of a digital signal delayer based on an FPGA and a high-precision delay chip.
Detailed Description
It will be appreciated by those of ordinary skill in the art that the embodiments described herein are intended to assist the reader in understanding the principles of the invention and are to be construed as being without limitation to such specifically recited embodiments and examples. Those skilled in the art can make various other specific changes and combinations based on the teachings of the present invention without departing from the spirit of the invention, and these changes and combinations are within the scope of the invention.
The invention is described in detail below with reference to the figures and specific embodiments.
Example 1
In this embodiment, a digital signal delay method of coarse delay + medium delay + fine delay is provided, and as shown in fig. 3, this embodiment includes the following steps:
s1: a user sets the delay time T of an input signal and the width Tw of an output pulse after delay according to requirements; the parameters T and Tw satisfy the following relationship: t < Tclk × (2)n-1)，T+Tw＜Tclk×(2n-1), where n is the number of bits of the coarse counter, Tclk is the coarse delay clock period, it is readily apparent from the above equation that the maximum value setting of T and Tw is related to the number of bits setting of the coarse counter;
s2: the TDC is used to measure the time value T1 of the input signal relative to the FPGA clock, as shown in fig. 4, in this embodiment, the TDC constructed in the FPGA is used to obtain the time value of the input signal relative to the FPGA clock, and in addition, a dedicated TDC chip outside the FPGA chip may be used to perform the measurement;
s3: respectively calculating delay parameters of the leading edge or the trailing edge of the digital signal by using the parameters T, Tw and T1, wherein the delay parameters specifically comprise: the method comprises the following steps of a coarse delay period N, a middle delay stage number Tap and a fine delay Code value Code, wherein leading edge delay parameters are only related to parameters T and T1, and the calculation method comprises the following steps:
the trailing edge delay parameter is related to both T, Tw and T1, and is calculated as follows:
in the above formula, floor represents rounding the calculated result downwards, Tclk is a coarse delay clock period, Ttap is the delay time of each stage of middle delay, and Tcode is the delay time of each code value of fine delay;
s4: delaying the leading edge and the trailing edge of the digital signal by using the delay parameter calculated in step S3, where the embodiment needs to perform coarse delay, medium delay, and fine delay on both the leading edge and the trailing edge of the signal;
dividing the time length T needing time delay into: the integer multiple part of the coarse delay clock period Tclk is N × Tclk, and the part T2 remaining after subtracting the integer multiple N × Tclk of the coarse delay clock period Tclk, where the coarse delay refers to the delay of completing the duration of N × Tclk, and the middle delay and the fine delay complete the delay of the duration of T2+ T1. For example, if a signal is delayed for 1234.56ns, and a coarse clock period is 10ns, the coarse delay is responsible for the 1230ns delay, and the fine delay (or the middle delay plus the fine delay) is responsible for the 4.56ns delay, where the 1230ns is N × Tclk, the 4.56ns is called T2, and the sum of the 4.56ns and T1 is subjected to a middle delay and a fine delay, where if T1 is 1ns, the delay time of the middle delay and the fine delay is 5.56ns, the middle delay Ttap is determined to be 0.1ns, and the fine delay is 0.01ns, the middle delay needs to complete the 5.5ns delay, and the fine delay only needs to complete the 0.06ns delay.
This is done primarily because the signal to be delayed will not typically arrive at the edge of the coarse delay clock period Tclk, and in order to make the delay of 4.56ns more accurate, a TDC is required to measure the time of the input signal relative to the clock edge and then compensate back, the delay compensation schematic of which is shown in fig. 2.
The specific time delay process is as follows: and when the count value of the coarse delay counter reaches N, the output signal of the coarse delay logic in the FPGA jumps, and the output signal of the coarse delay logic is accessed into the middle delay logic part and the high-precision delay chip to carry out middle delay and fine delay.
For the leading edge, the output signal output of the coarse delay logic changes from 0 jump to 1; for the trailing edge, the output signal of the coarse delay logic jumps from 1 to 0. After all the outputs of the coarse delay logic in the FPGA jump and wait for 1 period, all the outputs of the coarse delay logic are reset back to the original state, namely the front edge output is reset back to 0 from 1, and the back edge output is reset back to 1 from 0.
The coarse delay of this embodiment is realized by a coarse delay counter in the FPGA, the intermediate delay is realized by a controlled delay unit IODELAY in the FPGA chip, and in addition, the intermediate delay can be realized by a DLL chip outside the FPGA chip, and the fine delay in this embodiment is realized by a high-precision delay chip outside the FPGA chip, and in addition, the fine delay can be realized by a delay chain resource in the FPGA chip.
S5: the front edge and the back edge of the signal after delay processing are synthesized through AND logic operation, and output pulses with accurate and adjustable delay and width are obtained.
If the user does not pay attention to the width of the output pulse or wants to obtain higher pulse integration level, the user only needs to perform accurate delay processing on the leading edge of the output pulse to directly output the output pulse, does not need to perform delay processing on the trailing edge of the output pulse, and does not need to perform logic operation synthesis work.
In practice, the fine delay chip can complete the delay within the dynamic range of 5.56ns, so that the delay logic is not used, but when the delay logic is not used, the delay jitter is higher and is 50ps due to the process error of the delay chip, the delay jitter after the intermediate delay is adopted can be reduced to 25ps, and obviously, the signal delay jitter can be obviously reduced by adopting the intermediate delay.
However, for some use scenarios where the requirement for delay jitter is not very strict, a coarse count control logic and a high-precision delay chip can be directly adopted to complete a high-precision time delay function requiring delay and fine delay, and no intermediate delay is performed by the IODELAY logic to reduce delay jitter.
In summary, the present disclosure provides a digital signal delay method based on an FPGA and a high-precision delay chip, where a TDC built in the FPGA chip or a dedicated TDC chip measures a time value relative to an FPGA clock, and the time value and a user setting value are calculated in the FPGA to obtain a coarse delay period number, a medium delay stage number, and a fine delay code value of a leading edge and a trailing edge of an output pulse, which are used to configure a coarse count control logic, an IODELAY logic, and a high-precision delay chip of the leading edge and the trailing edge of the output pulse, respectively, and the delayed leading edge and trailing edge are subjected to logic operation to obtain the output pulse, thereby finally realizing setting of delay and width of a low-jitter and high-resolution digital signal.
Claims (7)
1. A digital signal delay method based on FPGA and high-precision delay chip is characterized by comprising the following steps:
s1: a user sets the delay time T of an input signal and the width Tw of an output pulse after delay according to requirements;
s2: measuring a time value T1 of the input signal relative to the FPGA clock by using the TDC;
s3: respectively calculating the delay parameter of the leading edge or the trailing edge of the digital signal by using the parameters T, Tw and T1;
s4: delaying the leading edge and the trailing edge of the digital signal by using the delay parameter calculated in the step S3;
s5: and synthesizing the front edge and the back edge of the signal subjected to delay processing through logic operation to obtain the output pulse with accurately adjustable delay and width.
2. The digital signal delay method based on the FPGA and the high-precision delay chip as claimed in claim 1, wherein the parameters T and Tw in the step S1 satisfy the following relationship: t < Tclk × (2)n-1)，T+Tw＜Tclk×(2n-1), where n is the number of bits of the coarse counter and Tclk is the delay clock period of the coarse delay.
3. The digital signal delay method based on the FPGA and the high-precision delay chip as claimed in claim 1, wherein the TDC in the step S2 is any one of a TDC built in the FPGA and a dedicated TDC chip outside the FPGA chip.
4. The digital signal delay method based on FPGA and high precision time delay chip of claim 1, wherein the signal leading edge delay parameter is related to parameters T and T1, and the signal trailing edge delay parameter is related to parameters T, Tw and T1 in step S3.
5. The digital signal delay method based on the FPGA and the high-precision delay chip of claim 1, wherein the delay parameters calculated in the step S3 include two delay parameters of a coarse delay period N and a fine delay Code value Code, or three delay parameters of a coarse delay period N, a middle delay stage Tap, and a fine delay Code value Code.
6. The digital signal delay method based on the FPGA and the high-precision delay chip as claimed in claim 1, wherein the digital signal delay processing in the step S4 is a combination of a coarse delay and a fine delay of the signal, or a combination of a coarse delay, a medium delay and a fine delay.
7. The digital signal delay method based on FPGA and high precision delay chip as claimed in claim 6, wherein the coarse delay is realized by a coarse delay counter in FPGA, the middle delay is realized by controlled delay unit IODELAY logic inside FPGA chip or DLL chip outside FPGA chip, and the fine delay is realized by high precision delay chip outside FPGA chip or delay chain resource inside FPGA chip.
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| US20230059991A1 (en) * | 2020-03-12 | 2023-02-23 | Analog Devices International Unlimited Company | Delay locked loops with calibration for external delay |
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