KR101991052B1 - Realtime High Speed and High Precision Timing Generator Using FPGA SerDes Logic - Google Patents

Abstract

The present invention relates to a real-time high-speed high-precision timing generator, capable of realizing high precision by using an FPGA serializer/deserializer (SerDes) logic, which comprises: a rate memory for outputting rate data; a digital down counter for calculating a long time unit delay time on the basis of upper bits of the rate data, and outputting a pulse after the calculated long time unit delay time; an accumulator for calculating an intermediate time unit delay time and a precise time unit delay time on the basis of lower bits of the rate data; a SerDes logic for delaying the pulse output from the digital down counter by the calculated intermediate time unit delay time; and a vernier unit for delaying the pulse delayed in the SerDes logic by the calculated precise time unit delay time.

Description

FIELD OF THE INVENTION [0001] The present invention relates to a real-time high-speed and high-precision timing generator using an FPGA,

The present invention relates to a high-speed and high-precision timing generator, and more particularly, to a real-time high-speed and high-precision timing generator capable of realizing high-precision using an FPGA deserializer (Serdes: Serializer / Deserializer) logic.

A test apparatus is used to give a test pattern to a device under test (DUT) to be tested and check its operation to determine whether it is good or not. The test apparatus includes a pattern generator (PG) for generating a test pattern to be given to the DUT, and a timing generator (TG) for defining a timing for giving the test pattern to the DUT. The period (frequency) of such a test pattern is also called a test rate, and the test apparatus must be capable of changing the test rate in real time.

Generally, a real-time timing generator is used to change the test rate of the test apparatus. This timing generator is composed of a down counter, which is a unit delay element for a long time, and a Vernier element, which is a precision time unit delay element. The real-time timing generator changes the test rate in real time by adjusting the time interval between any two pulses using a digital down counter and a Bernier device.

Since the Bernier device is sensitive to heat, voltage, and noise, it is desirable to design the timing generator as an ASIC (Application Specific Integrated Circuit) for reliable operation of the Bernier device. However, such an ASIC design requires a long development period (at least 2 years).

Typically, a field programmable gate array (FPGA) includes a loaderable digital down counter and 32 burner devices. The internal frequency of the FPGA is 400 MHz. The digital down counter can delay the output pulse time in 2.5 ns, and the more accurate output pulse time delay can be realized with the Bernier device. Current single-burner devices in FPGAs can be delayed for 19.5 ps, 39 ps, 78 ps, and so on. The maximum time that can be delayed by the Bernabeu (32 Bernie devices) embedded in the FPGA is about 2.45 ns (1.25 ns or 625 ps) as '78 ps (39 ps or 19.5 ps) * 32'. The pulse output time can be delayed from 0 to 2.45 ns (0 to 1.25 ns or 0 to 625 ps) depending on the number of Bernie devices used in the 32 built-in devices in the FPGA. In the conventional FPGA, the timing generator uses a digital down counter for a time delay of 2.5 ns, and uses a vanity block with a 78 ps delay specification for a finer time delay.

FIG. 1 is a block diagram of a timing generator implemented in an FPGA used in a low speed tester and a monitoring burn in terabyte (MBT).

The timing generator includes a rate memory 11, an accumulator 12, a digital down counter 13, and a Bernier 14.

The rate memory 11 stores 64 24-bit rate data and outputs one rate data Rate [23: 0] when the TO_EN signal is enabled. This 24-bit rate data is provided as a test rate to the accumulator 12 and the digital down counter 13 at the same time.

The digital down counter 13 calculates the delay time of the output pulse based on the upper 19 bits data (Rate [23: 5]) of the rate data Rate [23: 0] As shown in FIG. This will be explained in detail. A clock signal having a frequency of 400 MHz (2.5 ns cycle) is input to the clock terminal MCLK of the digital down counter 13. The digital down counter 13 sets the counter initial value based on the upper 19 bits data (Rate [23: 5]), subtracts the counter value one by one each time one clock is input to the MCLK terminal, A pulse is output to the output terminal Q. Therefore, the unit of the pulse output delay time of the down counter 13 is 2.5 ns. For example, if the test rate is 6 ns, the counter initial value of the digital down counter 13 is set to 2 from the upper 19 bits data, and when one clock is input to the MCLK terminal, the counter value is subtracted by 1, If more input, the counter value is decremented to 0 and a pulse is output to the output terminal. Since the period for inputting the clock to this MCLK terminal is 2.5 ns, the pulse output delay time unit is 2.5 ns.

The accumulator 12 calculates the fine delay time of the pulse output from the digital down counter 13 based on the lower 5 bits rate data (Rate [4: 0]) of the rate data Rate [23: 0] Delay. The accumulator 12 accumulates the lower 5 bits rate data (Rate [4: 0]) and transfers the lower 5 bits (Residue [4: 0]) data of the accumulated value to the burner unit 14. [ Since 5 bits have 32 status values, the number of Bernie elements participating in the delay driving is determined by the data of the lower 5 bits (Resildue [4: 0]) of this accumulated value. For example, when the lower 5 bits of the cumulative value (Residue [4: 0]) is '10110', 22 vanier elements are driven, and the delay time at this time is 78.125ps * 22 = 1.718ns .

When the cumulative value of the accumulator 12 exceeds 2.5 ns, that is, when the sixth bit of the accumulated value becomes 1, the carry terminal of the accumulator 12 is disabled to the CntEn terminal of the digital down counter 13 ) Signal is output, and the digital down counter 13 then stops counting down for one clock input time of MCLK.

The reason why such an operation is necessary will be described with reference to FIG. 2 and an example in which the rate data is 4 ns. When the first rate data is 4 ns, the upper rate data should be delayed by 2.5 ns (down counting once) and the lower rate data should be delayed by 1.5 ns. Therefore, for the first rate data, the TO_EN pulse is output after a delay of 2.5ns from t0, and the first output is output after the TO_EN pulse is delayed by 1.5ns (t1).

When the first output is output, the second rate data is output (t1). The second output should be output after 4ns delay (t2) from the first output output time (t1). Similarly to the first rate data, the second rate data is set such that one down counter is set for the higher rate data and 1.5 ns is delayed for the lower rate data. If the starting point of the MCLK clock coincides with the rate data outputting point as at t0, the downlink data may be down-counted once with the upper rate data and the rest may be delayed with the lower rate data. In the case of the second rate data, The MCLK clock does not start. Therefore, if the TO_EN pulse is output immediately, the time delay corresponding to the second rate data can not be obtained. Therefore, when the accumulation value of the delay time to be delayed with the lower rate data exceeds 2.5 ns (in this case, 1.5 ns + 1.5 ns = 3 ns) and the sixth bit value of the accumulated value becomes 1, The disable signal is output to the CntEn terminal of the digital down counter 13 at the Carry terminal. When the disable signal is input, the digital down counter 13 stops down counting for one MCLK clock and continues down counting at the next MCLK clock.

The accumulator 12 outputs the lower 5 bits (Residue [4: 0]) data (value corresponding to '3 ns - 2.5 ns = 0.5 ns') of the accumulated delay time to the burner unit 14. In this case, the lower 5 bits (Residue [4: 0]) of the cumulative value corresponding to 0.5 ns is provided to the burner unit 14, and the output is output after the additional time delay of 0.5 ns for the second TO_EN pulse.

As described above, the conventional timing generator implemented in the FPGA can generate time delay in units of 78 ps using 32 Bernie elements. However, since the memory of the DUT has been increasingly speeded up recently, it is required to increase the test rate and to achieve high precision. However, since the internal operating frequency of the FPGA is 400 MHz and the delay accuracy of the digital down counter is 2.5 ns, 32 binary devices need to delay 2.5 ns at uniform intervals. Therefore, It is difficult to implement a more advanced high-speed and high-precision timing generator in an FPGA.

Korea Patent No. 1429257 Korean Patent No. 1254439 Korean Patent No. 1285287

This invention implements an intermediate time delay between the digital down counter for long unit delays and the burner device for precision time unit delays using the embedded logic in the FPGA to change the test rate in real time A high-speed and high-precision timing generator.

According to an aspect of the present invention, there is provided a real-time high-speed and high-precision timing generator using FPGA hardware, comprising: a rate memory for outputting rate data;

A digital down counter for calculating a long time unit delay time based on upper bits of the rate data and outputting a pulse after the calculated long time unit delay time;

An accumulator for calculating an intermediate time unit delay time and precision time unit delay time based on lower bits of the rate data;

A deserial logic for delaying a pulse output from the digital down counter by the calculated intermediate time unit delay time;

And a burner unit for delaying the delayed pulse in the subtitle logic by the calculated precision time unit delay time.

According to the present invention, it is possible to provide a real-time high-speed and high-precision timing generator capable of precisely adjusting the delay timing in units of 39 ps or 19.5 ps by using a digital down-counter, There is an advantage.

FIG. 1 is a block diagram of a timing generator implemented in an FPGA used in a low speed tester and a monitoring burn in terabyte (MBT).
2 is an operation timing diagram of the timing generator of FIG.
3 is a diagram for explaining the operation of 2: 1 subsidiary logic.
4 is a diagram for explaining the operation of the 4: 1 subsidiary logic.
FIG. 5 is a block diagram of a real-time high-speed and high-precision timing generator according to an embodiment of the present invention using a 2: 1 subsidiary logic.
FIG. 6 is a block diagram of a real-time high-speed and high-precision timing generator according to another embodiment of the present invention using 4: 1 subsidiary logic.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear. In addition, the terms described below are defined in consideration of the functions of the present invention, and this may vary depending on the intention of the user, the operator, or the custom. Therefore, the definition should be based on the contents throughout this specification.

3 is a diagram for explaining the operation of the 2: 1 dead logic 31 used in the present invention. The 800Mhz clock and the 200Mhz clock are input to the server logic. If input terminal D0 is high and D1 is low, En terminal is enabled to active high, a pulse of 625ps width is output immediately from 0ns without a time delay (① pulse). When input terminal D0 is 'low' and input terminal D1 is 'high', when En terminal is enabled, a pulse of 625ps width is output after 1.27ns delay (② pulse).

4 is a diagram for explaining the operation of the 4: 1 context logic 41 used in the present invention. This 4: 1 DTS logic is controlled by the high / low combination of four input terminals (D0, D1, D2 and D3) at the moment when the En terminal is enabled (D0 (High), D1 (Low), D2 , D3 (Low)) (1 pulse) or En terminal is enabled and after 625ps delay (D0 (Low), D1 (High), D2 Is enabled and the En terminal is enabled after 1.25ns delay (D0 (Low), D1 (Low), D2 (High), D3 , D1 (Low), D2 (Low), and D3 (High)) (the fourth pulse) and 625ps wide pulse are output to the output terminal Q.

FIG. 5 is a block diagram of a real-time high-speed and high-precision timing generator according to an embodiment of the present invention using a 2: 1 subsidiary logic.

The timing generator according to the present invention includes a rate memory 51 for outputting rate data, a digital down converter 51 for calculating a long time unit delay time based on upper bits of the rate data and outputting a pulse after the calculated long time unit delay time, An accumulator 52 for calculating an intermediate time unit delay time and a precise time unit delay time based on the lower bits of the rate data, a counter 53 for calculating a pulse output from the digital down counter 53, A burner unit 56 for delaying the pulse delayed by the dead time logic unit 55 by the calculated precision time unit delay time, And a deserial controller 54 for outputting a 'high' or 'low' signal to the input terminals of the deserial logic according to the delay time.

The rate memory 51 stores 64 24-bit rate data and outputs one rate data Rate [23: 0] when the TO_EN signal is enabled. This 24-bit rate data is provided as a test rate to the accumulator 52 and the digital down counter 53 at the same time. In the rate memory 11 of FIG. 1, rate data of 78 ps accuracy is stored, but in the rate memory 51 of FIG. 5, rate data of 39 ps precision is stored.

The digital down counter 53 calculates a delay time of a long time (2.5 ns) of the output pulse based on the upper 18 bits rate data (Rate [23: 6]) of the rate data Rate [23: 0] And outputs a pulse to the output terminal Q after a delay. The digital down counter 53 operates in the same manner as the digital down counter 13 of FIG. 1, and a detailed description thereof will be omitted.

The accumulator 52 calculates the fine delay time of the pulse output from the digital down counter 53 based on the lower 6 bits rate data (Rate [5: 0]) of the rate data Rate [23: 0]. The accumulator 52 accumulates the lower 6 bits rate data Rate [5: 0] and delivers the lower 6 bits of the accumulation value (Residue [5: 0]) data to the deserial controller 54. Based on the 6th bit of the accumulation value, the predecode control unit 54 outputs a signal of high or low to the input terminal of the death logic 55, and transmits the lower 5 bits data of the cumulative value to the burner unit 56 .

That is, when the sixth bit of the cumulative value is 0, that is, when the fine delay time is between 0 and 1.25 ns, the command control unit 54 outputs a high / low signal to the input terminal D0 / D1 of the dead- low '. When the sixth bit of the cumulative value is 1, that is, when the fine delay time is between 1.25 ns and 2.5 ns, the command control unit 54 outputs 'low / high' to the input terminal D0 / D1 of the dead logic 55 '.

When the 'high / low' signal is input to the input terminal D0 / D1, the undershoot logic 55 outputs the pulse output from the digital down counter 53 without delay. When the 'low / high' signal is input to the input terminal D0 / D1, the undersolution logic 55 delays the pulse output from the digital down counter 53 by 1.25 ns and outputs the pulse.

On the other hand, based on the lower 5 bits (Resildue [4: 0]) data of the cumulative value transferred to the burner unit 56, the burner unit 56 that participates in the delay driving among the 32 burner units constituting the burner unit 56 The number is determined. Individual Bernier devices can delay the time in precise time (about 39 ps). The maximum delay time is 1.25 ns at the burner section 56 composed of a burner element with a precision of 39 ps.

In the present invention, by performing a delay of a long time (2.5 ns) with a digital down counter, performing a delay of an intermediate time (1.25 ns) with a dead-time logic, The precision of the generator can be realized with high precision of 39 ps.

When the cumulative value of the accumulator 52 exceeds 2.5 ns, that is, when the seventh bit of the accumulated value becomes 1, the carry terminal of the accumulator 52 is disabled to the CntEn terminal of the digital down counter 53 ) Signal is output, and the digital down counter 53 then stops down counting for one clock input time of MCLK. The reason why the digital down counter stops counting down for one clock is the same as that described above with reference to FIG. 1, and a detailed description thereof will be omitted here.

FIG. 6 is a block diagram of a real-time high-speed and high-precision timing generator according to another embodiment of the present invention using 4: 1 subsidiary logic.

The timing generator according to the present invention includes a rate memory 61, an accumulator 62, a digital down counter 63, a dead-time control unit 64, a dead logic 65, and a Vernier (66).

The rate memory 61 stores 64 24-bit rate data and outputs one rate data Rate [23: 0] when the TO_EN signal is enabled. The 24-bit rate data is provided as a test rate to the accumulator 62 and the digital down counter 63 at the same time. Rate data of 78 ps precision is stored in the rate memory 11 of Fig. 1, but rate data of 19.5 ps precision is stored in the rate memory 61 of Fig.

The digital down counter 63 calculates a delay time in units of a long time (2.5 ns) of the output pulse based on the upper 17 bits rate data (Rate [23: 7]) of the rate data Rate [23: 0] And outputs a pulse to the output terminal Q after a time delay. The digital down counter 63 operates in the same manner as the digital down counter 63 of FIG. 1, and a detailed description thereof will be omitted.

The accumulator 62 calculates the fine delay time of the pulse output from the digital down counter 63 based on the lower 7 bits rate data (Rate [6: 0]) of the rate data Rate [23: 0]. The accumulator 62 accumulates the lower 7 bits rate data (Rate [6: 0]) and transfers the lower 7 bits (Residue [6: 0]) data of the accumulation value to the deserial controller 64. Based on the upper 2 bits data of the accumulation value, the desdes control unit 64 outputs a signal of high or low to the input terminal of the death logic 65 and outputs the lower 5 bits (Residue [4: 0]) data of the accumulation value And transfers it to the burner unit 66.

That is, when the upper 2 bits of the accumulation value is '00', that is, when the fine delay time is between 0 and 0.625 ns, the deaddesk control unit 64 sets the input terminal D0 / D1 / D2 / Outputs 'high / low / low / low' to D3. D1 / D2 / D3 of the dead logic 65 when the upper 2 bits of the accumulated value is '01', that is, when the fine delay time is between 0.625 ns and 1.25 ns, Low / high / low / low '. D1 / D2 / D3 of the dead logic 65 when the upper 2 bits of the accumulated value is '10', that is, when the fine delay time is between 1.25 ns and 1.875 ns, Low / low / high / low '. D1 / D2 / D3 of the dead logic 65 when the upper 2 bits of the accumulation value is '11', that is, when the fine delay time is between 1.875 ns and 2.5 ns, Low / low / low / high '.

When the 'high / low / low / low' is input to the input terminal D0 / D1 / D2 / D3, the undersolution logic 65 outputs the pulse output from the digital down counter 63 without a time delay. When the 'low / high / low / low' is input to the input terminal D0 / D1 / D2 / D3, the underseat logic 65 delays the pulse output from the digital down counter 63 by 0.625 ns and outputs the pulse. When the 'low / low / high / low' is inputted to the input terminal D0 / D1 / D2 / D3, the undersolution logic 65 delays the pulse output from the digital down counter 63 by 1.25 ns. When the 'low / low / low / high' is inputted to the input terminal D0 / D1 / D2 / D3, the undershoot logic 65 delays the pulse output from the digital down counter 63 by 1.875 ns.

On the other hand, based on the lower 5 bits (Resildue [4: 0]) data of the accumulated value transferred to the burner unit 66, the burner unit 66, which constitutes the burner unit 66, The number is determined. Individual Bernier devices can delay the time in precise time (about 19.5 ps). The maximum delay time in the burner section 66 constituted by the burner element with the accuracy of 19.5 ps is 0.625 ns.

According to the present invention, by performing a delay of a long time (2.5 ns) with a digital down counter, performing a delay of an intermediate time (0.625 ns) with the dead logic, and performing a delay of unit time (19.5 ps) The precision of the timing generator can be realized with a high precision of 19.5 ps units.

When the cumulative value of the accumulator 62 exceeds 2.5 ns, that is, when the eighth bit of the accumulated value becomes 1, the carry terminal of the accumulator 62 is disabled to the CntEn terminal of the digital down counter 63 ) Signal is output, and the digital down counter 63 then stops down counting for one clock input time of MCLK. The reason why the digital down counter stops counting down for one clock is the same as that described above with reference to FIG. 1, and a detailed description thereof will be omitted here.

51, 61: Rate memory 52, 62:
53, 63: Digital down counter 54, 64:
55,65: Seadeth Logic 56,66: Bernie Abu

Claims (7)

A rate memory for storing a plurality of rate data and outputting one rate data;
A digital down counter for calculating a long time unit delay time which is a pulse cycle according to a clock signal based on the upper bits of the rate data and outputting a pulse to an output terminal after counting the calculated long time unit delay time;
(N is a positive integer) bits excluding the upper bits of the rate data and outputs the lower n bits of the accumulated value, and counts the digital down counter according to the (n + 1) An accumulator for stopping for one clock;
A subtraction logic for delaying a pulse output from the digital down counter by an intermediate time unit delay time shorter than the pulse period calculated based on at least one higher bit among the lower n bits of the accumulation value;
A desd control unit for outputting a 'high' or 'low' signal to the input terminals of the desdus logic based on at least one higher bit among the lower n bits of the accumulation value;
Delaying the pulse delayed by the dead time logic by a precision time unit delay time shorter than the intermediate time unit delay time calculated based on lower bits of the lower n bits of the accumulation value excluding the at least one upper bit, Real-time high-speed and high-precision timing generator using FPGA's undisclosed logic. 2. The real-time high-speed and high-precision timing generator according to claim 1, wherein the desdesign logic is a 2: 1 desdesign logic. 2. The real-time high-speed and high-precision timing generator according to claim 1, wherein the desdesign logic is 4: 1 desdesign logic. 2. The real-time high-speed and high-precision timing generator according to claim 1, wherein the burner unit is composed of a 39-ps delayed burner element. 2. The real-time high-speed and high-precision timing generator according to claim 1, wherein the burner part is composed of a 19.5ps delayed burner element. delete delete

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