CN106405238B - Broadband modulation domain measuring system and method thereof - Google Patents
Broadband modulation domain measuring system and method thereof Download PDFInfo
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- CN106405238B CN106405238B CN201610723387.2A CN201610723387A CN106405238B CN 106405238 B CN106405238 B CN 106405238B CN 201610723387 A CN201610723387 A CN 201610723387A CN 106405238 B CN106405238 B CN 106405238B
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Abstract
The invention provides a broadband modulation domain measuring system, which comprises: the device comprises a signal synchronization unit, a logic selection unit, a first tap delay line multi-path delay unit, a second tap delay line multi-path delay unit, a first data buffer unit, a second data buffer unit and a processing unit; the signal synchronization unit receives a detected signal as an input, and an output signal is connected with the logic selection unit; the logic selection unit receives an output signal of the signal synchronization unit as an input, and the output signal is connected with the first tap delay line multi-path delay unit and the second tap delay line multi-path delay unit; the first tap delay line multi-path delay unit is connected with the first data buffer unit; the second tap delay line multi-path delay unit is connected with the second data buffer unit; the outputs of the first data buffer unit and the second data buffer unit are connected with the processing unit. The measuring system has simple structure, and greatly simplifies the design difficulty and complexity of circuits and time sequences.
Description
Technical Field
The invention relates to the technical field of testing, in particular to a broadband modulation domain measuring system and a broadband modulation domain measuring method.
Background
The modulation, time and frequency domains are referred to collectively as the "three-domain". The time domain analysis is to measure the relation of the amplitude of the input signal changing along with the time; the frequency domain analysis is to measure the relation of the amplitude of the input signal along with the frequency change; and the modulation domain analysis is to measure the frequency of the input signal with time.
With the development of communication technology, frequency agile conversion, continuous wave frequency modulation, linear frequency modulation, pulse modulation, digital modulation and combined modulation technology are rapidly developed and applied, and meanwhile, the frequency band is greatly expanded, and higher requirements are provided for indexes. In order to meet new requirements, modern modulation domain analysis needs to have measurement requirements of large bandwidth, high speed, high resolution, no dead zone, short sampling interval and the like.
Because the modulation domain analysis has unique advantages compared with time domain analysis and frequency domain analysis, the modulation domain analysis is widely applied to anti-interference communication, frequency agile radar and electronic warfare systems, and is a necessary instrument in the stages of development, production, maintenance and the like of military and civil electronic systems.
Modulation domain analysis can accurately represent transient characteristics of a measured signal by high-speed continuous zero idle measurement on the measured signal, a typical measurement timing sequence is shown in figure 1, a gate signal is synchronized by the measured signal, a counter of the measured signal is controlled by a synchronous gate, and errors of +/-1 measured signal event can be eliminated. The gate time is measured by using a standard time base signal with higher frequency, and higher frequency resolution can be obtained compared with the traditional counter. Since the standard time base signal is not synchronized with the synchronization gate, there are still ± 1 standard time base errors. In order to improve the measurement resolution, precise time interpolation measurement is needed for the error between the standard time base and the front edge and the rear edge of the gate, and the measurement result is calculated as follows:
f1＝N1/(T1+ΔT1-ΔT2) (1)
wherein: f. of1Is a frequency measurement;
N1is the measured signal count value;
t1 is calculated according to the time base count value;
ΔT1and Δ T2Is a precisely interpolated measurement.
A typical system for modulation domain measurement is shown in FIG. 2, where the gate generation unit first generates the original gate G0After the original gate and the tested signal are synchronized, a synchronous gate signal G is generateds，GsAs enable signals for two sets of event counters and time counters, GsWhen the level is high, the event counting unit 1 and the time counting unit 1 are controlled to count the measured signal and the time base signal, GsWhen the level is low, the event counting unit 2 and the time counting unit 2 are controlled to count the measured signal and the time-base signal. The synchronous gate signal and the time base signal generate the error pulse E of the leading edge of the synchronous gate through the gate logic control unit1And a trailing edge error pulse E2The two error pulses are sent to a charge-discharge circuit of the analog interpolation unit, the error pulses are linearly expanded into relatively large pulses, and error compensation and counting are completed after expansion processing, so that time or frequency resolution can be effectively improved.
The method for broadening the error pulse is as follows: charging a capacitor with a constant current during the error pulse is high; and then, discharging at a speed which is N times slower (for example, N is 1000), so that the time for the capacitor to discharge to the initial state is N times of the error pulse width, obtaining an amplified pulse signal through a shaping circuit at the moment of charging the capacitor and the moment of discharging the capacitor to the initial state, and then measuring and counting the amplified pulse signal by using a standard clock to obtain the expanded pulse width.
Another approach to error pulse spreading is: converting the error pulse into slope voltage according to the required proportion, sampling the voltage by using A/D at the starting time and the ending time of the error pulse, and calculating to obtain an expanded correction value through the measured voltage value and the voltage conversion proportion.
And finally, uniformly calculating the event count value, the time count value and the front and back interpolation correction value according to the formula (1) to obtain the final measured signal frequency.
In the above measurement system, the error pulse charging and discharging circuit of the analog interpolation unit is a key part, which directly determines the measurement precision and measurement speed of the whole system. The phase difference between the time-base signal and the synchronous gate signal is the error pulse signal to be measured, error pulse E1And E2The range of (1) is 0 to one time base signal period, and the situation of extremely narrow pulse can occur when the error pulse is directly used for charging, so that the situation of failure of analog interpolation or large error is caused, therefore, the error pulse is generally subjected to broadening processing, the error pulse is linearly converted into relatively large pulse or relatively large voltage after broadening, and then subsequent processing is carried out, and an error pulse charging and discharging circuit is generally realized by adopting a current source and a bridge diode charging and discharging circuit.
The main limitation of the above measurement system is that in order to avoid the situation that the narrow error pulse causes the analog interpolation to fail or causes a large error, the error pulse width is required not to be too small, and the error pulse width needs to be expanded; to achieve higher accuracy, a larger multiple of the error pulse is required to be expanded. The combined effect of the error pulse width and the large multiple spread allows the total time of the interpolation spread to be scaled. When the error pulse is expanded by the comparison circuit, the expanded pulse is wider, so that the time for interpolation and expansion is longer; when the sampling method of the AD converter is extended, in order to fully utilize the effective range of the AD converter, it is required to make the effective voltage range of charge and discharge wider, and the time for extending the interpolation is also longer. Meanwhile, after each measurement, a certain reset time is reserved for the analog interpolation unit, so that the minimum value of the sampling interval of continuous measurement is limited by the two modes finally.
Analog interpolation is less stable because analog circuits are more sensitive to operating temperature. Meanwhile, the circuit has certain leakage current, so that the capacitor charging output voltage has certain nonlinearity, the measurement precision is greatly influenced, and if the high resolution is achieved, the voltage nonlinearity needs to be accurately calibrated. In addition, due to the inherent charge-discharge time limit of the analog circuit, the time interval of single measurement of the analog interpolation method cannot be too small, so that the application is greatly limited in the field of high-speed short-sampling interval measurement.
In order to meet the requirement of high resolution, a vernier method is adopted for measurement when measuring error pulses. The vernier method measures the difference between the edge of the gate and the rising edge of the standard counting clock by using the principle of a vernier caliper, usually a pair of vernier clocks is designed, when the counting gate is opened and closed, a vernier counter is started, the vernier clock continuously tracks the standard counting clock, and when the edge of the vernier clock is coincided with the rising edge of the standard counting clock, the vernier counter is closed.
The measurement error is in direct proportion to the difference between the standard counting clock period and the vernier clock period, and the smaller the difference between the standard counting clock period and the vernier clock period is, the higher the resolution is. The cursor tracking time is inversely proportional to the difference between the counting clock period and the cursor clock period, and the smaller the difference between the counting clock period and the cursor clock period is, the longer the cursor tracking time is. In order to achieve higher resolution and reduce measurement time as much as possible, standard clock frequency and vernier clock frequency as high as possible need to be used, a complex high-resolution frequency control technology is needed to generate standard counting clock and vernier clock, the frequency and phase of all clocks are strictly controlled, and very high precision and stability are achieved. Meanwhile, when the interval between the edge of the counting gate and the rising edge of the counting clock is small, a certain dead zone interval exists in the starting and the closing of the vernier counter under the limitation of the response time of the device, so that the minimum tracking time is limited to a certain extent.
The implementation shown in fig. 3 was developed with the development of programmable logic devices on the basis of the measurement system shown in fig. 2.
The gate generating unit first generates an original gate G0After the original gate and the tested signal are synchronized, a synchronous gate signal G is generateds，GsAs enable signals for two sets of event-counting units and time-counting units, GsAt a high level, the high-speed event counting unit 1, the low-speed event counting unit 1, the high-speed time counting unit 1 and the low-speed time counting unit 1 are operated, GsAt the low level, the high-speed event counting unit 2, the low-speed event counting unit 2, the high-speed time counting unit 2, and the low-speed time counting unit 2 operate. The two groups of counting units generate gate synchronous signals G through the gate synchronous unitsAnd controlling, when one group of counting units works, the other group performs parameter buffering processing, synchronization and resetting operation. The synchronous gate signal and the time base signal generate the error pulse E of the leading edge of the synchronous gate through the gate logic control unit1And a trailing edge error pulse E2The two error pulses are sent to a digital interpolation processing unit, the error pulses are linearly expanded into relatively large pulses, error compensation and counting are completed after expansion processing, and time or frequency resolution can be effectively improved.
When all event counting units and time counting units are realized by special chips, if long-time measurement requirements are met, high-bit-width counting needs to be realized, the high-bit-width counting needs to be realized by cascading a plurality of special counting chips, the printed board is complex in design, and the realization cost is high. When all event counters and time counters are implemented by programmable devices, the advantages are that the integration level and the design flexibility can be greatly improved, the cost is reduced, but the measurement requirement of large bandwidth is difficult to achieve due to the speed limit of a logic chip. In the implementation shown in fig. 3, the high-speed event counting unit and the high-speed time counting unit are formed by dedicated high-speed counting chips, and the low-speed event counting unit and the low-speed time counting unit are implemented in a programmable logic chip, and receive the most significant bit output of the high-speed event counting unit as input and are responsible for counting the most significant bit of the input. The implementation scheme shown in fig. 3 fully utilizes the advantages of the special chip, such as high speed, high performance, large bandwidth, convenient programming of the programmable logic device, flexible configuration and good expansibility, and reasonably designs and integrates the special chip, so that the special chip fully exerts the respective characteristics, and the frequency range of the detected signal is expanded.
The implementation scheme shown in fig. 3 uses a digital interpolation technology, and the digital interpolation technology is characterized in that the measurement of the error pulse signal is completed by utilizing the characteristic determined by the propagation delay of the electric signal, and the digital interpolation technology has no charge-discharge link required by analog interpolation, improves the speed of interpolation expansion, and expands the effective range of sampling intervals. The digital interpolation principle is shown in fig. 4, the digital interpolation uses a group of delay units with theoretically equal propagation delay to form a delay chain, and the high-resolution time measurement is realized by adopting a method of 'serial delay and parallel counting'. The resolution of the delay interpolation method depends on the delay time of the unit delay unit, and the smaller the delay time, the higher the measurement resolution.
The prior art scheme has the following disadvantages:
(1) the prior art comprises a plurality of units such as two-path symmetrical event counting, time counting, interpolation counting and the like, and the realization and the control are very complicated.
When all event counters and time counters are realized by special chips, if long-time measurement requirements are met, high-bit-width counting needs to be realized, the high-bit-width counting needs to be realized by cascading a plurality of special counting chips, the printed board is complex in design, and the realization cost is high.
When all event counters and time counters are implemented by programmable devices, the advantages are that the integration level and the design flexibility can be greatly improved, the cost is reduced, but the measurement requirement of large bandwidth is difficult to achieve due to the speed limit of a logic chip.
The special chip and the programmable logic device are reasonably designed and integrated, respective characteristics can be fully exerted, the requirement of large bandwidth measurement of a modulation domain is met, and the design complexity is further improved.
(2) There are significant limitations in high speed frequency measurement.
High resolution measurement can be realized by adopting analog interpolation expansion, but the analog interpolation method has poor stability because an analog circuit has higher sensitivity to the working temperature. Meanwhile, the circuit has certain leakage current, so that the capacitor charging output voltage has certain nonlinearity, the measurement precision is greatly influenced, and if the high resolution is achieved, the voltage nonlinearity needs to be accurately calibrated. In addition, due to the inherent charge-discharge time limit of the analog circuit, the time interval of single measurement of the analog interpolation method cannot be too small, so that the application is greatly limited in the field of high-speed short-sampling interval measurement.
The vernier method needs to use standard clock frequency and vernier clock frequency as high as possible, and needs complex high-resolution frequency control technology to generate standard counting clock and vernier clock, and strictly control the frequency and phase of all clocks, the circuit is complex, and the realization difficulty is high. Meanwhile, when the interval between the edge of the counting gate and the rising edge of the counting clock is small, a certain dead zone interval exists in the starting and the closing of the vernier counter under the limitation of the response time of the device, so that the minimum tracking time is limited to a certain extent.
The digital interpolation technology is adopted to construct a delay chain of serial delay and parallel counting to finish the measurement of the error pulse signal, and the measurement has no charge-discharge link required by analog interpolation, so that the speed of interpolation expansion can be further improved. In order to meet the requirement of continuous no-dead-zone measurement, a mode of alternately working symmetrical two measuring channels is adopted, and the two channels respectively pass through complementary two gate synchronous signals G generated by a gate high-speed synchronous unitsand/GsControl, in order to ensure the accurate synchronization of each unit and each gate can accurately count events and time, the time width of the gate still cannot be too small, and the prior artThe highest level of the technology, the minimum gate width is 100ns, and the frequency switching time cannot be measured quickly and accurately for the broadband quick frequency hopping signal.
(3) In the conventional implementation scheme, because the event signal and the time signal are asynchronous signals, the synchronous gate is completely synchronous with the event signal, and if the edges of the event signal and the time signal are very close to each other, the time counting unit and the error pulse extracting unit inevitably have +/-1 error and time sequence error in the process of synchronizing with the gate signal.
(4) And the prior art scheme is complex to realize, resulting in higher cost of the prior art scheme.
Disclosure of Invention
Compared with the prior art, the invention has simple structure, simplifies the system of a gate generation unit, a gate synchronization unit, a time counting unit, an event counting unit, an error extraction unit and the like, and greatly simplifies the design difficulty and complexity of circuits and time sequences.
The technical scheme of the invention is realized as follows:
a wideband modulation domain measurement system comprising: the device comprises a signal synchronization unit, a logic selection unit, a first tap delay line multi-path delay unit, a second tap delay line multi-path delay unit, a first data buffer unit, a second data buffer unit and a processing unit;
the signal synchronization unit receives a detected signal as an input, and an output signal is connected with the logic selection unit; the logic selection unit receives an output signal of the signal synchronization unit as an input, and the output signal is connected with the first tap delay line multi-path delay unit and the second tap delay line multi-path delay unit; the first tap delay line multi-path delay unit is connected with the first data buffer unit; the second tap delay line multi-path delay unit is connected with the second data buffer unit; the outputs of the first data buffer unit and the second data buffer unit are connected with the processing unit.
Optionally, the signal synchronization unit is implemented by a programmable logic chip, and when the measurement is started, a rising edge of a measured signal synchronously generates a timing control signal and sends the timing control signal to the logic selection unit; according to the requirement of measurement resolution, M signal periods are selected at intervals, and a synchronous signal is output, wherein M is more than or equal to 1.
Optionally, the logic selection unit receives an output signal of the signal synchronization unit, and sends the output signal to the first tap delay line multi-path delay unit and the second tap delay line multi-path delay unit through logic selection and control;
at first START-up measurement, START and STOP of the first tapped delay line multi-way delay unit1START and STOP generated by signal using logic selection unit1(ii) a After the first tap delay line multi-path delay unit finishes 1 measurement, when the measurement is started for the second time, STOP is used2N-2And STOP2N-1As START and STOP1(ii) a On the third start-up measurement, STOP is used3N-4And STOP3N-3As START and STOP1......；
START and STOP of multi-path delay unit of second tap delay line1STOP of multipath delay unit with first tap delay lineN-1And STOPNThe same signal is shared to form a cascade structure.
Optionally, the first tapped delay line multi-path delay unit and the second tapped delay line multi-path delay unit are used for extracting the START signal and the STOP signal1、STOP2......STOPNThe delay state of the two phases, and further calculating the delay time between the two phases;
the first tap delay line multi-path delay unit and the second tap delay line multi-path delay unit are in an alternative working state, in order to ensure that when one tap delay line multi-path delay unit works, the other tap delay line multi-path delay unit can be correctly latched and output and timely RESET, the tap delay line multi-path delay unit also synchronously outputs a LOCK signal for latching data by the data buffer unit, and after the data is latched, a RESET signal is also generated inside the tap delay line multi-path delay unit and is used for resetting the internal state of the tap delay line multi-path delay unit.
Optionally, the first data buffer unit and the second data buffer unit are responsible for latching the measurement data of the first tap delay line multi-path delay unit and the second tap delay line multi-path delay unit in time.
Optionally, the processing unit is responsible for interacting with the first data buffer unit and the second data buffer unit, reading the measurement data through the high-speed interface, and performing final operation, processing and display on the data.
Optionally, in the wideband modulation domain measurement system, a presorting unit is added to the front end.
The invention also provides a broadband modulation domain measuring method, which utilizes the measuring system to measure the modulation domain of the measured signal.
The invention has the beneficial effects that:
(1) the structure is simple, the system of the gate generation unit, the gate synchronization unit, the time counting unit, the event counting unit, the error extraction unit and the like is simplified, and the design difficulty and complexity of a circuit and a time sequence are greatly simplified;
(2) the gate generating unit, the gate synchronizing unit, the time counting unit, the error extracting unit and the like are not needed, the event signals are completely synchronized, the problem of synchronization errors of asynchronous signals such as gate signals, event signals, time signals and the like is solved, the work is more stable, and the reliability is high;
(3) the circuit and the time sequence are simplified, the cost is low, the realization by a programmable device is easy, a special logic chip is easy to customize, the integration level is high, and the confidentiality is good.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a timing diagram of zero idle count operation;
FIG. 2 is a schematic block diagram of an exemplary system for modulation domain measurement;
FIG. 3 is a functional block diagram of another exemplary system for modulation domain measurement;
FIG. 4 is a digital interpolation schematic;
FIG. 5 is a schematic diagram of a wideband modulation domain measurement system of the present invention;
FIG. 6 is a timing diagram of the signal synchronization unit according to the present invention;
FIG. 7 is a schematic diagram of a multi-path delay cell of the tapped delay line of the present invention;
FIG. 8 is a diagram of a multi-path delay cell package for a tapped delay line according to the present invention;
fig. 9 is a schematic diagram of the basic structure of the tapped delay line circuit of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in fig. 5, the present invention provides a wideband modulation domain measurement system, which includes: the device comprises a signal synchronization unit, a logic selection unit, a tap delay line multi-path delay unit, a data buffer unit and a processing unit.
The signal synchronization unit receives a detected signal as an input, and an output signal of the signal synchronization unit is connected with the logic selection unit; the logic selection unit receives an output signal of the signal synchronization unit as an input, and the output signal is connected with the first tap delay line multi-path delay unit and the second tap delay line multi-path delay unit; the first tap delay line multi-path delay unit is connected with the first data buffer unit; the second tap delay line multi-path delay unit is connected with the second data buffer unit; the outputs of the first data buffer unit and the second data buffer unit are connected with the processing unit.
The signal synchronization unit receives a signal to be measured as input, and when measurement is started, a timing control signal is synchronously generated by the rising edge of the signal to be measured and sent to the logic selection unit.
The signal synchronization unit is realized by a programmable logic chip, the time sequence is shown in fig. 6, signals such as START, LOCK, RESET, STOP and the like are synchronously generated by the rising edge of the detected signal, and the signals are sent to the logic selection unit. The M signal periods per interval can be selected according to the requirement of measurement resolution, and a synchronous signal is output, wherein the minimum M can be 1. If STOP1Time interval from START is T1，STOP2Time interval from START is T2，STOP3Time interval from START is T3.., then f1＝M/T1，f2＝M/(T2-T1)，f3＝M/(T3-T2)......
The logic selection unit is implemented by a programmable logic chip, receives the output signal of the signal synchronization unit, and the "logic selection" of the dashed box is a part of the logic selection unit, which is drawn outside to more clearly illustrate the sources of the START and STOP1 signals and the cascade relationship between the first tapped delay line multi-path delay unit and the second tapped delay line multi-path delay unit. At first START-up measurement, START and STOP of the first tapped delay line multi-way delay unit1START and STOP generated by signal using logic selection unit1(ii) a After the first tap delay line multi-path delay unit finishes 1 measurement, when the measurement is started for the second time, STOP is used2N-2And STOP2N-1As START and STOP1(ii) a On the third start-up measurement, STOP is used3N-4And STOP3N-3As START and STOP1....... START and STOP of multi-path delay unit of first tap delay line1STOP of multi-path delay unit with second tap delay lineN-1And STOPNThe same signal is shared to form a cascade structure. The cascade mode can eliminate the system error between the multipath delay units of the two tap delay lines.
The first tap delay line multi-path delay unit and the second tap delay line multi-path delay unit are used for extracting START signals and STOP signals1、STOP2......STOPNIs prolonged betweenThe late state, and hence the delay time between them. The first tap delay line multi-path delay unit and the second tap delay line multi-path delay unit are in an alternative working state, in order to ensure that when one tap delay line multi-path delay unit works, the other tap delay line multi-path delay unit can be correctly latched and output and timely RESET, the tap delay line multi-path delay unit also synchronously outputs a LOCK signal for latching data by the data buffer unit, and after the data is latched, a RESET signal is also generated inside the tap delay line multi-path delay unit and is used for resetting the internal state of the tap delay line multi-path delay unit. The relative timing is explicitly given in fig. 6.
The first tapped delay line multi-path delay unit and the second tapped delay line multi-path delay unit can be realized by adopting a programmable logic chip or a special chip, as shown in fig. 7, the tapped delay line multi-path delay unit comprises a multi-path cascaded tapped delay line circuit structure, and the structure supports the same initial signal and a plurality of ending signals. The above multi-path cascaded tapped delay line circuit structure is packaged into a module, and the output latch signal is considered, so that the tapped delay line multi-path delay unit can be obtained, as shown in fig. 8.
The tap time-delay structure is a basic realization structure of digital interpolation, is a full-digital high-precision time interval measurement mode, and uses the phenomenon that time delay action is generated certainly when an electric signal is transmitted through an electronic element and a connecting wire as a means for measuring time interval. Fig. 9 is a schematic diagram of the basic structure of a tapped delay line circuit.
The tapped delay line circuit uses logic buffer gates whose output logic states change with input as basic elements for delay, each delay element being followed by a flip-flop. The START pulse signal START is input to the serial input of the first delay cell, and since it takes time for the signal to pass through each logic gate and the connecting wire, the signal will pass through each logic buffer gate in turn, so that the output of each buffer gate will change its output state in turn at intervals of the delay time τ. When the rising edge of the STOP signal STOP comes, each flip-flop records how many logic buffer gates have changed their states until then, and converts the number of delay units with changed states into digital signals through the internal circuit for output. The time interval to be measured can be obtained by the following formula:
T＝m×τ (2)
in the formula, T is the time interval between the rising edge of the START signal START and the rising edge of the STOP signal STOP, and m is the number of delay cells with changed states. The delay time of the delay unit, i.e. the minimum time interval that the tapped delay line circuit can resolve, determines the time interval measurement resolution, and the number of delay units multiplied by the delay time of each unit determines the delay time measurement range.
In fig. 5, the first data buffer unit and the second data buffer unit are responsible for latching the measurement data of the first tap delay line multi-path delay unit and the second tap delay line multi-path delay unit in time.
The processing unit is responsible for interacting with the data buffer unit, reading the measurement data through the high-speed interface, and performing final operation, processing and display on the data.
On the basis of the embodiment shown in fig. 5, a pre-frequency-division unit is added at the front end of the wideband modulation domain measurement system, so that the frequency measurement range can be further expanded, and ultra-wideband frequency measurement can be realized.
Based on the broadband modulation domain measurement system, the invention also provides a broadband modulation domain measurement method, and the measurement principle is described in detail in the measurement system and is not described again here.
The broadband modulation domain measurement system has the following advantages:
(1) the system has the advantages that the structure of the block diagram is simple, the system such as the gate generation unit, the gate synchronization unit, the time counting unit, the event counting unit, the error extraction unit and the like is simplified, and the design difficulty and complexity of a circuit and a time sequence are greatly simplified.
(2) When the signal synchronization unit generates the START signal and the STOP signal, M signal periods at intervals can be selected according to the requirement of measurement resolution, one synchronization signal is output, the minimum M value can be 1, the sampling interval of the frequency signal can be greatly reduced, and the requirement of measuring the frequency switching time of the broadband rapid frequency hopping signal is met.
(3) In the conventional implementation scheme, because the event signal and the time signal are asynchronous signals, the synchronous gate is completely synchronous with the event signal, and if the edges of the event signal and the time signal are very close to each other, the time counting unit and the error pulse extracting unit inevitably have +/-1 error and time sequence error in the process of synchronizing with the gate signal. According to the scheme, a gate generation unit, a gate synchronization unit, a time counting unit, an error extraction unit and the like are not needed, the synchronization is completely realized by event signals, the problem of synchronization errors of asynchronous signals is solved, the work is more stable, and the reliability is high.
(4) And for chips with the multi-path structure of the tapped delay line produced by other manufacturers, the chip can be easily upgraded and replaced by referring to the schematic block diagram and the timing diagram of the invention, and the expansibility is good.
(5) The technical scheme of the invention has the advantages of simple structure, simplified circuit and time sequence and low cost.
(6) The method is easy to realize by using a programmable device and customize a special logic chip, and has high integration level and good confidentiality.
(7) On the basis of the principle block diagram, the front end is additionally provided with the pre-frequency-division unit, so that the frequency measurement range can be further expanded, and ultra-wideband frequency measurement is realized.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
Claims (6)
1. A wideband modulation domain measurement system, comprising: the device comprises a signal synchronization unit, a logic selection unit, a first tap delay line multi-path delay unit, a second tap delay line multi-path delay unit, a first data buffer unit, a second data buffer unit and a processing unit;
the signal synchronization unit receives a detected signal as an input, and an output signal is connected with the logic selection unit; the logic selection unit receives an output signal of the signal synchronization unit as an input, and the output signal is connected with the first tap delay line multi-path delay unit and the second tap delay line multi-path delay unit; the first tap delay line multi-path delay unit is connected with the first data buffer unit; the second tap delay line multi-path delay unit is connected with the second data buffer unit; the outputs of the first data buffer unit and the second data buffer unit are connected with the processing unit;
the logic selection unit receives an output signal of the signal synchronization unit, and sends the output signal to the first tap delay line multi-path delay unit and the second tap delay line multi-path delay unit through logic selection and control;
at first START-up measurement, START and STOP of the first tapped delay line multi-way delay unit1START and STOP generated by signal using logic selection unit1(ii) a After the first tap delay line multi-path delay unit finishes 1 measurement, when the measurement is started for the second time, STOP is used2N-2And STOP2N-1As START and STOP1(ii) a On the third start-up measurement, STOP is used4N-4And STOP4N-3As START and STOP1；
START and STOP of multi-path delay unit of second tap delay line1STOP of multipath delay unit with first tap delay lineN-1And STOPNThe same signal is shared to form a cascade structure;
the signal synchronization unit is realized by a programmable logic chip, and when the measurement is started, a measured signal rising edge synchronously generates a time sequence control signal and sends the time sequence control signal to the logic selection unit; according to the requirement of measuring resolution, M signal periods are selected at intervals, a synchronous signal is output, M is larger than or equal to 1, N cascaded tapped delay line circuits are respectively arranged in the first tapped delay line multi-path delay unit and the second tapped delay line multi-path delay unit, and the first tapped delay line multi-path delay unit and the second tapped delay line multi-path delay unit support the same initial signal and a plurality of end signals.
2. The wideband modulation domain measurement system of claim 1, wherein the first tapped delay line multi-way delay unitMultiple delay unit with element and second tap delay line for extracting START signal and STOP1、STOP2To STOPNThe delay state between cycles, and then calculate the delay time between them;
the first tap delay line multi-path delay unit and the second tap delay line multi-path delay unit are in an alternative working state, in order to ensure that when one tap delay line multi-path delay unit works, the other tap delay line multi-path delay unit can be correctly latched and output and timely RESET, the tap delay line multi-path delay unit in a non-working state synchronously outputs a LOCK signal for latching data by the data buffer unit, and after the data are latched, a RESET signal is generated in the tap delay line multi-path delay unit in the non-working state and is used for resetting the internal state of the tap delay line multi-path delay unit.
3. The wideband modulation domain measurement system according to claim 1, wherein the first and second data buffer units are responsible for latching the measurement data of the first and second tapped delay line multi-way delay units in time.
4. The wideband modulation domain measurement system according to claim 1, wherein the processing unit is responsible for interacting with the first and second data buffer units, reading measurement data through a high speed interface, and for performing final operations, processing and displaying on the data.
5. The wideband modulation domain measurement system according to any one of claims 1 to 4, wherein a pre-frequency division unit is added at a front end of the wideband modulation domain measurement system.
6. A method for measuring the modulation domain of a broadband, characterized in that the modulation domain measurement is performed on a signal to be measured by using the measuring system of any one of claims 1 to 5.
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