TWI572146B - Offset time cancellation method and system applied to time measurement of pulse shrinking - Google Patents

Description

Offset time elimination method and system suitable for pulse reduction method time measurement

The present invention relates to an offset time cancellation method suitable for pulse reduction method and its system, and more particularly to a time-to-digital method for eliminating the offset time of the pulse reduction method time measurement system. The time-to-digital converter (TDC) structure mainly uses a built-in delay line to add a module and a time reduction module, and additionally adds a time interval to a time to digital converter. The pulse is reduced, and then the extra delay time is removed, so that the time width to be tested can be completely converted into the corresponding digital code, so as to solve the problem that the conventional pulse reduction method has an undesired offset time to the digital converter and cannot measure the pulse width to be tested. Disadvantages of full digital code conversion, the system of the present invention can also verify unnecessary offset time elimination by using the full digitized cyclic pulse reduction time-to-digital converter of Xilinx's field programmable logic gate array chip. Widening the time measurement range and improving the accuracy of the characteristics.

According to the high-performance time-to-digital converter (TDC), it is the core component of the precision instrumentation system, physical equipment or timing circuitry, in which the physical quantity system is first converted into a Time interval, which is digitized via a time-to-digital converter (TDC) to obtain a digital code that can be stored and processed for subsequent digital signal processing; time-to-digital converter (TDC) is a semiconductor Process The technology is prepared to meet the requirements of high resolution, low cost, and precise time interval digitization such as low power consumption; there are many systems such as parallel scaled delay elements and Vernier delay lines. Or time amplification is studied to improve the resolution to achieve circuit complexity and area up to the deep sub-gate resolution.

Pulse reduction technique is one of the most commonly used methods to achieve deep gate delay resolution. The concept is to form a pulse of width t _in where t _in is equal to the start of signal ( t ₁ ) and the end of signal ( t ₂ ). The time difference, however, regardless of the pulse reduction method used, the main disadvantage is that the pulse width t _{in is} too short and suddenly disappears, so that the normal time reduction can no longer be performed, and the pulse width less than the offset time cannot be measured. Measurement, equivalent to the time measurement range is limited; see the sixth and seventh diagrams, the system construction block diagram for the traditional time to digital converter, and the traditional pulse reduction mechanism operation diagram, where the input signal is reduced by the traditional pulse The unit (61) is reduced with a series of conventional cyclic delay lines (62), and the reduced pulse width of each unit is a pulse-shrinking amount, referred to as R , which disappears completely at the end. The problem of shift time comes from the limitation of the logic gate drive capability. Therefore, when the pulse width is too small, the pulse cannot be smoothly converted from the high state (logic 1) to the low state ( Logic 0), or vice versa, is that the pulse will suddenly disappear, and its time width cannot be completely converted into the corresponding digital code, that is, the measurement range is limited and the measurement range is limited; Referring to the eighth figure, the schematic diagram of the relationship between the resolution of the conventional pulse reduction time to the digital converter and the pulse width is shown. The digital code n of the system is: Where t _offset is the offset time. Since there is an offset time in the above formula, the time t _{in to} be measured is not completely converted; therefore, in order to effectively improve the offset time in the pulse reduction time measurement problem, and keep the time to the digital position The low area and low power loss characteristics of the converter (TDC), how to effectively eliminate the problem caused by the offset time measurement by the pulse reduction method, is still the developer of today's time to digital converter (TDC) or Researchers need to continue to work hard to overcome and solve important issues.

Now, the inventor is considering that the above-mentioned conventional time-to-digital converter (TDC) suddenly disappears due to the excessively small pulse width, that is, there is an offset time, so that it is impossible to perform normal time reduction measurement and the like, and thus It is a tireless spirit and is supplemented by its rich professional knowledge and years of practical experience, and the invention has been developed accordingly.

The main object of the present invention is to provide an offset time cancellation system suitable for pulse reduction time measurement and a method thereof, and more particularly to a time to digital converter for eliminating the offset time of a pulse reduction method time measurement system ( The TDC) structure mainly increases the module and time reduction module by adding a delay line, and additionally adds a time interval to a time-to-digital converter for pulse reduction, and then removes additional delay time. The invention can completely convert the time width to be tested into a corresponding digital code, and achieve the disadvantage that the conventional pulse reduction method time to the digital converter has an undesired offset time and the pulse width to be tested cannot be completely converted into a digital code. The system can also verify the unnecessary offset time elimination by using the full digitized cyclic pulse reduction method time-to-digital converter of Xilinx's field programmable logic gate array chip, effectively achieving the widening time measurement range and improving accuracy. Characteristics.

In order to achieve the above-mentioned implementation object, the inventors have proposed an offset time cancellation method suitable for pulse reduction time measurement, which includes at least the following steps: First, sequentially generating two pulses t ₁ and t ₂ , wherein the time difference between the two pulses It is a time width t _{in to} be measured; then, a time interval t _{d is} additionally generated; and the time width t _in to be measured is added to the time interval t _d to form an input pulse t _p and input to a time to a digit In the converter (TDC); thereafter, using a time-to-digital converter (TDC) to pulse down the input pulse t _p and output an output pulse t _out ; finally, comparing the pulse width of the output pulse t _out with the time interval t _d Correspondence relationship, in order to complete the offset time elimination for the pulse reduction method time measurement.

Pulses as described above is suitable for reducing shift time measuring method of Time cancellation method, wherein when the ratio of the output pulse of the pulse width t _out is greater than the time interval t _{d, the} time is repeatedly performed to digital converter (TDC) pulse reduction Until the pulse width of the output pulse t _out is equal or less than the time interval t _d , outputting a stop count signal causes a counter to stop counting.

In addition, the present invention further provides an offset time cancellation system suitable for pulse reduction time measurement, which includes at least a time to digital converter (TDC), a time adder, and a time reduction module. (time substractor), and a counter; the time-to-digital converter (TDC) is a series of pulse reduction units (PSUs) connected in series with a cyclic delay line (pulse reduction line). The unit (PSU) is composed of two series connected NAND gates, and the cyclic delay line is formed by a plurality of NOT gates connected in series; the time increasing module is composed of a first delay line ( The first delay line is formed in series with an XNOR gate, wherein the first delay line is formed by a plurality of reverse gates connected in series, and the output of the mutually exclusive or gate is electrically connected to the pulse reduction unit. One of them is opposite to the input end of the gate; the time reduction module is composed of a pulse width detector (PWD) and an AND gate, wherein the pulse width detector is composed of a plurality of series connected D -type positive D-type flip flop (DFF) and one Delay line configuration, and the input terminal of the pulse width of the detector line is electrically connected to the output terminal of the delay line loop; electrically connected to a counter-based time to reduce the output of the module.

The offset time cancellation system suitable for pulse reduction time measurement as described above, wherein the output end of the cyclic delay line is further electrically connected to the input end of the pulse reduction unit.

Offset time cancellation system for pulse reduction time measurement as described above The output end of the cyclic delay line can be further electrically connected to the input of the time reduction module and the gate.

An offset time cancellation system suitable for pulse reduction time measurement as described above, wherein the pulse width detector is composed of three D-type flip-flops connected in series and a second delay line.

An offset time cancellation system suitable for pulse reduction time measurement as described above, wherein the first delay line and the second delay line have the same structure.

The offset time cancellation system suitable for pulse reduction time measurement as described above, wherein the offset time cancellation system suitable for pulse reduction time measurement can be performed by means of a Field Programmable Gate Array (Field Programmable Gate Array). FPGA) wafers are built.

Therefore, the offset time elimination method and the system thereof applicable to the pulse reduction method time measurement method of the present invention are designed by circuits such as a time increasing module and a pulse width detector each having a simple type delay line built therein. Eliminate unnecessary offset time by adding extra time and then deducting the time. The extra time must be greater than the offset time. Without complicated and expensive calibration mechanism, the widening time measurement can be effectively achieved. The advantage of the range and the improvement of the accuracy; in addition, the offset time elimination method and system for the pulse reduction method of the present invention generate additional delay time by the time increase module, and add up to the time width to be tested Forming an input pulse, operating through a time-to-digital converter with a cyclic pulse reduction function to generate an output signal, and finally detecting a previously added time width through a pulse width detector of the time reduction module, when the time width of the output signal is less than The increased time width, there will be a cutoff signal to close the output signal and continue to input to the counter, which is equivalent to removing The external delay time is completely converted into the corresponding digital code by the time width to be tested, which effectively solves the problem that the conventional pulse reduction method has an undesired offset time to the digital converter, and cannot completely convert the pulse width to be tested into a digital code conversion. Disadvantages; finally, the present invention is applicable to pulse reduction time The measurement offset time cancellation system and method thereof can verify unnecessary offset time elimination by using the full digitized cyclic pulse reduction time-to-digital converter of Xilinx's field programmable logic gate array (FPGA) chip. Effectively achieve the characteristics of widening time measurement range and improving accuracy.

(1) ‧ ‧ time increase module

(11) ‧‧‧First delay line

(12) ‧‧‧ Mutually exclusive or gate

(2) ‧ ‧ time to digital converter

(21) ‧‧‧pulse reduction unit

(22) ‧‧‧Cyclic delay line

(3) ‧ ‧ time reduction module

(31)‧‧‧ Pulse width detector

(32)‧‧‧ and gate

(4) ‧ ‧ counter

(61) ‧‧‧Traditional Pulse Reduction Unit

(62) ‧‧‧Traditional cycle delay line

(S1)‧‧‧Step one

(S2)‧‧‧Step 2

(S3) ‧ ‧ Step 3

(S4)‧‧‧Step four

(S5) ‧ ‧ step five

The first figure: the flow chart of the steps of the method for eliminating the offset time of the pulse reduction method for measuring the time of the invention

Second: The system configuration block diagram of a preferred embodiment of the present invention is applicable to an offset time elimination system for pulse reduction time measurement

Third: The present invention is applicable to the operation of the pulse reduction mechanism of a preferred embodiment of the offset time elimination system for pulse reduction method

Fourth: The internal structure of the pulse width detector of the preferred embodiment of the present invention is applicable to the offset time elimination method of the pulse reduction method

Fig. 5 is a diagram showing the relationship between the resolution and the pulse width of a preferred embodiment of the offset time elimination system for pulse reduction method

Figure 6: System configuration block diagram of traditional time to digital converter

Figure 7: Schematic diagram of the operation of the traditional pulse reduction mechanism

Figure 8: Schematic diagram of the relationship between the resolution of the traditional pulse reduction time to the digital converter and the pulse width

The object of the present invention and its structural design and advantages will be explained in the light of the preferred embodiments shown in the following drawings, so that the reviewing committee can have a more in-depth and specific understanding of the present invention.

First, please refer to the first figure, which is a flow chart of the steps of the method for eliminating the offset time of the pulse reduction method for the time measurement of the pulse reduction method, and the offset time elimination method suitable for the time measurement of the pulse reduction method mainly includes The following steps are performed: Step 1 (S1): sequentially generating two pulses t ₁ and t ₂ , wherein the time difference between the two pulses is a time width t _{in to} be measured; in a preferred embodiment of the present invention, mainly by The pulse generator of the Standard Research DG535 digital delay/pulse generator generates a pulse; step 2 (S2): additionally generates a time interval t _d ; in a preferred embodiment of the invention, a time-increasing module is mainly used ( 1) The built-in first delay line (11) generates a time interval t _d ; Step 3 (S3): sums the time width t _in to be measured and the time interval t _d to form an input pulse t _p and input to a time Into a digital converter (2); in a preferred embodiment of the invention, the input pulse t _p = t _in + t _d and input by the time increasing module (1) to the time to digital converter (2) Input; step four (S4): use time to digital conversion (2) the input pulse to reduce a pulse t _p, and outputs an output pulse t _out; in one preferred embodiment of the invention, the time-to-digital converter (2) by a pulse train reduction means (21) with a The cyclic delay line (22) is connected in series, the pulse reduction unit (21) is composed of two series-connected anti-gates (211), and the cyclic delay line (22) is formed by connecting a plurality of reverse gates (221) in series. The two anti-gates (211) constituting the pulse reduction unit (21) are inhomogeneous gates to control the reduction of the input pulse by the pulse reduction amount R , and output an output signal t _out to a time reduction module (3); and a step five (S5): Compare the output pulse and the pulse width t of the time _out interval t _d corresponding to the relationship, to accomplish the purpose of the pulse applied to reduce the shift time measuring method of eliminating time; if the ratio When the pulse width of the output pulse t _out is greater than the time interval t _d , the time of step four ( S4 ) is repeatedly performed to the pulse reduction program of the digital converter, when the pulse width of the output pulse t _out is equal to or smaller than the time interval t _d , i.e. the count stop when the measured time is converted into the width t _in Corresponding to the digital code n, i.e. the offset time of the originally present are eliminated; in one preferred embodiment of the present invention, to reduce the use of time-based module (3) of the built-in pulse width detector (31) to detect Outputting the pulse width of the pulse t _out and comparing the width difference with the time interval t _d , if the pulse width of the output pulse t _out is less than the pulse width of the time interval t _d , the pulse width detector ( 31 ) outputs a conversion termination End of conversion (EOC) and through the time reduction module (3) built-in and gate (32) to suspend the operation of the counter (4), and the pulse width of the output pulse t _out is less than the time interval t _d , but still Continue to be reduced by time to digital converter (2) until its width is reduced to offset time t _offset and the pulse disappears, but the number of reductions in this phase is not counted by counter (4), time interval t _d must be offset The time t _{offset is} large, and the offset time elimination method can be successful.

In addition, in order to enable the reviewing committee to have a more in-depth and specific understanding of the present invention, please refer to the second and third figures, which is a preferred embodiment of the offset time eliminating system applicable to the pulse reduction method for time measurement. The system construction block diagram, and the operation diagram of the pulse reduction mechanism, wherein the offset time elimination system suitable for the pulse reduction method time measurement system includes at least: a time to digital converter (2), which is a pulse reduction unit ( 21) is formed in series with a cyclic delay line (22), wherein the pulse reduction unit (21) is composed of two series-connected anti-gates (211), and the cyclic delay line (22) is composed of a plurality of reverse gates ( 221) in series; in a preferred embodiment of the invention, the time to digital converter (2) has the same architecture as a conventional time to digital converter (TDC), wherein the pulse reduction unit (21) is formed. The two anti-gates (211) are non-homogeneous gates to control the reduction of the input pulse by the pulse reduction amount R. The main features are smaller circuit area, ultra-low power consumption, and more power-saving circuits. Operation, etc.; in addition, in this issue In a preferred embodiment, the output end of the cyclic delay line (22) can be further electrically connected to the input end of the pulse reduction unit (21) as an input signal of the pulse reduction unit (21), and the pulse reduction unit ( 21) The other input signal is a reset signal; the time-increasing module (1) is formed by a first delay line (11) connected in series with a mutually exclusive or anti-gate (12). The first delay line (11) is formed by a plurality of reverse gates (111) connected in series, and the output end of the mutually exclusive reverse gate or gate (12) is electrically connected to one of the pulse reduction units (21). The input terminal of 111); in a preferred embodiment of the present invention, the first delay line (11) formed by connecting a plurality of reverse gates (111) in series is used to generate a time interval t _d and then input with the outside world. The time width of the time difference ( t _in ) of the pulse t ₁ and t ₂ is added to the input pulse width t _p , that is, t _p = t _in + t _d , and t _{p is} then mutually exclusive or gated (12) The output terminal is input to the input end of the pulse reduction unit (21) and the gate (211); t _p is cyclically reduced by the time to digital converter (2) to generate an output signal t _out ; a time reduction module ( 3) is a combination of a pulse width detector (31) and a gate (32), wherein the pulse width detector (31) is composed of a plurality of series D -type flip-flops (311) and a second A delay line (312) is formed, wherein the input end of the pulse width detector (31) is electrically connected to the output end of the cyclic delay line (22); in a preferred embodiment of the invention, the pulse width detector (31) ) is used to detect the pulse width of the output signal t _out and compare the width difference with the time interval t _d ; please refer to the fourth figure as shown in the figure, which is suitable for the offset time of the pulse reduction method time measurement A schematic diagram of the internal structure of a pulse width detector according to a preferred embodiment of the system, wherein the pulse width detector (31) is composed of three D -type flip-flops (311) DFF1~DFF3 and a second delay line (312) connected in series. the configuration, a series of three D flip-flop (311) output signal lines for detecting the pulse width t _out, and the second delay line (312) for comparing the output signal lines and the delay time t _out of t _D The pulse width is poor. If the output signal t _{out is} greater than the time interval t _d , the nodes Q1 and Q2 are at a low potential. Conversely, if the input is When the outgoing signal t _{out is} less than the time interval t _d , the end of conversion (EOC) signal output by the pulse width detector (31) is excited and changed from High to Low , and the gate (32) is outputted to output a t. _Out ' stops the operation of the counter (4), therefore, the time reduction module (3) can be regarded as subtracting the extra time interval t _d from the input pulse width t _p to eliminate the offset time; in addition, the time to digital converter (2) The output of the cyclic delay line (22) can be further electrically connected to the input of the time reduction module (3) and the gate (32); further, the second delay built into the pulse width detector (31) The line (312) has the same circuit structure as the first delay line (11) built in the time increasing module (1); and a counter (4), which is an output end of the electrical connection time reduction module (3) .

In addition, since the pulse width detector (31) is used to detect the pulse width of the output signal t _out and compare the width difference with the extra time interval t _d , when the pulse width of the output signal t _out is less than the extra time interval t _At the pulse width of _d , an ETS signal is activated and passed through the AND gate (32) to stop the output signal and continue to input the counter (4), so that the counter (4) stops counting (although the output signal t _out continues) It is reduced), that is, only the time width t _{in to} be measured is converted to the corresponding digital code n , therefore, the digital code system of the offset time elimination system applicable to the pulse reduction time measurement of the present invention can be expressed by the following relationship : Compared with the traditional time-to-digital converter digital code, the digital code output of the present invention does not have an offset time, and the time width t _in to be tested is completely converted into a corresponding digital code; in other words, the conventional The time-to-digital converter offset time problem has been solved, and the additional time interval of the present invention is consistent with the time of reduction, so that the time to be tested can be completely converted into a corresponding digital code, thereby removing the offset time. (equivalent to increasing the measurement time range), and increasing the accuracy, that is, when the traditional pulse width is reduced to the offset time, the reduction is not a fixed R, but an imminent change, so the last few digits will be inaccurate. Therefore, the accuracy is affected; the offset time elimination system applicable to the pulse reduction time measurement of the present invention can effectively achieve the advantages of widening the dynamic range and improving the accuracy.

Furthermore, please refer to the fifth figure, which is a relationship between the resolution and the pulse width of a preferred embodiment of the offset time elimination system applicable to the pulse reduction method for time measurement, compared with the conventional pulse of the eighth figure. Reduce the time to the resolution and pulse of the digital converter The schematic diagram of the impulse width relationship simulation, the offset time elimination system suitable for the pulse reduction method of the present invention has a high degree of linearity, and is effective for each digit value, thereby achieving an improvement in accuracy.

Furthermore, the offset time cancellation system of the present invention suitable for pulse reduction time measurement can be constructed by means of a field programmable logic gate array (FPGA) chip; in a preferred embodiment of the invention, The pulse time reduction method for measuring the offset time is based on the full digitization cyclic pulse reduction time-to-digital converter of the Xilinx XC3S200AN field programmable logic gate array (FPGA) chip to achieve unnecessary offset time elimination. Effectively achieve the characteristics of widening the measurement time range and improving the accuracy.

It can be seen from the above description that the offset time elimination system and the method thereof suitable for pulse reduction time measurement of the present invention have the following advantages compared with the prior art:

1. The offset time elimination method and system thereof suitable for pulse reduction method time measurement according to the present invention are designed by circuit design such as time increasing module and pulse width detector each having a simple type delay line built therein Add extra time and then deduct the time to eliminate unnecessary offset time. The extra time must be greater than the offset time. Without complicated and expensive calibration mechanism, the widening time measurement range can be effectively achieved. And the advantage of improving accuracy.

2. The offset time elimination method and system for the time reduction measurement of the pulse reduction method of the present invention generate an additional delay time by the time increase module, and form an input pulse with the time width of the test to be measured, through the cycle The time-to-digital converter of the pulse reduction function operates to generate an output signal, and finally detects the previously added time width through the pulse width detector of the time reduction module. When the time width of the output signal is less than the time width of the increase, there is a time The cut-off signal turns off the output signal and continues to input to the counter, which is equivalent to removing the extra delay time, which is completely converted into phase by the time width to be tested. Corresponding digital code effectively solves the shortcomings such as the unsatisfactory offset time of the traditional pulse reduction method to the digital converter and the complete conversion of the pulse width to be tested.

3. The offset time elimination method and system thereof suitable for pulse reduction method time measurement according to the present invention can be fully digitized cyclic pulse reduction method time to digital conversion by Xilinx field programmable logic gate array (FPGA) chip. To verify the unnecessary offset time elimination, effectively achieve the characteristics of widening the time measurement range and improving the accuracy.

In summary, the present invention is applicable to an offset time elimination system for pulse reduction time measurement and a method thereof, and can achieve the intended use efficiency by the above disclosed embodiments, and the present invention has not been disclosed in Before applying, Cheng has fully complied with the requirements and requirements of the Patent Law.爰Issuing an application for a patent for invention in accordance with the law, and asking for a review, and granting a patent, is truly sensible.

The illustrations and descriptions of the present invention are merely preferred embodiments of the present invention, and are not intended to limit the scope of the present invention; those skilled in the art, which are characterized by the scope of the present invention, Equivalent variations or modifications are considered to be within the scope of the design of the invention.

(S1)‧‧‧Step one

(S2)‧‧‧Step 2

(S3) ‧ ‧ Step 3

(S4)‧‧‧Step four

(S5) ‧ ‧ step five

Claims (7)

An offset time elimination method suitable for pulse reduction method time measurement includes the following steps: Step 1: sequentially generating two pulses t ₁ and t ₂ , wherein the time difference of the two pulses is a time width t _{in to} be measured Step 2: additionally generating a time interval t _d ; Step 3: summing the time width t _in to be measured and the time interval t _d to form an input pulse t _p and inputting into a time to digital converter; 4: using the time to digital converter to perform pulse reduction of the input pulse tp, and outputting an output pulse t _out ; and step 5: comparing the pulse width of the output pulse t _out with the time interval t _d , when When the pulse width of the output pulse t _out is greater than the time interval t _d , the time of step 4 is repeatedly performed until the pulse of the digital converter is reduced until the pulse width of the output pulse t _out is equal to or less than the time interval t _d , To accomplish the purpose of offset time cancellation for pulse reduction time measurement. An offset time cancellation system suitable for pulse reduction time measurement includes at least: a time to digital converter formed by a pulse reduction unit and a cyclic delay line connected in series, wherein the pulse reduction unit is Two series of anti-gates are formed, and the cyclic delay line is formed by a plurality of anti-gates connected in series; the module is added at a time by a first delay line and a mutually exclusive or anti-gate in series, wherein The first delay line is formed by a plurality of reverse gates connected in series, and the output end of the mutual exclusion or gate is electrically connected to one of the pulse reduction units and the input end of the gate; The pulse width detector is composed of a plurality of series-connected D -type flip-flops and a second delay line, wherein the pulse width detector is connected to the input terminal of the pulse width detector. Electrically connecting the output end of the cyclic delay line; and a counter electrically connected to the output end of the time reduction module. The offset time cancellation system is applicable to the pulse method for reducing the time measurement as described in claim 2, wherein the output end of the cyclic delay line is further electrically connected to the input end of the pulse reduction unit. The offset time cancellation system is applicable to the pulse reduction time measurement according to the second aspect of the patent application, wherein the output end of the cyclic delay line is further electrically connected to the input end of the time reduction module and the gate. An offset time cancellation system suitable for pulse reduction time measurement as described in claim 2, wherein the pulse width detector is composed of three series-connected D -type flip-flops and the second delay line . An offset time cancellation system suitable for pulse reduction time measurement as described in claim 2, wherein the first delay line and the second delay line have the same structure. An offset time cancellation system suitable for pulse reduction time measurement as described in claim 2, wherein the offset time cancellation system for pulse reduction time measurement is performed by means of a field programmable logic gate array (FPGA) wafers are built.